arch/arm64/boot/dts/marvell/armada-8040-db.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (C) 2016 Marvell Technology Group Ltd.
   4  *
   5  * Device Tree file for Marvell Armada 8040 Development board platform
   6  */
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include "armada-8040.dtsi"
  10
  11 / {
  12         model = "Marvell Armada 8040 DB board";
  13         compatible = "marvell,armada8040-db", "marvell,armada8040",
  14                      "marvell,armada-ap806-quad", "marvell,armada-ap806";
  15
  16         chosen {
  17                 stdout-path = "serial0:115200n8";
  18         };
  19
  20         memory@0 {
  21                 device_type = "memory";
  22                 reg = <0x0 0x0 0x0 0x80000000>;
  23         };
  24
  25         aliases {
  26                 ethernet0 = &cp0_eth0;
  27                 ethernet1 = &cp0_eth2;
  28                 ethernet2 = &cp1_eth0;
  29                 ethernet3 = &cp1_eth1;
  30                 i2c1 = &cp0_i2c0;
  31                 i2c2 = &cp1_i2c0;
  32         };
  33
  34         cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
  35                 compatible = "regulator-fixed";
  36                 regulator-name = "cp0-usb3h0-vbus";
  37                 regulator-min-microvolt = <5000000>;
  38                 regulator-max-microvolt = <5000000>;
  39                 enable-active-high;
  40                 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
  41         };
  42
  43         cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
  44                 compatible = "regulator-fixed";
  45                 regulator-name = "cp0-usb3h1-vbus";
  46                 regulator-min-microvolt = <5000000>;
  47                 regulator-max-microvolt = <5000000>;
  48                 enable-active-high;
  49                 gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
  50         };
  51
  52         cp0_usb3_0_phy: cp0-usb3-0-phy {
  53                 compatible = "usb-nop-xceiv";
  54                 vcc-supply = <&cp0_reg_usb3_0_vbus>;
  55         };
  56
  57         cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus {
  58                 compatible = "regulator-fixed";
  59                 regulator-name = "cp1-usb3h0-vbus";
  60                 regulator-min-microvolt = <5000000>;
  61                 regulator-max-microvolt = <5000000>;
  62                 enable-active-high;
  63                 gpio = <&expander1 0 GPIO_ACTIVE_HIGH>;
  64         };
  65
  66         cp1_usb3_0_phy: cp1-usb3-0-phy {
  67                 compatible = "usb-nop-xceiv";
  68                 vcc-supply = <&cp1_reg_usb3_0_vbus>;
  69         };
  70 };
  71
  72 &spi0 {
  73         status = "okay";
  74
  75         spi-flash@0 {
  76                 compatible = "jedec,spi-nor";
  77                 reg = <0>;
  78                 spi-max-frequency = <10000000>;
  79
  80                 partitions {
  81                         compatible = "fixed-partitions";
  82                         #address-cells = <1>;
  83                         #size-cells = <1>;
  84
  85                         partition@0 {
  86                                 label = "U-Boot";
  87                                 reg = <0 0x200000>;
  88                         };
  89                         partition@400000 {
  90                                 label = "Filesystem";
  91                                 reg = <0x200000 0xce0000>;
  92                         };
  93                 };
  94         };
  95 };
  96
  97 /* Accessible over the mini-USB CON9 connector on the main board */
  98 &uart0 {
  99         status = "okay";
 100         pinctrl-0 = <&uart0_pins>;
 101         pinctrl-names = "default";
 102 };
 103
 104 /* CON6 on CP0 expansion */
 105 &cp0_pcie0 {
 106         phys = <&cp0_comphy0 0>;
 107         phy-names = "cp0-pcie0-x1-phy";
 108         status = "okay";
 109 };
 110
 111 /* CON5 on CP0 expansion */
 112 &cp0_pcie2 {
 113         phys = <&cp0_comphy5 2>;
 114         phy-names = "cp0-pcie2-x1-phy";
 115         status = "okay";
 116 };
 117
 118 &cp0_i2c0 {
 119         status = "okay";
 120         clock-frequency = <100000>;
 121
 122         /* U31 */
 123         expander0: pca9555@21 {
 124                 compatible = "nxp,pca9555";
 125                 pinctrl-names = "default";
 126                 gpio-controller;
 127                 #gpio-cells = <2>;
 128                 reg = <0x21>;
 129         };
 130
 131         /* U25 */
 132         expander1: pca9555@25 {
 133                 compatible = "nxp,pca9555";
 134                 pinctrl-names = "default";
 135                 gpio-controller;
 136                 #gpio-cells = <2>;
 137                 reg = <0x25>;
 138         };
 139
 140 };
 141
 142 /* CON4 on CP0 expansion */
 143 &cp0_sata0 {
 144         status = "okay";
 145
 146         sata-port@0 {
 147                 phys = <&cp0_comphy1 0>;
 148                 phy-names = "cp0-sata0-0-phy";
 149         };
 150         sata-port@1 {
 151                 phys = <&cp0_comphy3 1>;
 152                 phy-names = "cp0-sata0-1-phy";
 153         };
 154 };
 155
 156 /* CON9 on CP0 expansion */
 157 &cp0_usb3_0 {
 158         usb-phy = <&cp0_usb3_0_phy>;
 159         status = "okay";
 160 };
 161
 162 &cp0_comphy4 {
 163         cp0_usbh1_con: connector {
 164                 compatible = "usb-a-connector";
 165                 phy-supply = <&cp0_reg_usb3_1_vbus>;
 166         };
 167 };
 168
 169 /* CON10 on CP0 expansion */
 170 &cp0_usb3_1 {
 171         phys = <&cp0_comphy4 1>;
 172         phy-names = "cp0-usb3h1-comphy";
 173         status = "okay";
 174 };
 175
 176 &cp0_mdio {
 177         status = "okay";
 178
 179         phy1: ethernet-phy@1 {
 180                 reg = <1>;
 181         };
 182 };
 183
 184 &cp0_ethernet {
 185         status = "okay";
 186 };
 187
 188 &cp0_eth0 {
 189         status = "okay";
 190         phy-mode = "10gbase-kr";
 191
 192         fixed-link {
 193                 speed = <10000>;
 194                 full-duplex;
 195         };
 196 };
 197
 198 &cp0_eth2 {
 199         status = "okay";
 200         phy = <&phy1>;
 201         phy-mode = "rgmii-id";
 202 };
 203
 204 /* CON6 on CP1 expansion */
 205 &cp1_pcie0 {
 206         phys = <&cp1_comphy0 0>;
 207         phy-names = "cp1-pcie0-x1-phy";
 208         status = "okay";
 209 };
 210
 211 /* CON7 on CP1 expansion */
 212 &cp1_pcie1 {
 213         phys = <&cp1_comphy4 1>;
 214         phy-names = "cp1-pcie1-x1-phy";
 215         status = "okay";
 216 };
 217
 218 /* CON5 on CP1 expansion */
 219 &cp1_pcie2 {
 220         phys = <&cp1_comphy5 2>;
 221         phy-names = "cp1-pcie2-x1-phy";
 222         status = "okay";
 223 };
 224
 225 &cp1_i2c0 {
 226         status = "okay";
 227         clock-frequency = <100000>;
 228 };
 229
 230 &cp1_spi1 {
 231         status = "okay";
 232
 233         spi-flash@0 {
 234                 compatible = "jedec,spi-nor";
 235                 reg = <0x0>;
 236                 spi-max-frequency = <20000000>;
 237
 238                 partitions {
 239                         compatible = "fixed-partitions";
 240                         #address-cells = <1>;
 241                         #size-cells = <1>;
 242
 243                         partition@0 {
 244                                 label = "Boot";
 245                                 reg = <0x0 0x200000>;
 246                         };
 247                         partition@200000 {
 248                                 label = "Filesystem";
 249                                 reg = <0x200000 0xd00000>;
 250                         };
 251                         partition@f00000 {
 252                                 label = "Boot_2nd";
 253                                 reg = <0xf00000 0x100000>;
 254                         };
 255                 };
 256         };
 257 };
 258
 259 /*
 260  * Proper NAND usage will require DPR-76 to be in position 1-2, which disables
 261  * MDIO signal of CP1.
 262  */
 263 &cp1_nand_controller {
 264         pinctrl-0 = <&nand_pins>, <&nand_rb>;
 265         pinctrl-names = "default";
 266
 267         nand@0 {
 268                 reg = <0>;
 269                 nand-rb = <0>;
 270                 nand-on-flash-bbt;
 271                 nand-ecc-strength = <4>;
 272                 nand-ecc-step-size = <512>;
 273
 274                 partitions {
 275                         compatible = "fixed-partitions";
 276                         #address-cells = <1>;
 277                         #size-cells = <1>;
 278
 279                         partition@0 {
 280                                 label = "U-Boot";
 281                                 reg = <0 0x200000>;
 282                         };
 283                         partition@200000 {
 284                                 label = "Linux";
 285                                 reg = <0x200000 0xe00000>;
 286                         };
 287                         partition@1000000 {
 288                                 label = "Filesystem";
 289                                 reg = <0x1000000 0x3f000000>;
 290                         };
 291                 };
 292         };
 293 };
 294
 295 /* CON4 on CP1 expansion */
 296 &cp1_sata0 {
 297         status = "okay";
 298
 299         sata-port@0 {
 300                 phys = <&cp1_comphy1 0>;
 301                 phy-names = "cp1-sata0-0-phy";
 302         };
 303         sata-port@1 {
 304                 phys = <&cp1_comphy3 1>;
 305                 phy-names = "cp1-sata0-1-phy";
 306         };
 307 };
 308
 309 /* CON9 on CP1 expansion */
 310 &cp1_usb3_0 {
 311         usb-phy = <&cp1_usb3_0_phy>;
 312         status = "okay";
 313 };
 314
 315 /* CON10 on CP1 expansion */
 316 &cp1_usb3_1 {
 317         status = "okay";
 318 };
 319
 320 &cp1_mdio {
 321         status = "okay";
 322
 323         phy0: ethernet-phy@0 {
 324                 reg = <0>;
 325         };
 326 };
 327
 328 &cp1_ethernet {
 329         status = "okay";
 330 };
 331
 332 &cp1_eth0 {
 333         status = "okay";
 334         phy-mode = "10gbase-kr";
 335
 336         fixed-link {
 337                 speed = <10000>;
 338                 full-duplex;
 339         };
 340 };
 341
 342 &cp1_eth1 {
 343         status = "okay";
 344         phy = <&phy0>;
 345         phy-mode = "rgmii-id";
 346 };
 347
 348 &ap_sdhci0 {
 349         status = "okay";
 350         bus-width = <4>;
 351         non-removable;
 352 };
 353
 354 &cp0_sdhci0 {
 355         status = "okay";
 356         bus-width = <8>;
 357         non-removable;
 358 };