1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2018 SolidRun ltd.
4 * Based on Marvell MACCHIATOBin board
6 * Device Tree file for SolidRun's ClearFog GT 8K
9 #include "armada-8040.dtsi"
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/gpio/gpio.h>
15 model = "SolidRun ClearFog GT 8K";
16 compatible = "solidrun,clearfog-gt-8k", "marvell,armada8040",
17 "marvell,armada-ap806-quad", "marvell,armada-ap806";
20 stdout-path = "serial0:115200n8";
24 device_type = "memory";
25 reg = <0x0 0x0 0x0 0x80000000>;
29 ethernet0 = &cp1_eth1;
30 ethernet1 = &cp0_eth0;
31 ethernet2 = &cp1_eth2;
34 v_3_3: regulator-3-3v {
35 compatible = "regulator-fixed";
36 regulator-name = "v_3_3";
37 regulator-min-microvolt = <3300000>;
38 regulator-max-microvolt = <3300000>;
43 v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
44 compatible = "regulator-fixed";
45 gpio = <&cp0_gpio2 15 GPIO_ACTIVE_LOW>;
46 pinctrl-names = "default";
47 pinctrl-0 = <&cp0_xhci_vbus_pins>;
48 regulator-name = "v_5v0_usb3_hst_vbus";
49 regulator-min-microvolt = <5000000>;
50 regulator-max-microvolt = <5000000>;
54 usb3h0_phy: usb3_phy0 {
55 compatible = "usb-nop-xceiv";
56 vcc-supply = <&v_5v0_usb3_hst_vbus>;
59 sfp_cp0_eth0: sfp-cp0-eth0 {
60 compatible = "sff,sfp";
61 i2c-bus = <&cp0_i2c1>;
62 mod-def0-gpio = <&cp0_gpio2 17 GPIO_ACTIVE_LOW>;
63 tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;
64 pinctrl-names = "default";
65 pinctrl-0 = <&cp0_sfp_present_pins &cp1_sfp_tx_disable_pins>;
69 compatible = "gpio-leds";
70 pinctrl-0 = <&cp0_led0_pins
72 pinctrl-names = "default";
73 /* No designated function for these LEDs at the moment */
75 label = "clearfog-gt-8k:green:led0";
76 gpios = <&cp0_gpio2 8 GPIO_ACTIVE_LOW>;
80 label = "clearfog-gt-8k:green:led1";
81 gpios = <&cp0_gpio2 9 GPIO_ACTIVE_LOW>;
87 compatible = "gpio-keys";
88 pinctrl-0 = <&cp0_gpio_reset_pins &cp1_wps_button_pins>;
89 pinctrl-names = "default";
93 label = "Rear Button";
94 gpios = <&cp0_gpio2 7 GPIO_ACTIVE_LOW>;
101 label = "WPS Button";
102 gpios = <&cp1_gpio1 30 GPIO_ACTIVE_LOW>;
104 linux,code = <KEY_WPS_BUTTON>;
111 pinctrl-0 = <&uart0_pins>;
112 pinctrl-names = "default";
122 vqmmc-supply = <&v_3_3>;
126 clock-frequency = <100000>;
127 pinctrl-names = "default";
128 pinctrl-0 = <&cp0_i2c0_pins>;
133 clock-frequency = <100000>;
134 pinctrl-names = "default";
135 pinctrl-0 = <&cp0_i2c1_pins>;
142 * [0-31] = 0xff: Keep default CP0_shared_pins:
143 * [11] CLKOUT_MPP_11 (out)
144 * [23] LINK_RD_IN_CP2CP (in)
145 * [25] CLKOUT_MPP_25 (out)
146 * [29] AVS_FB_IN_CP2CP (in)
147 * [32, 33, 34] pci0/1/2 reset
148 * [35-38] CP0 I2C1 and I2C0
149 * [39] GPIO reset button
150 * [40,41] LED0 and LED1
151 * [43] 1512 phy reset
152 * [47] USB VBUS EN (active low)
154 * [49] SFP+ present signal
160 * [55] Micro SD card detect
164 cp0_pci0_reset_pins: pci0-reset-pins {
165 marvell,pins = "mpp32";
166 marvell,function = "gpio";
169 cp0_pci1_reset_pins: pci1-reset-pins {
170 marvell,pins = "mpp33";
171 marvell,function = "gpio";
174 cp0_pci2_reset_pins: pci2-reset-pins {
175 marvell,pins = "mpp34";
176 marvell,function = "gpio";
179 cp0_i2c1_pins: i2c1-pins {
180 marvell,pins = "mpp35", "mpp36";
181 marvell,function = "i2c1";
184 cp0_i2c0_pins: i2c0-pins {
185 marvell,pins = "mpp37", "mpp38";
186 marvell,function = "i2c0";
189 cp0_gpio_reset_pins: gpio-reset-pins {
190 marvell,pins = "mpp39";
191 marvell,function = "gpio";
194 cp0_led0_pins: led0-pins {
195 marvell,pins = "mpp40";
196 marvell,function = "gpio";
199 cp0_led1_pins: led1-pins {
200 marvell,pins = "mpp41";
201 marvell,function = "gpio";
204 cp0_copper_eth_phy_reset: copper-eth-phy-reset {
205 marvell,pins = "mpp43";
206 marvell,function = "gpio";
209 cp0_xhci_vbus_pins: xhci0-vbus-pins {
210 marvell,pins = "mpp47";
211 marvell,function = "gpio";
214 cp0_fan_pwm_pins: fan-pwm-pins {
215 marvell,pins = "mpp48";
216 marvell,function = "gpio";
219 cp0_sfp_present_pins: sfp-present-pins {
220 marvell,pins = "mpp49";
221 marvell,function = "gpio";
224 cp0_tpm_irq_pins: tpm-irq-pins {
225 marvell,pins = "mpp50";
226 marvell,function = "gpio";
229 cp0_sdhci_pins: sdhci-pins {
230 marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
232 marvell,function = "sdio";
237 pinctrl-names = "default";
238 pinctrl-0 = <&cp0_pci0_reset_pins>;
239 reset-gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
246 gpios = <1 GPIO_ACTIVE_HIGH>;
252 gpios = <2 GPIO_ACTIVE_LOW>;
258 gpios = <21 GPIO_ACTIVE_LOW>;
270 phy-mode = "10gbase-kr";
271 managed = "in-band-status";
272 phys = <&cp0_comphy2 0>;
273 sfp = <&sfp_cp0_eth0>;
279 pinctrl-names = "default";
280 pinctrl-0 = <&cp0_sdhci_pins>;
282 vqmmc-supply = <&v_3_3>;
294 * [7] CP1 SPI0 CSn1 (FXS)
295 * [8] CP1 SPI0 CSn0 (TPM)
296 * [9.11]CP1 SPI0 MOSI/MISO/CLK
297 * [13] CP1 SPI1 MISO (TDM and SPI ROM shared)
298 * [14] CP1 SPI1 CS0n (64Mb SPI ROM)
299 * [15] CP1 SPI1 MOSI (TDM and SPI ROM shared)
300 * [16] CP1 SPI1 CLK (TDM and SPI ROM shared)
301 * [24] Topaz switch reset
305 * [29] CP0 10G SFP TX Disable
307 * [31] Front panel button
310 cp1_spi1_pins: spi1-pins {
311 marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
312 marvell,function = "spi1";
315 cp1_switch_reset_pins: switch-reset-pins {
316 marvell,pins = "mpp24";
317 marvell,function = "gpio";
320 cp1_ge_mdio_pins: ge-mdio-pins {
321 marvell,pins = "mpp27", "mpp28";
322 marvell,function = "ge";
325 cp1_sfp_tx_disable_pins: sfp-tx-disable-pins {
326 marvell,pins = "mpp29";
327 marvell,function = "gpio";
330 cp1_wps_button_pins: wps-button-pins {
331 marvell,pins = "mpp30";
332 marvell,function = "gpio";
337 pinctrl-0 = <&cp0_pci1_reset_pins>;
342 pinctrl-names = "default";
343 pinctrl-0 = <&cp1_ge_mdio_pins>;
346 ge_phy: ethernet-phy@0 {
348 * LED1 - on: link, blink: activity
350 marvell,reg-init = <3 16 0 0x1017>;
352 pinctrl-names = "default";
353 pinctrl-0 = <&cp0_copper_eth_phy_reset>;
354 reset-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
355 reset-assert-us = <10000>;
359 compatible = "marvell,mv88e6085";
361 pinctrl-names = "default";
362 pinctrl-0 = <&cp1_switch_reset_pins>;
363 reset-gpios = <&cp1_gpio1 24 GPIO_ACTIVE_LOW>;
366 #address-cells = <1>;
372 phy-handle = <&switch0phy0>;
378 phy-handle = <&switch0phy1>;
384 phy-handle = <&switch0phy2>;
390 phy-handle = <&switch0phy3>;
396 ethernet = <&cp1_eth2>;
401 #address-cells = <1>;
404 switch0phy0: switch0phy0@11 {
408 switch0phy1: switch0phy1@12 {
412 switch0phy2: switch0phy2@13 {
416 switch0phy3: switch0phy3@14 {
432 phys = <&cp1_comphy3 1>;
438 phy-mode = "2500base-x";
439 phys = <&cp1_comphy5 2>;
447 pinctrl-names = "default";
448 pinctrl-0 = <&cp1_spi1_pins>;
452 compatible = "st,w25q32";
453 spi-max-frequency = <50000000>;
459 usb-phy = <&usb3h0_phy>;