arch/arm64/boot/dts/marvell/armada-7040-db.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (C) 2016 Marvell Technology Group Ltd.
   4  *
   5  * Device Tree file for Marvell Armada 7040 Development board platform
   6  */
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include "armada-7040.dtsi"
  10
  11 / {
  12         model = "Marvell Armada 7040 DB board";
  13         compatible = "marvell,armada7040-db", "marvell,armada7040",
  14                      "marvell,armada-ap806-quad", "marvell,armada-ap806";
  15
  16         chosen {
  17                 stdout-path = "serial0:115200n8";
  18         };
  19
  20         memory@0 {
  21                 device_type = "memory";
  22                 reg = <0x0 0x0 0x0 0x80000000>;
  23         };
  24
  25         aliases {
  26                 ethernet0 = &cp0_eth0;
  27                 ethernet1 = &cp0_eth1;
  28                 ethernet2 = &cp0_eth2;
  29         };
  30
  31         cp0_exp_usb3_0_current_regulator: gpio-regulator {
  32                 compatible = "regulator-gpio";
  33                 regulator-name = "cp0-usb3-0-current-regulator";
  34                 regulator-type = "current";
  35                 regulator-min-microamp = <500000>;
  36                 regulator-max-microamp = <900000>;
  37                 gpios = <&expander0 4 GPIO_ACTIVE_HIGH>;
  38                 states = <500000 0x0
  39                           900000 0x1>;
  40                 enable-active-high;
  41                 gpios-states = <0>;
  42         };
  43
  44         cp0_exp_usb3_1_current_regulator: gpio-regulator {
  45                 compatible = "regulator-gpio";
  46                 regulator-name = "cp0-usb3-1-current-regulator";
  47                 regulator-type = "current";
  48                 regulator-min-microamp = <500000>;
  49                 regulator-max-microamp = <900000>;
  50                 gpios = <&expander0 5 GPIO_ACTIVE_HIGH>;
  51                 states = <500000 0x0
  52                           900000 0x1>;
  53                 enable-active-high;
  54                 gpios-states = <0>;
  55         };
  56
  57         cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
  58                 compatible = "regulator-fixed";
  59                 regulator-name = "usb3h0-vbus";
  60                 regulator-min-microvolt = <5000000>;
  61                 regulator-max-microvolt = <5000000>;
  62                 enable-active-high;
  63                 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
  64                 vin-supply = <&cp0_exp_usb3_0_current_regulator>;
  65         };
  66
  67         cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
  68                 compatible = "regulator-fixed";
  69                 regulator-name = "usb3h1-vbus";
  70                 regulator-min-microvolt = <5000000>;
  71                 regulator-max-microvolt = <5000000>;
  72                 enable-active-high;
  73                 gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
  74                 vin-supply = <&cp0_exp_usb3_1_current_regulator>;
  75         };
  76
  77         cp0_usb3_0_phy: cp0-usb3-0-phy {
  78                 compatible = "usb-nop-xceiv";
  79                 vcc-supply = <&cp0_reg_usb3_0_vbus>;
  80         };
  81
  82         cp0_usb3_1_phy: cp0-usb3-1-phy {
  83                 compatible = "usb-nop-xceiv";
  84                 vcc-supply = <&cp0_reg_usb3_1_vbus>;
  85         };
  86 };
  87
  88 &i2c0 {
  89         status = "okay";
  90         clock-frequency = <100000>;
  91 };
  92
  93 &spi0 {
  94         status = "okay";
  95
  96         spi-flash@0 {
  97                 compatible = "jedec,spi-nor";
  98                 reg = <0>;
  99                 spi-max-frequency = <10000000>;
 100
 101                 partitions {
 102                         compatible = "fixed-partitions";
 103                         #address-cells = <1>;
 104                         #size-cells = <1>;
 105
 106                         partition@0 {
 107                                 label = "U-Boot";
 108                                 reg = <0 0x200000>;
 109                         };
 110                         partition@400000 {
 111                                 label = "Filesystem";
 112                                 reg = <0x200000 0xce0000>;
 113                         };
 114                 };
 115         };
 116 };
 117
 118 &uart0 {
 119         status = "okay";
 120         pinctrl-0 = <&uart0_pins>;
 121         pinctrl-names = "default";
 122 };
 123
 124
 125 &cp0_pcie2 {
 126         status = "okay";
 127 };
 128
 129 &cp0_i2c0 {
 130         status = "okay";
 131         clock-frequency = <100000>;
 132
 133         expander0: pca9555@21 {
 134                 compatible = "nxp,pca9555";
 135                 pinctrl-names = "default";
 136                 gpio-controller;
 137                 #gpio-cells = <2>;
 138                 reg = <0x21>;
 139                 /*
 140                  * IO0_0: USB3_PWR_EN0  IO1_0: USB_3_1_Dev_Detect
 141                  * IO0_1: USB3_PWR_EN1  IO1_1: USB2_1_current_limit
 142                  * IO0_2: DDR3_4_Detect IO1_2: Hcon_IO_RstN
 143                  * IO0_3: USB2_DEVICE_DETECT
 144                  * IO0_4: GPIO_0        IO1_4: SD_Status
 145                  * IO0_5: GPIO_1        IO1_5: LDO_5V_Enable
 146                  * IO0_6: IHB_5V_Enable IO1_6: PWR_EN_eMMC
 147                  * IO0_7:               IO1_7: SDIO_Vcntrl
 148                  */
 149         };
 150 };
 151
 152 &cp0_nand_controller {
 153         /*
 154          * SPI on CPM and NAND have common pins on this board. We can
 155          * use only one at a time. To enable the NAND (which will
 156          * disable the SPI), the "status = "okay";" line have to be
 157          * added here.
 158          */
 159         pinctrl-0 = <&nand_pins>, <&nand_rb>;
 160         pinctrl-names = "default";
 161
 162         nand@0 {
 163                 reg = <0>;
 164                 label = "pxa3xx_nand-0";
 165                 nand-rb = <0>;
 166                 nand-on-flash-bbt;
 167                 nand-ecc-strength = <4>;
 168                 nand-ecc-step-size = <512>;
 169
 170                 partitions {
 171                         compatible = "fixed-partitions";
 172                         #address-cells = <1>;
 173                         #size-cells = <1>;
 174
 175                         partition@0 {
 176                                 label = "U-Boot";
 177                                 reg = <0 0x200000>;
 178                         };
 179
 180                         partition@200000 {
 181                                 label = "Linux";
 182                                 reg = <0x200000 0xe00000>;
 183                         };
 184
 185                         partition@1000000 {
 186                                 label = "Filesystem";
 187                                 reg = <0x1000000 0x3f000000>;
 188                         };
 189
 190                 };
 191         };
 192 };
 193
 194 &cp0_spi1 {
 195         status = "okay";
 196
 197         spi-flash@0 {
 198                 compatible = "jedec,spi-nor";
 199                 reg = <0x0>;
 200                 spi-max-frequency = <20000000>;
 201
 202                 partitions {
 203                         compatible = "fixed-partitions";
 204                         #address-cells = <1>;
 205                         #size-cells = <1>;
 206
 207                         partition@0 {
 208                                 label = "U-Boot";
 209                                 reg = <0x0 0x200000>;
 210                         };
 211
 212                         partition@400000 {
 213                                 label = "Filesystem";
 214                                 reg = <0x200000 0xe00000>;
 215                         };
 216                 };
 217         };
 218 };
 219
 220 &cp0_sata0 {
 221         status = "okay";
 222 };
 223
 224 &cp0_usb3_0 {
 225         usb-phy = <&cp0_usb3_0_phy>;
 226         status = "okay";
 227 };
 228
 229 &cp0_usb3_1 {
 230         usb-phy = <&cp0_usb3_1_phy>;
 231         status = "okay";
 232 };
 233
 234 &ap_sdhci0 {
 235         status = "okay";
 236         bus-width = <4>;
 237         no-1-8-v;
 238         non-removable;
 239 };
 240
 241 &cp0_sdhci0 {
 242         status = "okay";
 243         bus-width = <4>;
 244         no-1-8-v;
 245         cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>;
 246 };
 247
 248 &cp0_mdio {
 249         status = "okay";
 250
 251         phy0: ethernet-phy@0 {
 252                 reg = <0>;
 253         };
 254         phy1: ethernet-phy@1 {
 255                 reg = <1>;
 256         };
 257 };
 258
 259 &cp0_ethernet {
 260         status = "okay";
 261 };
 262
 263 &cp0_eth0 {
 264         status = "okay";
 265         /* Network PHY */
 266         phy-mode = "10gbase-kr";
 267         /* Generic PHY, providing serdes lanes */
 268         phys = <&cp0_comphy2 0>;
 269
 270         fixed-link {
 271                 speed = <10000>;
 272                 full-duplex;
 273         };
 274 };
 275
 276 &cp0_eth1 {
 277         status = "okay";
 278         /* Network PHY */
 279         phy = <&phy0>;
 280         phy-mode = "sgmii";
 281         /* Generic PHY, providing serdes lanes */
 282         phys = <&cp0_comphy0 1>;
 283 };
 284
 285 &cp0_eth2 {
 286         status = "okay";
 287         phy = <&phy1>;
 288         phy-mode = "rgmii-id";
 289 };