1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for CZ.NIC Turris Mox Board
4 * 2019 by Marek Behun <marek.behun@nic.cz>
9 #include <dt-bindings/bus/moxtet.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include "armada-372x.dtsi"
15 model = "CZ.NIC Turris Mox Board";
16 compatible = "cznic,turris-mox", "marvell,armada3720",
25 stdout-path = "serial0:115200n8";
29 device_type = "memory";
30 reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
34 compatible = "gpio-leds";
36 label = "mox:red:activity";
37 gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
38 linux,default-trigger = "default-on";
43 compatible = "gpio-keys";
47 linux,code = <KEY_RESTART>;
48 gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
49 debounce-interval = <60>;
53 exp_usb3_vbus: usb3-vbus {
54 compatible = "regulator-fixed";
55 regulator-name = "usb3-vbus";
56 regulator-min-microvolt = <5000000>;
57 regulator-max-microvolt = <5000000>;
60 gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
64 compatible = "regulator-gpio";
65 regulator-name = "vsdc";
66 regulator-min-microvolt = <1800000>;
67 regulator-max-microvolt = <3300000>;
70 gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
77 vsdio_reg: vsdio-reg {
78 compatible = "regulator-gpio";
79 regulator-name = "vsdio";
80 regulator-min-microvolt = <1800000>;
81 regulator-max-microvolt = <3300000>;
84 gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>;
91 sdhci1_pwrseq: sdhci1-pwrseq {
92 compatible = "mmc-pwrseq-simple";
93 reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>;
98 compatible = "sff,sfp+";
100 los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
101 tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
102 mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
103 tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
104 rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
106 /* enabled by U-Boot if SFP module is present */
112 pinctrl-names = "default";
113 pinctrl-0 = <&i2c1_pins>;
114 clock-frequency = <100000>;
118 compatible = "microchip,mcp7940x";
128 pinctrl-names = "default";
129 pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
131 max-link-speed = <2>;
132 reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
135 /* enabled by U-Boot if PCIe module is present */
144 pinctrl-names = "default";
145 pinctrl-0 = <&rgmii_pins>;
146 phy-mode = "rgmii-id";
152 phy-mode = "2500base-x";
153 managed = "in-band-status";
160 cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>;
161 vqmmc-supply = <&vsdc_reg>;
162 marvell,pad-type = "sd";
167 pinctrl-names = "default";
168 pinctrl-0 = <&sdio_pins>;
171 marvell,pad-type = "sd";
172 vqmmc-supply = <&vsdio_reg>;
173 mmc-pwrseq = <&sdhci1_pwrseq>;
179 pinctrl-names = "default";
180 pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
181 assigned-clocks = <&nb_periph_clk 7>;
182 assigned-clock-parents = <&tbg 1>;
183 assigned-clock-rates = <20000000>;
186 #address-cells = <1>;
188 compatible = "jedec,spi-nor";
190 spi-max-frequency = <20000000>;
193 compatible = "fixed-partitions";
194 #address-cells = <1>;
198 label = "secure-firmware";
204 reg = <0x20000 0x160000>;
208 label = "u-boot-env";
209 reg = <0x180000 0x10000>;
213 label = "Rescue system";
214 reg = <0x190000 0x660000>;
219 reg = <0x7f0000 0x10000>;
225 #address-cells = <1>;
227 compatible = "cznic,moxtet";
229 reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
230 spi-max-frequency = <10000000>;
233 interrupt-controller;
234 #interrupt-cells = <1>;
235 interrupt-parent = <&gpiosb>;
236 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
240 compatible = "cznic,moxtet-gpio";
255 compatible = "usb-a-connector";
256 phy-supply = <&exp_usb3_vbus>;
266 pinctrl-names = "default";
267 pinctrl-0 = <&smi_pins>;
270 phy1: ethernet-phy@1 {
274 /* switch nodes are enabled by U-Boot if modules are present */
276 compatible = "marvell,mv88e6190";
279 interrupt-parent = <&moxtet>;
280 interrupts = <MOXTET_IRQ_PERIDOT(0)>;
284 #address-cells = <1>;
287 switch0phy1: switch0phy1@1 {
291 switch0phy2: switch0phy2@2 {
295 switch0phy3: switch0phy3@3 {
299 switch0phy4: switch0phy4@4 {
303 switch0phy5: switch0phy5@5 {
307 switch0phy6: switch0phy6@6 {
311 switch0phy7: switch0phy7@7 {
315 switch0phy8: switch0phy8@8 {
321 #address-cells = <1>;
327 phy-handle = <&switch0phy1>;
333 phy-handle = <&switch0phy2>;
339 phy-handle = <&switch0phy3>;
345 phy-handle = <&switch0phy4>;
351 phy-handle = <&switch0phy5>;
357 phy-handle = <&switch0phy6>;
363 phy-handle = <&switch0phy7>;
369 phy-handle = <&switch0phy8>;
376 phy-mode = "2500base-x";
377 managed = "in-band-status";
380 switch0port10: port@a {
383 phy-mode = "2500base-x";
384 managed = "in-band-status";
385 link = <&switch1port9 &switch2port9>;
394 managed = "in-band-status";
401 compatible = "marvell,mv88e6085";
404 interrupt-parent = <&moxtet>;
405 interrupts = <MOXTET_IRQ_TOPAZ>;
409 #address-cells = <1>;
412 switch0phy1_topaz: switch0phy1@11 {
416 switch0phy2_topaz: switch0phy2@12 {
420 switch0phy3_topaz: switch0phy3@13 {
424 switch0phy4_topaz: switch0phy4@14 {
430 #address-cells = <1>;
436 phy-handle = <&switch0phy1_topaz>;
442 phy-handle = <&switch0phy2_topaz>;
448 phy-handle = <&switch0phy3_topaz>;
454 phy-handle = <&switch0phy4_topaz>;
460 phy-mode = "2500base-x";
461 managed = "in-band-status";
468 compatible = "marvell,mv88e6190";
471 interrupt-parent = <&moxtet>;
472 interrupts = <MOXTET_IRQ_PERIDOT(1)>;
476 #address-cells = <1>;
479 switch1phy1: switch1phy1@1 {
483 switch1phy2: switch1phy2@2 {
487 switch1phy3: switch1phy3@3 {
491 switch1phy4: switch1phy4@4 {
495 switch1phy5: switch1phy5@5 {
499 switch1phy6: switch1phy6@6 {
503 switch1phy7: switch1phy7@7 {
507 switch1phy8: switch1phy8@8 {
513 #address-cells = <1>;
519 phy-handle = <&switch1phy1>;
525 phy-handle = <&switch1phy2>;
531 phy-handle = <&switch1phy3>;
537 phy-handle = <&switch1phy4>;
543 phy-handle = <&switch1phy5>;
549 phy-handle = <&switch1phy6>;
555 phy-handle = <&switch1phy7>;
561 phy-handle = <&switch1phy8>;
564 switch1port9: port@9 {
567 phy-mode = "2500base-x";
568 managed = "in-band-status";
569 link = <&switch0port10>;
572 switch1port10: port@a {
575 phy-mode = "2500base-x";
576 managed = "in-band-status";
577 link = <&switch2port9>;
586 managed = "in-band-status";
593 compatible = "marvell,mv88e6085";
596 interrupt-parent = <&moxtet>;
597 interrupts = <MOXTET_IRQ_TOPAZ>;
601 #address-cells = <1>;
604 switch1phy1_topaz: switch1phy1@11 {
608 switch1phy2_topaz: switch1phy2@12 {
612 switch1phy3_topaz: switch1phy3@13 {
616 switch1phy4_topaz: switch1phy4@14 {
622 #address-cells = <1>;
628 phy-handle = <&switch1phy1_topaz>;
634 phy-handle = <&switch1phy2_topaz>;
640 phy-handle = <&switch1phy3_topaz>;
646 phy-handle = <&switch1phy4_topaz>;
652 phy-mode = "2500base-x";
653 managed = "in-band-status";
654 link = <&switch0port10>;
660 compatible = "marvell,mv88e6190";
663 interrupt-parent = <&moxtet>;
664 interrupts = <MOXTET_IRQ_PERIDOT(2)>;
668 #address-cells = <1>;
671 switch2phy1: switch2phy1@1 {
675 switch2phy2: switch2phy2@2 {
679 switch2phy3: switch2phy3@3 {
683 switch2phy4: switch2phy4@4 {
687 switch2phy5: switch2phy5@5 {
691 switch2phy6: switch2phy6@6 {
695 switch2phy7: switch2phy7@7 {
699 switch2phy8: switch2phy8@8 {
705 #address-cells = <1>;
711 phy-handle = <&switch2phy1>;
717 phy-handle = <&switch2phy2>;
723 phy-handle = <&switch2phy3>;
729 phy-handle = <&switch2phy4>;
735 phy-handle = <&switch2phy5>;
741 phy-handle = <&switch2phy6>;
747 phy-handle = <&switch2phy7>;
753 phy-handle = <&switch2phy8>;
756 switch2port9: port@9 {
759 phy-mode = "2500base-x";
760 managed = "in-band-status";
761 link = <&switch1port10 &switch0port10>;
769 managed = "in-band-status";
776 compatible = "marvell,mv88e6085";
779 interrupt-parent = <&moxtet>;
780 interrupts = <MOXTET_IRQ_TOPAZ>;
784 #address-cells = <1>;
787 switch2phy1_topaz: switch2phy1@11 {
791 switch2phy2_topaz: switch2phy2@12 {
795 switch2phy3_topaz: switch2phy3@13 {
799 switch2phy4_topaz: switch2phy4@14 {
805 #address-cells = <1>;
811 phy-handle = <&switch2phy1_topaz>;
817 phy-handle = <&switch2phy2_topaz>;
823 phy-handle = <&switch2phy3_topaz>;
829 phy-handle = <&switch2phy4_topaz>;
835 phy-mode = "2500base-x";
836 managed = "in-band-status";
837 link = <&switch1port10 &switch0port10>;