1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for CZ.NIC Turris Mox Board
4 * 2019 by Marek Behun <marek.behun@nic.cz>
9 #include <dt-bindings/bus/moxtet.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include "armada-372x.dtsi"
15 model = "CZ.NIC Turris Mox Board";
16 compatible = "cznic,turris-mox", "marvell,armada3720",
25 stdout-path = "serial0:115200n8";
29 device_type = "memory";
30 reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
34 compatible = "gpio-leds";
36 label = "mox:red:activity";
37 gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
38 linux,default-trigger = "default-on";
43 compatible = "gpio-keys";
47 linux,code = <KEY_RESTART>;
48 gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
49 debounce-interval = <60>;
53 exp_usb3_vbus: usb3-vbus {
54 compatible = "regulator-fixed";
55 regulator-name = "usb3-vbus";
56 regulator-min-microvolt = <5000000>;
57 regulator-max-microvolt = <5000000>;
60 gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
64 compatible = "regulator-gpio";
65 regulator-name = "vsdc";
66 regulator-min-microvolt = <1800000>;
67 regulator-max-microvolt = <3300000>;
70 gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
77 vsdio_reg: vsdio-reg {
78 compatible = "regulator-gpio";
79 regulator-name = "vsdio";
80 regulator-min-microvolt = <1800000>;
81 regulator-max-microvolt = <3300000>;
84 gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>;
91 sdhci1_pwrseq: sdhci1-pwrseq {
92 compatible = "mmc-pwrseq-simple";
93 reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>;
98 compatible = "sff,sfp+";
100 los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
101 tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
102 mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
103 tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
104 rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
106 /* enabled by U-Boot if SFP module is present */
112 compatible = "cznic,turris-mox-rwtm";
120 pinctrl-names = "default";
121 pinctrl-0 = <&i2c1_pins>;
122 clock-frequency = <100000>;
126 compatible = "microchip,mcp7940x";
132 pinctrl-names = "default";
133 pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
135 reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
137 /* enabled by U-Boot if PCIe module is present */
146 pinctrl-names = "default";
147 pinctrl-0 = <&rgmii_pins>;
148 phy-mode = "rgmii-id";
154 phy-mode = "2500base-x";
155 managed = "in-band-status";
162 cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>;
163 vqmmc-supply = <&vsdc_reg>;
164 marvell,pad-type = "sd";
169 pinctrl-names = "default";
170 pinctrl-0 = <&sdio_pins>;
173 marvell,pad-type = "sd";
174 vqmmc-supply = <&vsdio_reg>;
175 mmc-pwrseq = <&sdhci1_pwrseq>;
176 /* forbid SDR104 for FCC purposes */
177 sdhci-caps-mask = <0x2 0x0>;
183 pinctrl-names = "default";
184 pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
185 assigned-clocks = <&nb_periph_clk 7>;
186 assigned-clock-parents = <&tbg 1>;
187 assigned-clock-rates = <20000000>;
190 #address-cells = <1>;
192 compatible = "jedec,spi-nor";
194 spi-max-frequency = <20000000>;
197 compatible = "fixed-partitions";
198 #address-cells = <1>;
202 label = "secure-firmware";
208 reg = <0x20000 0x160000>;
212 label = "u-boot-env";
213 reg = <0x180000 0x10000>;
217 label = "Rescue system";
218 reg = <0x190000 0x660000>;
223 reg = <0x7f0000 0x10000>;
229 #address-cells = <1>;
231 compatible = "cznic,moxtet";
233 reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
234 spi-max-frequency = <10000000>;
237 interrupt-controller;
238 #interrupt-cells = <1>;
239 interrupt-parent = <&gpiosb>;
240 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
244 compatible = "cznic,moxtet-gpio";
259 compatible = "usb-a-connector";
260 phy-supply = <&exp_usb3_vbus>;
270 pinctrl-names = "default";
271 pinctrl-0 = <&smi_pins>;
274 phy1: ethernet-phy@1 {
278 /* switch nodes are enabled by U-Boot if modules are present */
280 compatible = "marvell,mv88e6190";
283 interrupt-parent = <&moxtet>;
284 interrupts = <MOXTET_IRQ_PERIDOT(0)>;
288 #address-cells = <1>;
291 switch0phy1: switch0phy1@1 {
295 switch0phy2: switch0phy2@2 {
299 switch0phy3: switch0phy3@3 {
303 switch0phy4: switch0phy4@4 {
307 switch0phy5: switch0phy5@5 {
311 switch0phy6: switch0phy6@6 {
315 switch0phy7: switch0phy7@7 {
319 switch0phy8: switch0phy8@8 {
325 #address-cells = <1>;
331 phy-handle = <&switch0phy1>;
337 phy-handle = <&switch0phy2>;
343 phy-handle = <&switch0phy3>;
349 phy-handle = <&switch0phy4>;
355 phy-handle = <&switch0phy5>;
361 phy-handle = <&switch0phy6>;
367 phy-handle = <&switch0phy7>;
373 phy-handle = <&switch0phy8>;
380 phy-mode = "2500base-x";
381 managed = "in-band-status";
384 switch0port10: port@a {
387 phy-mode = "2500base-x";
388 managed = "in-band-status";
389 link = <&switch1port9 &switch2port9>;
398 managed = "in-band-status";
405 compatible = "marvell,mv88e6085";
408 interrupt-parent = <&moxtet>;
409 interrupts = <MOXTET_IRQ_TOPAZ>;
413 #address-cells = <1>;
416 switch0phy1_topaz: switch0phy1@11 {
420 switch0phy2_topaz: switch0phy2@12 {
424 switch0phy3_topaz: switch0phy3@13 {
428 switch0phy4_topaz: switch0phy4@14 {
434 #address-cells = <1>;
440 phy-handle = <&switch0phy1_topaz>;
446 phy-handle = <&switch0phy2_topaz>;
452 phy-handle = <&switch0phy3_topaz>;
458 phy-handle = <&switch0phy4_topaz>;
464 phy-mode = "2500base-x";
465 managed = "in-band-status";
472 compatible = "marvell,mv88e6190";
475 interrupt-parent = <&moxtet>;
476 interrupts = <MOXTET_IRQ_PERIDOT(1)>;
480 #address-cells = <1>;
483 switch1phy1: switch1phy1@1 {
487 switch1phy2: switch1phy2@2 {
491 switch1phy3: switch1phy3@3 {
495 switch1phy4: switch1phy4@4 {
499 switch1phy5: switch1phy5@5 {
503 switch1phy6: switch1phy6@6 {
507 switch1phy7: switch1phy7@7 {
511 switch1phy8: switch1phy8@8 {
517 #address-cells = <1>;
523 phy-handle = <&switch1phy1>;
529 phy-handle = <&switch1phy2>;
535 phy-handle = <&switch1phy3>;
541 phy-handle = <&switch1phy4>;
547 phy-handle = <&switch1phy5>;
553 phy-handle = <&switch1phy6>;
559 phy-handle = <&switch1phy7>;
565 phy-handle = <&switch1phy8>;
568 switch1port9: port@9 {
571 phy-mode = "2500base-x";
572 managed = "in-band-status";
573 link = <&switch0port10>;
576 switch1port10: port@a {
579 phy-mode = "2500base-x";
580 managed = "in-band-status";
581 link = <&switch2port9>;
590 managed = "in-band-status";
597 compatible = "marvell,mv88e6085";
600 interrupt-parent = <&moxtet>;
601 interrupts = <MOXTET_IRQ_TOPAZ>;
605 #address-cells = <1>;
608 switch1phy1_topaz: switch1phy1@11 {
612 switch1phy2_topaz: switch1phy2@12 {
616 switch1phy3_topaz: switch1phy3@13 {
620 switch1phy4_topaz: switch1phy4@14 {
626 #address-cells = <1>;
632 phy-handle = <&switch1phy1_topaz>;
638 phy-handle = <&switch1phy2_topaz>;
644 phy-handle = <&switch1phy3_topaz>;
650 phy-handle = <&switch1phy4_topaz>;
656 phy-mode = "2500base-x";
657 managed = "in-band-status";
658 link = <&switch0port10>;
664 compatible = "marvell,mv88e6190";
667 interrupt-parent = <&moxtet>;
668 interrupts = <MOXTET_IRQ_PERIDOT(2)>;
672 #address-cells = <1>;
675 switch2phy1: switch2phy1@1 {
679 switch2phy2: switch2phy2@2 {
683 switch2phy3: switch2phy3@3 {
687 switch2phy4: switch2phy4@4 {
691 switch2phy5: switch2phy5@5 {
695 switch2phy6: switch2phy6@6 {
699 switch2phy7: switch2phy7@7 {
703 switch2phy8: switch2phy8@8 {
709 #address-cells = <1>;
715 phy-handle = <&switch2phy1>;
721 phy-handle = <&switch2phy2>;
727 phy-handle = <&switch2phy3>;
733 phy-handle = <&switch2phy4>;
739 phy-handle = <&switch2phy5>;
745 phy-handle = <&switch2phy6>;
751 phy-handle = <&switch2phy7>;
757 phy-handle = <&switch2phy8>;
760 switch2port9: port@9 {
763 phy-mode = "2500base-x";
764 managed = "in-band-status";
765 link = <&switch1port10 &switch0port10>;
773 managed = "in-band-status";
780 compatible = "marvell,mv88e6085";
783 interrupt-parent = <&moxtet>;
784 interrupts = <MOXTET_IRQ_TOPAZ>;
788 #address-cells = <1>;
791 switch2phy1_topaz: switch2phy1@11 {
795 switch2phy2_topaz: switch2phy2@12 {
799 switch2phy3_topaz: switch2phy3@13 {
803 switch2phy4_topaz: switch2phy4@14 {
809 #address-cells = <1>;
815 phy-handle = <&switch2phy1_topaz>;
821 phy-handle = <&switch2phy2_topaz>;
827 phy-handle = <&switch2phy3_topaz>;
833 phy-handle = <&switch2phy4_topaz>;
839 phy-mode = "2500base-x";
840 managed = "in-band-status";
841 link = <&switch1port10 &switch0port10>;