1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for CZ.NIC Turris Mox Board
4 * 2019 by Marek BehĂșn <kabel@kernel.org>
9 #include <dt-bindings/bus/moxtet.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include "armada-372x.dtsi"
15 model = "CZ.NIC Turris Mox Board";
16 compatible = "cznic,turris-mox", "marvell,armada3720",
27 stdout-path = "serial0:115200n8";
31 device_type = "memory";
32 reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
36 compatible = "gpio-leds";
38 label = "mox:red:activity";
39 gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
40 linux,default-trigger = "default-on";
45 compatible = "gpio-keys";
49 linux,code = <KEY_RESTART>;
50 gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
51 debounce-interval = <60>;
55 exp_usb3_vbus: usb3-vbus {
56 compatible = "regulator-fixed";
57 regulator-name = "usb3-vbus";
58 regulator-min-microvolt = <5000000>;
59 regulator-max-microvolt = <5000000>;
62 gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
66 compatible = "regulator-gpio";
67 regulator-name = "vsdc";
68 regulator-min-microvolt = <1800000>;
69 regulator-max-microvolt = <3300000>;
72 gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
79 vsdio_reg: vsdio-reg {
80 compatible = "regulator-gpio";
81 regulator-name = "vsdio";
82 regulator-min-microvolt = <1800000>;
83 regulator-max-microvolt = <3300000>;
86 gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>;
93 sdhci1_pwrseq: sdhci1-pwrseq {
94 compatible = "mmc-pwrseq-simple";
95 reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>;
100 compatible = "sff,sfp";
102 los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
103 tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
104 mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
105 tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
106 rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
107 maximum-power-milliwatt = <3000>;
109 /* enabled by U-Boot if SFP module is present */
115 compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm";
121 pinctrl-names = "default";
122 pinctrl-0 = <&i2c1_pins>;
123 clock-frequency = <100000>;
124 /delete-property/ mrvl,i2c-fast-mode;
128 compatible = "microchip,mcp7940x";
134 pinctrl-names = "default";
135 pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
137 reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
139 * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property
140 * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and
141 * 2 size cells and also expects that the second range starts at 16 MB offset. If these
142 * conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address
143 * space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window
144 * for IO and the rest 112 MB (64+32+16) for MEM, despite that maximal IO size is just 64 kB.
145 * This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in
146 * U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix):
147 * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7
148 * https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf
149 * https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33
151 #address-cells = <3>;
153 ranges = <0x81000000 0 0xe8000000 0 0xe8000000 0 0x01000000 /* Port 0 IO */
154 0x82000000 0 0xe9000000 0 0xe9000000 0 0x07000000>; /* Port 0 MEM */
156 /* enabled by U-Boot if PCIe module is present */
165 pinctrl-names = "default";
166 pinctrl-0 = <&rgmii_pins>;
167 phy-mode = "rgmii-id";
168 phy-handle = <&phy1>;
173 phy-mode = "2500base-x";
174 managed = "in-band-status";
181 cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>;
182 vqmmc-supply = <&vsdc_reg>;
183 marvell,pad-type = "sd";
188 pinctrl-names = "default";
189 pinctrl-0 = <&sdio_pins>;
192 marvell,pad-type = "sd";
193 vqmmc-supply = <&vsdio_reg>;
194 mmc-pwrseq = <&sdhci1_pwrseq>;
195 /* forbid SDR104 for FCC purposes */
196 sdhci-caps-mask = <0x2 0x0>;
202 pinctrl-names = "default";
203 pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
204 assigned-clocks = <&nb_periph_clk 7>;
205 assigned-clock-parents = <&tbg 1>;
206 assigned-clock-rates = <20000000>;
209 #address-cells = <1>;
211 compatible = "jedec,spi-nor";
213 spi-max-frequency = <20000000>;
216 compatible = "fixed-partitions";
217 #address-cells = <1>;
221 label = "secure-firmware";
226 label = "a53-firmware";
227 reg = <0x20000 0x160000>;
231 label = "u-boot-env";
232 reg = <0x180000 0x10000>;
236 label = "Rescue system";
237 reg = <0x190000 0x660000>;
242 reg = <0x7f0000 0x10000>;
248 #address-cells = <1>;
250 compatible = "cznic,moxtet";
252 reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
253 spi-max-frequency = <10000000>;
256 interrupt-controller;
257 #interrupt-cells = <1>;
258 interrupt-parent = <&gpiosb>;
259 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
263 compatible = "cznic,moxtet-gpio";
278 compatible = "usb-a-connector";
279 phy-supply = <&exp_usb3_vbus>;
289 pinctrl-names = "default";
290 pinctrl-0 = <&smi_pins>;
293 phy1: ethernet-phy@1 {
297 /* switch nodes are enabled by U-Boot if modules are present */
299 compatible = "marvell,mv88e6190";
302 interrupt-parent = <&moxtet>;
303 interrupts = <MOXTET_IRQ_PERIDOT(0)>;
307 #address-cells = <1>;
310 switch0phy1: switch0phy1@1 {
314 switch0phy2: switch0phy2@2 {
318 switch0phy3: switch0phy3@3 {
322 switch0phy4: switch0phy4@4 {
326 switch0phy5: switch0phy5@5 {
330 switch0phy6: switch0phy6@6 {
334 switch0phy7: switch0phy7@7 {
338 switch0phy8: switch0phy8@8 {
344 #address-cells = <1>;
350 phy-handle = <&switch0phy1>;
356 phy-handle = <&switch0phy2>;
362 phy-handle = <&switch0phy3>;
368 phy-handle = <&switch0phy4>;
374 phy-handle = <&switch0phy5>;
380 phy-handle = <&switch0phy6>;
386 phy-handle = <&switch0phy7>;
392 phy-handle = <&switch0phy8>;
399 phy-mode = "2500base-x";
400 managed = "in-band-status";
403 switch0port10: port@a {
406 phy-mode = "2500base-x";
407 managed = "in-band-status";
408 link = <&switch1port9 &switch2port9>;
417 managed = "in-band-status";
424 compatible = "marvell,mv88e6085";
427 interrupt-parent = <&moxtet>;
428 interrupts = <MOXTET_IRQ_TOPAZ>;
432 #address-cells = <1>;
435 switch0phy1_topaz: switch0phy1@11 {
439 switch0phy2_topaz: switch0phy2@12 {
443 switch0phy3_topaz: switch0phy3@13 {
447 switch0phy4_topaz: switch0phy4@14 {
453 #address-cells = <1>;
459 phy-handle = <&switch0phy1_topaz>;
465 phy-handle = <&switch0phy2_topaz>;
471 phy-handle = <&switch0phy3_topaz>;
477 phy-handle = <&switch0phy4_topaz>;
483 phy-mode = "2500base-x";
484 managed = "in-band-status";
491 compatible = "marvell,mv88e6190";
494 interrupt-parent = <&moxtet>;
495 interrupts = <MOXTET_IRQ_PERIDOT(1)>;
499 #address-cells = <1>;
502 switch1phy1: switch1phy1@1 {
506 switch1phy2: switch1phy2@2 {
510 switch1phy3: switch1phy3@3 {
514 switch1phy4: switch1phy4@4 {
518 switch1phy5: switch1phy5@5 {
522 switch1phy6: switch1phy6@6 {
526 switch1phy7: switch1phy7@7 {
530 switch1phy8: switch1phy8@8 {
536 #address-cells = <1>;
542 phy-handle = <&switch1phy1>;
548 phy-handle = <&switch1phy2>;
554 phy-handle = <&switch1phy3>;
560 phy-handle = <&switch1phy4>;
566 phy-handle = <&switch1phy5>;
572 phy-handle = <&switch1phy6>;
578 phy-handle = <&switch1phy7>;
584 phy-handle = <&switch1phy8>;
587 switch1port9: port@9 {
590 phy-mode = "2500base-x";
591 managed = "in-band-status";
592 link = <&switch0port10>;
595 switch1port10: port@a {
598 phy-mode = "2500base-x";
599 managed = "in-band-status";
600 link = <&switch2port9>;
609 managed = "in-band-status";
616 compatible = "marvell,mv88e6085";
619 interrupt-parent = <&moxtet>;
620 interrupts = <MOXTET_IRQ_TOPAZ>;
624 #address-cells = <1>;
627 switch1phy1_topaz: switch1phy1@11 {
631 switch1phy2_topaz: switch1phy2@12 {
635 switch1phy3_topaz: switch1phy3@13 {
639 switch1phy4_topaz: switch1phy4@14 {
645 #address-cells = <1>;
651 phy-handle = <&switch1phy1_topaz>;
657 phy-handle = <&switch1phy2_topaz>;
663 phy-handle = <&switch1phy3_topaz>;
669 phy-handle = <&switch1phy4_topaz>;
675 phy-mode = "2500base-x";
676 managed = "in-band-status";
677 link = <&switch0port10>;
683 compatible = "marvell,mv88e6190";
686 interrupt-parent = <&moxtet>;
687 interrupts = <MOXTET_IRQ_PERIDOT(2)>;
691 #address-cells = <1>;
694 switch2phy1: switch2phy1@1 {
698 switch2phy2: switch2phy2@2 {
702 switch2phy3: switch2phy3@3 {
706 switch2phy4: switch2phy4@4 {
710 switch2phy5: switch2phy5@5 {
714 switch2phy6: switch2phy6@6 {
718 switch2phy7: switch2phy7@7 {
722 switch2phy8: switch2phy8@8 {
728 #address-cells = <1>;
734 phy-handle = <&switch2phy1>;
740 phy-handle = <&switch2phy2>;
746 phy-handle = <&switch2phy3>;
752 phy-handle = <&switch2phy4>;
758 phy-handle = <&switch2phy5>;
764 phy-handle = <&switch2phy6>;
770 phy-handle = <&switch2phy7>;
776 phy-handle = <&switch2phy8>;
779 switch2port9: port@9 {
782 phy-mode = "2500base-x";
783 managed = "in-band-status";
784 link = <&switch1port10 &switch0port10>;
792 managed = "in-band-status";
799 compatible = "marvell,mv88e6085";
802 interrupt-parent = <&moxtet>;
803 interrupts = <MOXTET_IRQ_TOPAZ>;
807 #address-cells = <1>;
810 switch2phy1_topaz: switch2phy1@11 {
814 switch2phy2_topaz: switch2phy2@12 {
818 switch2phy3_topaz: switch2phy3@13 {
822 switch2phy4_topaz: switch2phy4@14 {
828 #address-cells = <1>;
834 phy-handle = <&switch2phy1_topaz>;
840 phy-handle = <&switch2phy2_topaz>;
846 phy-handle = <&switch2phy3_topaz>;
852 phy-handle = <&switch2phy4_topaz>;
858 phy-mode = "2500base-x";
859 managed = "in-band-status";
860 link = <&switch1port10 &switch0port10>;