arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree For AC5.
   4  *
   5  * Copyright (C) 2021 Marvell
   6  * Copyright (C) 2022 Allied Telesis Labs
   7  */
   8
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11
  12 / {
  13         model = "Marvell AC5 SoC";
  14         compatible = "marvell,ac5";
  15         interrupt-parent = <&gic>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         cpus {
  20                 #address-cells = <2>;
  21                 #size-cells = <0>;
  22
  23                 cpu-map {
  24                         cluster0 {
  25                                 core0 {
  26                                         cpu = <&cpu0>;
  27                                 };
  28                                 core1 {
  29                                         cpu = <&cpu1>;
  30                                 };
  31                         };
  32                 };
  33
  34                 cpu0: cpu@0 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a55";
  37                         reg = <0x0 0x0>;
  38                         enable-method = "psci";
  39                         next-level-cache = <&l2>;
  40                 };
  41
  42                 cpu1: cpu@1 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a55";
  45                         reg = <0x0 0x100>;
  46                         enable-method = "psci";
  47                         next-level-cache = <&l2>;
  48                 };
  49
  50                 l2: l2-cache {
  51                         compatible = "cache";
  52                         cache-level = <2>;
  53                 };
  54         };
  55
  56         psci {
  57                 compatible = "arm,psci-0.2";
  58                 method = "smc";
  59         };
  60
  61         timer {
  62                 compatible = "arm,armv8-timer";
  63                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>,
  64                              <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>,
  65                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>,
  66                              <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
  67         };
  68
  69         pmu {
  70                 compatible = "arm,armv8-pmuv3";
  71                 interrupts = <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
  72         };
  73
  74         soc {
  75                 compatible = "simple-bus";
  76                 #address-cells = <2>;
  77                 #size-cells = <2>;
  78                 ranges;
  79                 dma-ranges;
  80
  81                 internal-regs@7f000000 {
  82                         #address-cells = <1>;
  83                         #size-cells = <1>;
  84                         compatible = "simple-bus";
  85                         /* 16M internal register @ 0x7f00_0000 */
  86                         ranges = <0x0 0x0 0x7f000000 0x1000000>;
  87                         dma-coherent;
  88
  89                         uart0: serial@12000 {
  90                                 compatible = "snps,dw-apb-uart";
  91                                 reg = <0x12000 0x100>;
  92                                 reg-shift = <2>;
  93                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
  94                                 reg-io-width = <1>;
  95                                 clocks = <&cnm_clock>;
  96                                 status = "okay";
  97                         };
  98
  99                         uart1: serial@12100 {
 100                                 compatible = "snps,dw-apb-uart";
 101                                 reg = <0x12100 0x100>;
 102                                 reg-shift = <2>;
 103                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 104                                 reg-io-width = <1>;
 105                                 clocks = <&cnm_clock>;
 106                                 status = "disabled";
 107                         };
 108
 109                         uart2: serial@12200 {
 110                                 compatible = "snps,dw-apb-uart";
 111                                 reg = <0x12200 0x100>;
 112                                 reg-shift = <2>;
 113                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 114                                 reg-io-width = <1>;
 115                                 clocks = <&cnm_clock>;
 116                                 status = "disabled";
 117                         };
 118
 119                         uart3: serial@12300 {
 120                                 compatible = "snps,dw-apb-uart";
 121                                 reg = <0x12300 0x100>;
 122                                 reg-shift = <2>;
 123                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 124                                 reg-io-width = <1>;
 125                                 clocks = <&cnm_clock>;
 126                                 status = "disabled";
 127                         };
 128
 129                         mdio: mdio@22004 {
 130                                 #address-cells = <1>;
 131                                 #size-cells = <0>;
 132                                 compatible = "marvell,orion-mdio";
 133                                 reg = <0x22004 0x4>;
 134                                 clocks = <&cnm_clock>;
 135                         };
 136
 137                         i2c0: i2c@11000{
 138                                 compatible = "marvell,mv78230-i2c";
 139                                 reg = <0x11000 0x20>;
 140                                 #address-cells = <1>;
 141                                 #size-cells = <0>;
 142
 143                                 clocks = <&cnm_clock>;
 144                                 clock-names = "core";
 145                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 146                                 clock-frequency=<100000>;
 147
 148                                 pinctrl-names = "default", "gpio";
 149                                 pinctrl-0 = <&i2c0_pins>;
 150                                 pinctrl-1 = <&i2c0_gpio>;
 151                                 scl-gpios = <&gpio0 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 152                                 sda-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 153                                 status = "disabled";
 154                         };
 155
 156                         i2c1: i2c@11100{
 157                                 compatible = "marvell,mv78230-i2c";
 158                                 reg = <0x11100 0x20>;
 159                                 #address-cells = <1>;
 160                                 #size-cells = <0>;
 161
 162                                 clocks = <&cnm_clock>;
 163                                 clock-names = "core";
 164                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 165                                 clock-frequency=<100000>;
 166
 167                                 pinctrl-names = "default", "gpio";
 168                                 pinctrl-0 = <&i2c1_pins>;
 169                                 pinctrl-1 = <&i2c1_gpio>;
 170                                 scl-gpios = <&gpio0 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 171                                 sda-gpios = <&gpio0 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 172                                 status = "disabled";
 173                         };
 174
 175                         gpio0: gpio@18100 {
 176                                 compatible = "marvell,orion-gpio";
 177                                 reg = <0x18100 0x40>;
 178                                 ngpios = <32>;
 179                                 gpio-controller;
 180                                 #gpio-cells = <2>;
 181                                 gpio-ranges = <&pinctrl0 0 0 32>;
 182                                 marvell,pwm-offset = <0x1f0>;
 183                                 interrupt-controller;
 184                                 #interrupt-cells = <2>;
 185                                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
 186                                              <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 187                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
 188                                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 189                         };
 190
 191                         gpio1: gpio@18140 {
 192                                 reg = <0x18140 0x40>;
 193                                 compatible = "marvell,orion-gpio";
 194                                 ngpios = <14>;
 195                                 gpio-controller;
 196                                 #gpio-cells = <2>;
 197                                 gpio-ranges = <&pinctrl0 0 32 14>;
 198                                 marvell,pwm-offset = <0x1f0>;
 199                                 interrupt-controller;
 200                                 #interrupt-cells = <2>;
 201                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
 202                                              <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 203                         };
 204                 };
 205
 206                 /*
 207                  * Dedicated section for devices behind 32bit controllers so we
 208                  * can configure specific DMA mapping for them
 209                  */
 210                 behind-32bit-controller@7f000000 {
 211                         compatible = "simple-bus";
 212                         #address-cells = <0x2>;
 213                         #size-cells = <0x2>;
 214                         ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>;
 215                         /* Host phy ram starts at 0x200M */
 216                         dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>;
 217                         dma-coherent;
 218
 219                         eth0: ethernet@20000 {
 220                                 compatible = "marvell,armada-ac5-neta";
 221                                 reg = <0x0 0x20000 0x0 0x4000>;
 222                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 223                                 clocks = <&cnm_clock>;
 224                                 phy-mode = "sgmii";
 225                                 status = "disabled";
 226                         };
 227
 228                         eth1: ethernet@24000 {
 229                                 compatible = "marvell,armada-ac5-neta";
 230                                 reg = <0x0 0x24000 0x0 0x4000>;
 231                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 232                                 clocks = <&cnm_clock>;
 233                                 phy-mode = "sgmii";
 234                                 status = "disabled";
 235                         };
 236
 237                         usb0: usb@80000 {
 238                                 compatible = "marvell,orion-ehci";
 239                                 reg = <0x0 0x80000 0x0 0x500>;
 240                                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 241                                 status = "disabled";
 242                         };
 243
 244                         usb1: usb@a0000 {
 245                                 compatible = "marvell,orion-ehci";
 246                                 reg = <0x0 0xa0000 0x0 0x500>;
 247                                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 248                                 status = "disabled";
 249                         };
 250                 };
 251
 252                 pinctrl0: pinctrl@80020100 {
 253                         compatible = "marvell,ac5-pinctrl";
 254                         reg = <0 0x80020100 0 0x20>;
 255
 256                         i2c0_pins: i2c0-pins {
 257                                 marvell,pins = "mpp26", "mpp27";
 258                                 marvell,function = "i2c0";
 259                         };
 260
 261                         i2c0_gpio: i2c0-gpio-pins {
 262                                 marvell,pins = "mpp26", "mpp27";
 263                                 marvell,function = "gpio";
 264                         };
 265
 266                         i2c1_pins: i2c1-pins {
 267                                 marvell,pins = "mpp20", "mpp21";
 268                                 marvell,function = "i2c1";
 269                         };
 270
 271                         i2c1_gpio: i2c1-gpio-pins {
 272                                 marvell,pins = "mpp20", "mpp21";
 273                                 marvell,function = "i2c1";
 274                         };
 275                 };
 276
 277                 spi0: spi@805a0000 {
 278                         compatible = "marvell,armada-3700-spi";
 279                         reg = <0x0 0x805a0000 0x0 0x50>;
 280                         #address-cells = <0x1>;
 281                         #size-cells = <0x0>;
 282                         clocks = <&spi_clock>;
 283                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 284                         num-cs = <1>;
 285                         status = "disabled";
 286                 };
 287
 288                 spi1: spi@805a8000 {
 289                         compatible = "marvell,armada-3700-spi";
 290                         reg = <0x0 0x805a8000 0x0 0x50>;
 291                         #address-cells = <0x1>;
 292                         #size-cells = <0x0>;
 293                         clocks = <&spi_clock>;
 294                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 295                         num-cs = <1>;
 296                         status = "disabled";
 297                 };
 298
 299                 gic: interrupt-controller@80600000 {
 300                         compatible = "arm,gic-v3";
 301                         #interrupt-cells = <3>;
 302                         interrupt-controller;
 303                         reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */
 304                               <0x0 0x80660000 0x0 0x40000>; /* GICR */
 305                         interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
 306                 };
 307         };
 308
 309         clocks {
 310                 cnm_clock: cnm-clock {
 311                         compatible = "fixed-clock";
 312                         #clock-cells = <0>;
 313                         clock-frequency = <328000000>;
 314                 };
 315
 316                 spi_clock: spi-clock {
 317                         compatible = "fixed-clock";
 318                         #clock-cells = <0>;
 319                         clock-frequency = <200000000>;
 320                 };
 321         };
 322 };