1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for lg1313 SoC
5 * Copyright (C) 2016, LG Electronics
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 compatible = "lge,lg1313";
16 interrupt-parent = <&gic>;
24 compatible = "arm,cortex-a53";
26 next-level-cache = <&L2_0>;
30 compatible = "arm,cortex-a53";
32 enable-method = "psci";
33 next-level-cache = <&L2_0>;
37 compatible = "arm,cortex-a53";
39 enable-method = "psci";
40 next-level-cache = <&L2_0>;
44 compatible = "arm,cortex-a53";
46 enable-method = "psci";
47 next-level-cache = <&L2_0>;
55 compatible = "arm,psci-0.2", "arm,psci";
57 cpu_suspend = <0x84000001>;
58 cpu_off = <0x84000002>;
59 cpu_on = <0x84000003>;
62 gic: interrupt-controller@c0001000 {
63 #interrupt-cells = <3>;
64 compatible = "arm,gic-400";
66 reg = <0x0 0xc0001000 0x1000>,
67 <0x0 0xc0002000 0x2000>,
68 <0x0 0xc0004000 0x2000>,
69 <0x0 0xc0006000 0x2000>;
73 compatible = "arm,cortex-a53-pmu";
74 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
75 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
78 interrupt-affinity = <&cpu0>,
85 compatible = "arm,armv8-timer";
86 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x0f) |
88 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x0f) |
90 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x0f) |
92 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x0f) |
99 compatible = "fixed-clock";
100 clock-frequency = <198000000>;
101 clock-output-names = "BUSCLK";
105 #address-cells = <2>;
108 compatible = "simple-bus";
109 interrupt-parent = <&gic>;
112 eth0: ethernet@c3700000 {
113 compatible = "cdns,gem";
114 reg = <0x0 0xc3700000 0x1000>;
115 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
116 clocks = <&clk_bus>, <&clk_bus>;
117 clock-names = "hclk", "pclk";
119 /* Filled in by boot */
120 mac-address = [ 00 00 00 00 00 00 ];
125 #address-cells = <2>;
127 #interrupt-cells = <3>;
129 compatible = "simple-bus";
130 interrupt-parent = <&gic>;
133 timers: timer@fd100000 {
134 compatible = "arm,sp804", "arm,primecell";
135 reg = <0x0 0xfd100000 0x1000>;
136 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
137 clocks = <&clk_bus>, <&clk_bus>, <&clk_bus>;
138 clock-names = "timer0clk", "timer1clk", "apb_pclk";
140 wdog: watchdog@fd200000 {
141 compatible = "arm,sp805", "arm,primecell";
142 reg = <0x0 0xfd200000 0x1000>;
143 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
144 clocks = <&clk_bus>, <&clk_bus>;
145 clock-names = "wdog_clk", "apb_pclk";
147 uart0: serial@fe000000 {
148 compatible = "arm,pl011", "arm,primecell";
149 reg = <0x0 0xfe000000 0x1000>;
150 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
152 clock-names = "apb_pclk";
155 uart1: serial@fe100000 {
156 compatible = "arm,pl011", "arm,primecell";
157 reg = <0x0 0xfe100000 0x1000>;
158 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
160 clock-names = "apb_pclk";
163 uart2: serial@fe200000 {
164 compatible = "arm,pl011", "arm,primecell";
165 reg = <0x0 0xfe200000 0x1000>;
166 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
168 clock-names = "apb_pclk";
172 compatible = "arm,pl022", "arm,primecell";
173 reg = <0x0 0xfe800000 0x1000>;
174 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
176 clock-names = "apb_pclk";
179 compatible = "arm,pl022", "arm,primecell";
180 reg = <0x0 0xfe900000 0x1000>;
181 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
183 clock-names = "apb_pclk";
185 dmac0: dma-controller@c1128000 {
186 compatible = "arm,pl330", "arm,primecell";
187 reg = <0x0 0xc1128000 0x1000>;
188 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
190 clock-names = "apb_pclk";
193 gpio0: gpio@fd400000 {
195 compatible = "arm,pl061", "arm,primecell";
197 reg = <0x0 0xfd400000 0x1000>;
199 clock-names = "apb_pclk";
202 gpio1: gpio@fd410000 {
204 compatible = "arm,pl061", "arm,primecell";
206 reg = <0x0 0xfd410000 0x1000>;
208 clock-names = "apb_pclk";
211 gpio2: gpio@fd420000 {
213 compatible = "arm,pl061", "arm,primecell";
215 reg = <0x0 0xfd420000 0x1000>;
217 clock-names = "apb_pclk";
220 gpio3: gpio@fd430000 {
222 compatible = "arm,pl061", "arm,primecell";
224 reg = <0x0 0xfd430000 0x1000>;
226 clock-names = "apb_pclk";
228 gpio4: gpio@fd440000 {
230 compatible = "arm,pl061", "arm,primecell";
232 reg = <0x0 0xfd440000 0x1000>;
234 clock-names = "apb_pclk";
237 gpio5: gpio@fd450000 {
239 compatible = "arm,pl061", "arm,primecell";
241 reg = <0x0 0xfd450000 0x1000>;
243 clock-names = "apb_pclk";
246 gpio6: gpio@fd460000 {
248 compatible = "arm,pl061", "arm,primecell";
250 reg = <0x0 0xfd460000 0x1000>;
252 clock-names = "apb_pclk";
255 gpio7: gpio@fd470000 {
257 compatible = "arm,pl061", "arm,primecell";
259 reg = <0x0 0xfd470000 0x1000>;
261 clock-names = "apb_pclk";
264 gpio8: gpio@fd480000 {
266 compatible = "arm,pl061", "arm,primecell";
268 reg = <0x0 0xfd480000 0x1000>;
270 clock-names = "apb_pclk";
273 gpio9: gpio@fd490000 {
275 compatible = "arm,pl061", "arm,primecell";
277 reg = <0x0 0xfd490000 0x1000>;
279 clock-names = "apb_pclk";
282 gpio10: gpio@fd4a0000 {
284 compatible = "arm,pl061", "arm,primecell";
286 reg = <0x0 0xfd4a0000 0x1000>;
288 clock-names = "apb_pclk";
291 gpio11: gpio@fd4b0000 {
293 compatible = "arm,pl061", "arm,primecell";
295 reg = <0x0 0xfd4b0000 0x1000>;
297 clock-names = "apb_pclk";
299 gpio12: gpio@fd4c0000 {
301 compatible = "arm,pl061", "arm,primecell";
303 reg = <0x0 0xfd4c0000 0x1000>;
305 clock-names = "apb_pclk";
308 gpio13: gpio@fd4d0000 {
310 compatible = "arm,pl061", "arm,primecell";
312 reg = <0x0 0xfd4d0000 0x1000>;
314 clock-names = "apb_pclk";
317 gpio14: gpio@fd4e0000 {
319 compatible = "arm,pl061", "arm,primecell";
321 reg = <0x0 0xfd4e0000 0x1000>;
323 clock-names = "apb_pclk";
326 gpio15: gpio@fd4f0000 {
328 compatible = "arm,pl061", "arm,primecell";
330 reg = <0x0 0xfd4f0000 0x1000>;
332 clock-names = "apb_pclk";
335 gpio16: gpio@fd500000 {
337 compatible = "arm,pl061", "arm,primecell";
339 reg = <0x0 0xfd500000 0x1000>;
341 clock-names = "apb_pclk";
344 gpio17: gpio@fd510000 {
346 compatible = "arm,pl061", "arm,primecell";
348 reg = <0x0 0xfd510000 0x1000>;
350 clock-names = "apb_pclk";