arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi

   1 /*
   2  * DTS File for HiSilicon Hi3798cv200 SoC.
   3  *
   4  * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
   5  *
   6  * Released under the GPLv2 only.
   7  * SPDX-License-Identifier: GPL-2.0
   8  */
   9
  10 #include <dt-bindings/clock/histb-clock.h>
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/phy/phy.h>
  14 #include <dt-bindings/reset/ti-syscon.h>
  15
  16 / {
  17         compatible = "hisilicon,hi3798cv200";
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         psci {
  23                 compatible = "arm,psci-0.2";
  24                 method = "smc";
  25         };
  26
  27         cpus {
  28                 #address-cells = <2>;
  29                 #size-cells = <0>;
  30
  31                 cpu@0 {
  32                         compatible = "arm,cortex-a53";
  33                         device_type = "cpu";
  34                         reg = <0x0 0x0>;
  35                         enable-method = "psci";
  36                 };
  37
  38                 cpu@1 {
  39                         compatible = "arm,cortex-a53";
  40                         device_type = "cpu";
  41                         reg = <0x0 0x1>;
  42                         enable-method = "psci";
  43                 };
  44
  45                 cpu@2 {
  46                         compatible = "arm,cortex-a53";
  47                         device_type = "cpu";
  48                         reg = <0x0 0x2>;
  49                         enable-method = "psci";
  50                 };
  51
  52                 cpu@3 {
  53                         compatible = "arm,cortex-a53";
  54                         device_type = "cpu";
  55                         reg = <0x0 0x3>;
  56                         enable-method = "psci";
  57                 };
  58         };
  59
  60         gic: interrupt-controller@f1001000 {
  61                 compatible = "arm,gic-400";
  62                 reg = <0x0 0xf1001000 0x0 0x1000>,  /* GICD */
  63                       <0x0 0xf1002000 0x0 0x100>;   /* GICC */
  64                 #address-cells = <0>;
  65                 #interrupt-cells = <3>;
  66                 interrupt-controller;
  67         };
  68
  69         timer {
  70                 compatible = "arm,armv8-timer";
  71                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
  72                               IRQ_TYPE_LEVEL_LOW)>,
  73                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
  74                               IRQ_TYPE_LEVEL_LOW)>,
  75                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
  76                               IRQ_TYPE_LEVEL_LOW)>,
  77                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
  78                               IRQ_TYPE_LEVEL_LOW)>;
  79         };
  80
  81         soc: soc@f0000000 {
  82                 compatible = "simple-bus";
  83                 #address-cells = <1>;
  84                 #size-cells = <1>;
  85                 ranges = <0x0 0x0 0xf0000000 0x10000000>;
  86
  87                 crg: clock-reset-controller@8a22000 {
  88                         compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd";
  89                         reg = <0x8a22000 0x1000>;
  90                         #clock-cells = <1>;
  91                         #reset-cells = <2>;
  92
  93                         gmacphyrst: reset-controller {
  94                                 compatible = "ti,syscon-reset";
  95                                 #reset-cells = <1>;
  96                                 ti,reset-bits =
  97                                         <0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR |
  98                                          DEASSERT_SET|STATUS_NONE)>,
  99                                         <0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR |
 100                                          DEASSERT_SET|STATUS_NONE)>;
 101                         };
 102                 };
 103
 104                 sysctrl: system-controller@8000000 {
 105                         compatible = "hisilicon,hi3798cv200-sysctrl", "syscon";
 106                         reg = <0x8000000 0x1000>;
 107                         #clock-cells = <1>;
 108                         #reset-cells = <2>;
 109                 };
 110
 111                 perictrl: peripheral-controller@8a20000 {
 112                         compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
 113                                      "simple-mfd";
 114                         reg = <0x8a20000 0x1000>;
 115                         #address-cells = <1>;
 116                         #size-cells = <1>;
 117                         ranges = <0x0 0x8a20000 0x1000>;
 118
 119                         usb2_phy1: usb2-phy@120 {
 120                                 compatible = "hisilicon,hi3798cv200-usb2-phy";
 121                                 reg = <0x120 0x4>;
 122                                 clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
 123                                 resets = <&crg 0xbc 4>;
 124                                 #address-cells = <1>;
 125                                 #size-cells = <0>;
 126
 127                                 usb2_phy1_port0: phy@0 {
 128                                         reg = <0>;
 129                                         #phy-cells = <0>;
 130                                         resets = <&crg 0xbc 8>;
 131                                 };
 132
 133                                 usb2_phy1_port1: phy@1 {
 134                                         reg = <1>;
 135                                         #phy-cells = <0>;
 136                                         resets = <&crg 0xbc 9>;
 137                                 };
 138                         };
 139
 140                         usb2_phy2: usb2-phy@124 {
 141                                 compatible = "hisilicon,hi3798cv200-usb2-phy";
 142                                 reg = <0x124 0x4>;
 143                                 clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
 144                                 resets = <&crg 0xbc 6>;
 145                                 #address-cells = <1>;
 146                                 #size-cells = <0>;
 147
 148                                 usb2_phy2_port0: phy@0 {
 149                                         reg = <0>;
 150                                         #phy-cells = <0>;
 151                                         resets = <&crg 0xbc 10>;
 152                                 };
 153                         };
 154
 155                         combphy0: phy@850 {
 156                                 compatible = "hisilicon,hi3798cv200-combphy";
 157                                 reg = <0x850 0x8>;
 158                                 #phy-cells = <1>;
 159                                 clocks = <&crg HISTB_COMBPHY0_CLK>;
 160                                 resets = <&crg 0x188 4>;
 161                                 assigned-clocks = <&crg HISTB_COMBPHY0_CLK>;
 162                                 assigned-clock-rates = <100000000>;
 163                                 hisilicon,fixed-mode = <PHY_TYPE_USB3>;
 164                         };
 165
 166                         combphy1: phy@858 {
 167                                 compatible = "hisilicon,hi3798cv200-combphy";
 168                                 reg = <0x858 0x8>;
 169                                 #phy-cells = <1>;
 170                                 clocks = <&crg HISTB_COMBPHY1_CLK>;
 171                                 resets = <&crg 0x188 12>;
 172                                 assigned-clocks = <&crg HISTB_COMBPHY1_CLK>;
 173                                 assigned-clock-rates = <100000000>;
 174                                 hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
 175                         };
 176                 };
 177
 178                 uart0: serial@8b00000 {
 179                         compatible = "arm,pl011", "arm,primecell";
 180                         reg = <0x8b00000 0x1000>;
 181                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 182                         clocks = <&sysctrl HISTB_UART0_CLK>;
 183                         clock-names = "apb_pclk";
 184                         status = "disabled";
 185                 };
 186
 187                 uart2: serial@8b02000 {
 188                         compatible = "arm,pl011", "arm,primecell";
 189                         reg = <0x8b02000 0x1000>;
 190                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 191                         clocks = <&crg HISTB_UART2_CLK>;
 192                         clock-names = "apb_pclk";
 193                         status = "disabled";
 194                 };
 195
 196                 i2c0: i2c@8b10000 {
 197                         compatible = "hisilicon,hix5hd2-i2c";
 198                         reg = <0x8b10000 0x1000>;
 199                         #address-cells = <1>;
 200                         #size-cells = <0>;
 201                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 202                         clock-frequency = <400000>;
 203                         clocks = <&crg HISTB_I2C0_CLK>;
 204                         status = "disabled";
 205                 };
 206
 207                 i2c1: i2c@8b11000 {
 208                         compatible = "hisilicon,hix5hd2-i2c";
 209                         reg = <0x8b11000 0x1000>;
 210                         #address-cells = <1>;
 211                         #size-cells = <0>;
 212                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 213                         clock-frequency = <400000>;
 214                         clocks = <&crg HISTB_I2C1_CLK>;
 215                         status = "disabled";
 216                 };
 217
 218                 i2c2: i2c@8b12000 {
 219                         compatible = "hisilicon,hix5hd2-i2c";
 220                         reg = <0x8b12000 0x1000>;
 221                         #address-cells = <1>;
 222                         #size-cells = <0>;
 223                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 224                         clock-frequency = <400000>;
 225                         clocks = <&crg HISTB_I2C2_CLK>;
 226                         status = "disabled";
 227                 };
 228
 229                 i2c3: i2c@8b13000 {
 230                         compatible = "hisilicon,hix5hd2-i2c";
 231                         reg = <0x8b13000 0x1000>;
 232                         #address-cells = <1>;
 233                         #size-cells = <0>;
 234                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 235                         clock-frequency = <400000>;
 236                         clocks = <&crg HISTB_I2C3_CLK>;
 237                         status = "disabled";
 238                 };
 239
 240                 i2c4: i2c@8b14000 {
 241                         compatible = "hisilicon,hix5hd2-i2c";
 242                         reg = <0x8b14000 0x1000>;
 243                         #address-cells = <1>;
 244                         #size-cells = <0>;
 245                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 246                         clock-frequency = <400000>;
 247                         clocks = <&crg HISTB_I2C4_CLK>;
 248                         status = "disabled";
 249                 };
 250
 251                 spi0: spi@8b1a000 {
 252                         compatible = "arm,pl022", "arm,primecell";
 253                         reg = <0x8b1a000 0x1000>;
 254                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 255                         num-cs = <1>;
 256                         cs-gpios = <&gpio7 1 0>;
 257                         clocks = <&crg HISTB_SPI0_CLK>;
 258                         clock-names = "apb_pclk";
 259                         #address-cells = <1>;
 260                         #size-cells = <0>;
 261                         status = "disabled";
 262                 };
 263
 264                 sd0: mmc@9820000 {
 265                         compatible = "snps,dw-mshc";
 266                         reg = <0x9820000 0x10000>;
 267                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 268                         clocks = <&crg HISTB_SDIO0_CIU_CLK>,
 269                                  <&crg HISTB_SDIO0_BIU_CLK>;
 270                         clock-names = "ciu", "biu";
 271                         resets = <&crg 0x9c 4>;
 272                         reset-names = "reset";
 273                         status = "disabled";
 274                 };
 275
 276                 emmc: mmc@9830000 {
 277                         compatible = "snps,dw-mshc";
 278                         reg = <0x9830000 0x10000>;
 279                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 280                         clocks = <&crg HISTB_MMC_CIU_CLK>,
 281                                  <&crg HISTB_MMC_BIU_CLK>;
 282                         clock-names = "ciu", "biu";
 283                 };
 284
 285                 gpio0: gpio@8b20000 {
 286                         compatible = "arm,pl061", "arm,primecell";
 287                         reg = <0x8b20000 0x1000>;
 288                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 289                         gpio-controller;
 290                         #gpio-cells = <2>;
 291                         interrupt-controller;
 292                         #interrupt-cells = <2>;
 293                         clocks = <&crg HISTB_APB_CLK>;
 294                         clock-names = "apb_pclk";
 295                         status = "disabled";
 296                 };
 297
 298                 gpio1: gpio@8b21000 {
 299                         compatible = "arm,pl061", "arm,primecell";
 300                         reg = <0x8b21000 0x1000>;
 301                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 302                         gpio-controller;
 303                         #gpio-cells = <2>;
 304                         interrupt-controller;
 305                         #interrupt-cells = <2>;
 306                         clocks = <&crg HISTB_APB_CLK>;
 307                         clock-names = "apb_pclk";
 308                         status = "disabled";
 309                 };
 310
 311                 gpio2: gpio@8b22000 {
 312                         compatible = "arm,pl061", "arm,primecell";
 313                         reg = <0x8b22000 0x1000>;
 314                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 315                         gpio-controller;
 316                         #gpio-cells = <2>;
 317                         interrupt-controller;
 318                         #interrupt-cells = <2>;
 319                         clocks = <&crg HISTB_APB_CLK>;
 320                         clock-names = "apb_pclk";
 321                         status = "disabled";
 322                 };
 323
 324                 gpio3: gpio@8b23000 {
 325                         compatible = "arm,pl061", "arm,primecell";
 326                         reg = <0x8b23000 0x1000>;
 327                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 328                         gpio-controller;
 329                         #gpio-cells = <2>;
 330                         interrupt-controller;
 331                         #interrupt-cells = <2>;
 332                         clocks = <&crg HISTB_APB_CLK>;
 333                         clock-names = "apb_pclk";
 334                         status = "disabled";
 335                 };
 336
 337                 gpio4: gpio@8b24000 {
 338                         compatible = "arm,pl061", "arm,primecell";
 339                         reg = <0x8b24000 0x1000>;
 340                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 341                         gpio-controller;
 342                         #gpio-cells = <2>;
 343                         interrupt-controller;
 344                         #interrupt-cells = <2>;
 345                         clocks = <&crg HISTB_APB_CLK>;
 346                         clock-names = "apb_pclk";
 347                         status = "disabled";
 348                 };
 349
 350                 gpio5: gpio@8004000 {
 351                         compatible = "arm,pl061", "arm,primecell";
 352                         reg = <0x8004000 0x1000>;
 353                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 354                         gpio-controller;
 355                         #gpio-cells = <2>;
 356                         interrupt-controller;
 357                         #interrupt-cells = <2>;
 358                         clocks = <&crg HISTB_APB_CLK>;
 359                         clock-names = "apb_pclk";
 360                         status = "disabled";
 361                 };
 362
 363                 gpio6: gpio@8b26000 {
 364                         compatible = "arm,pl061", "arm,primecell";
 365                         reg = <0x8b26000 0x1000>;
 366                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 367                         gpio-controller;
 368                         #gpio-cells = <2>;
 369                         interrupt-controller;
 370                         #interrupt-cells = <2>;
 371                         clocks = <&crg HISTB_APB_CLK>;
 372                         clock-names = "apb_pclk";
 373                         status = "disabled";
 374                 };
 375
 376                 gpio7: gpio@8b27000 {
 377                         compatible = "arm,pl061", "arm,primecell";
 378                         reg = <0x8b27000 0x1000>;
 379                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 380                         gpio-controller;
 381                         #gpio-cells = <2>;
 382                         interrupt-controller;
 383                         #interrupt-cells = <2>;
 384                         clocks = <&crg HISTB_APB_CLK>;
 385                         clock-names = "apb_pclk";
 386                         status = "disabled";
 387                 };
 388
 389                 gpio8: gpio@8b28000 {
 390                         compatible = "arm,pl061", "arm,primecell";
 391                         reg = <0x8b28000 0x1000>;
 392                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 393                         gpio-controller;
 394                         #gpio-cells = <2>;
 395                         interrupt-controller;
 396                         #interrupt-cells = <2>;
 397                         clocks = <&crg HISTB_APB_CLK>;
 398                         clock-names = "apb_pclk";
 399                         status = "disabled";
 400                 };
 401
 402                 gpio9: gpio@8b29000 {
 403                         compatible = "arm,pl061", "arm,primecell";
 404                         reg = <0x8b29000 0x1000>;
 405                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 406                         gpio-controller;
 407                         #gpio-cells = <2>;
 408                         interrupt-controller;
 409                         #interrupt-cells = <2>;
 410                         clocks = <&crg HISTB_APB_CLK>;
 411                         clock-names = "apb_pclk";
 412                         status = "disabled";
 413                 };
 414
 415                 gpio10: gpio@8b2a000 {
 416                         compatible = "arm,pl061", "arm,primecell";
 417                         reg = <0x8b2a000 0x1000>;
 418                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 419                         gpio-controller;
 420                         #gpio-cells = <2>;
 421                         interrupt-controller;
 422                         #interrupt-cells = <2>;
 423                         clocks = <&crg HISTB_APB_CLK>;
 424                         clock-names = "apb_pclk";
 425                         status = "disabled";
 426                 };
 427
 428                 gpio11: gpio@8b2b000 {
 429                         compatible = "arm,pl061", "arm,primecell";
 430                         reg = <0x8b2b000 0x1000>;
 431                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 432                         gpio-controller;
 433                         #gpio-cells = <2>;
 434                         interrupt-controller;
 435                         #interrupt-cells = <2>;
 436                         clocks = <&crg HISTB_APB_CLK>;
 437                         clock-names = "apb_pclk";
 438                         status = "disabled";
 439                 };
 440
 441                 gpio12: gpio@8b2c000 {
 442                         compatible = "arm,pl061", "arm,primecell";
 443                         reg = <0x8b2c000 0x1000>;
 444                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 445                         gpio-controller;
 446                         #gpio-cells = <2>;
 447                         interrupt-controller;
 448                         #interrupt-cells = <2>;
 449                         clocks = <&crg HISTB_APB_CLK>;
 450                         clock-names = "apb_pclk";
 451                         status = "disabled";
 452                 };
 453
 454                 gmac0: ethernet@9840000 {
 455                         compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
 456                         reg = <0x9840000 0x1000>,
 457                               <0x984300c 0x4>;
 458                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 459                         clocks = <&crg HISTB_ETH0_MAC_CLK>,
 460                                  <&crg HISTB_ETH0_MACIF_CLK>;
 461                         clock-names = "mac_core", "mac_ifc";
 462                         resets = <&crg 0xcc 8>,
 463                                  <&crg 0xcc 10>,
 464                                  <&gmacphyrst 0>;
 465                         reset-names = "mac_core", "mac_ifc", "phy";
 466                         status = "disabled";
 467                 };
 468
 469                 gmac1: ethernet@9841000 {
 470                         compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
 471                         reg = <0x9841000 0x1000>,
 472                               <0x9843010 0x4>;
 473                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 474                         clocks = <&crg HISTB_ETH1_MAC_CLK>,
 475                                  <&crg HISTB_ETH1_MACIF_CLK>;
 476                         clock-names = "mac_core", "mac_ifc";
 477                         resets = <&crg 0xcc 9>,
 478                                  <&crg 0xcc 11>,
 479                                  <&gmacphyrst 1>;
 480                         reset-names = "mac_core", "mac_ifc", "phy";
 481                         status = "disabled";
 482                 };
 483
 484                 ir: ir@8001000 {
 485                         compatible = "hisilicon,hix5hd2-ir";
 486                         reg = <0x8001000 0x1000>;
 487                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 488                         clocks = <&sysctrl HISTB_IR_CLK>;
 489                         status = "disabled";
 490                 };
 491
 492                 pcie: pcie@9860000 {
 493                         compatible = "hisilicon,hi3798cv200-pcie";
 494                         reg = <0x9860000 0x1000>,
 495                               <0x0 0x2000>,
 496                               <0x2000000 0x01000000>;
 497                         reg-names = "control", "rc-dbi", "config";
 498                         #address-cells = <3>;
 499                         #size-cells = <2>;
 500                         device_type = "pci";
 501                         bus-range = <0 15>;
 502                         num-lanes = <1>;
 503                         ranges = <0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000
 504                                   0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000>;
 505                         interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
 506                         interrupt-names = "msi";
 507                         #interrupt-cells = <1>;
 508                         interrupt-map-mask = <0 0 0 0>;
 509                         interrupt-map = <0 0 0 0 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>;
 510                         clocks = <&crg HISTB_PCIE_AUX_CLK>,
 511                                  <&crg HISTB_PCIE_PIPE_CLK>,
 512                                  <&crg HISTB_PCIE_SYS_CLK>,
 513                                  <&crg HISTB_PCIE_BUS_CLK>;
 514                         clock-names = "aux", "pipe", "sys", "bus";
 515                         resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
 516                         reset-names = "soft", "sys", "bus";
 517                         phys = <&combphy1 PHY_TYPE_PCIE>;
 518                         phy-names = "phy";
 519                         status = "disabled";
 520                 };
 521
 522                 ohci: ohci@9880000 {
 523                         compatible = "generic-ohci";
 524                         reg = <0x9880000 0x10000>;
 525                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 526                         clocks = <&crg HISTB_USB2_BUS_CLK>,
 527                                  <&crg HISTB_USB2_12M_CLK>,
 528                                  <&crg HISTB_USB2_48M_CLK>;
 529                         clock-names = "bus", "clk12", "clk48";
 530                         resets = <&crg 0xb8 12>;
 531                         reset-names = "bus";
 532                         phys = <&usb2_phy1_port0>;
 533                         phy-names = "usb";
 534                         status = "disabled";
 535                 };
 536
 537                 ehci: ehci@9890000 {
 538                         compatible = "generic-ehci";
 539                         reg = <0x9890000 0x10000>;
 540                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 541                         clocks = <&crg HISTB_USB2_BUS_CLK>,
 542                                  <&crg HISTB_USB2_PHY_CLK>,
 543                                  <&crg HISTB_USB2_UTMI_CLK>;
 544                         clock-names = "bus", "phy", "utmi";
 545                         resets = <&crg 0xb8 12>,
 546                                  <&crg 0xb8 16>,
 547                                  <&crg 0xb8 13>;
 548                         reset-names = "bus", "phy", "utmi";
 549                         phys = <&usb2_phy1_port0>;
 550                         phy-names = "usb";
 551                         status = "disabled";
 552                 };
 553         };
 554 };