1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for Hisilicon Hi3670 SoC
5 * Copyright (C) 2016, Hisilicon Ltd.
6 * Copyright (C) 2018, Linaro Ltd.
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/hi3670-clock.h>
13 compatible = "hisilicon,hi3670";
14 interrupt-parent = <&gic>;
19 compatible = "arm,psci-0.2";
59 compatible = "arm,cortex-a53";
62 enable-method = "psci";
66 compatible = "arm,cortex-a53";
69 enable-method = "psci";
73 compatible = "arm,cortex-a53";
76 enable-method = "psci";
80 compatible = "arm,cortex-a53";
83 enable-method = "psci";
87 compatible = "arm,cortex-a73";
90 enable-method = "psci";
94 compatible = "arm,cortex-a73";
97 enable-method = "psci";
101 compatible = "arm,cortex-a73";
104 enable-method = "psci";
108 compatible = "arm,cortex-a73";
111 enable-method = "psci";
115 gic: interrupt-controller@e82b0000 {
116 compatible = "arm,gic-400";
117 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
118 <0x0 0xe82b2000 0 0x2000>, /* GICC */
119 <0x0 0xe82b4000 0 0x2000>, /* GICH */
120 <0x0 0xe82b6000 0 0x2000>; /* GICV */
121 #interrupt-cells = <3>;
122 #address-cells = <0>;
123 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
124 IRQ_TYPE_LEVEL_HIGH)>;
125 interrupt-controller;
129 compatible = "arm,armv8-timer";
130 interrupt-parent = <&gic>;
131 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
132 IRQ_TYPE_LEVEL_LOW)>,
133 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
134 IRQ_TYPE_LEVEL_LOW)>,
135 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
136 IRQ_TYPE_LEVEL_LOW)>,
137 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
138 IRQ_TYPE_LEVEL_LOW)>;
139 clock-frequency = <1920000>;
143 compatible = "simple-bus";
144 #address-cells = <2>;
148 crg_ctrl: crg_ctrl@fff35000 {
149 compatible = "hisilicon,hi3670-crgctrl", "syscon";
150 reg = <0x0 0xfff35000 0x0 0x1000>;
154 pctrl: pctrl@e8a09000 {
155 compatible = "hisilicon,hi3670-pctrl", "syscon";
156 reg = <0x0 0xe8a09000 0x0 0x1000>;
160 pmuctrl: crg_ctrl@fff34000 {
161 compatible = "hisilicon,hi3670-pmuctrl", "syscon";
162 reg = <0x0 0xfff34000 0x0 0x1000>;
166 sctrl: sctrl@fff0a000 {
167 compatible = "hisilicon,hi3670-sctrl", "syscon";
168 reg = <0x0 0xfff0a000 0x0 0x1000>;
172 iomcu: iomcu@ffd7e000 {
173 compatible = "hisilicon,hi3670-iomcu", "syscon";
174 reg = <0x0 0xffd7e000 0x0 0x1000>;
178 media1_crg: media1_crgctrl@e87ff000 {
179 compatible = "hisilicon,hi3670-media1-crg", "syscon";
180 reg = <0x0 0xe87ff000 0x0 0x1000>;
184 media2_crg: media2_crgctrl@e8900000 {
185 compatible = "hisilicon,hi3670-media2-crg","syscon";
186 reg = <0x0 0xe8900000 0x0 0x1000>;
190 uart0: serial@fdf02000 {
191 compatible = "arm,pl011", "arm,primecell";
192 reg = <0x0 0xfdf02000 0x0 0x1000>;
193 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&crg_ctrl HI3670_CLK_GATE_UART0>,
195 <&crg_ctrl HI3670_PCLK>;
196 clock-names = "uartclk", "apb_pclk";
197 pinctrl-names = "default";
198 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
202 uart1: serial@fdf00000 {
203 compatible = "arm,pl011", "arm,primecell";
204 reg = <0x0 0xfdf00000 0x0 0x1000>;
205 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
206 clocks = <&crg_ctrl HI3670_CLK_GATE_UART1>,
207 <&crg_ctrl HI3670_PCLK>;
208 clock-names = "uartclk", "apb_pclk";
209 pinctrl-names = "default";
213 uart2: serial@fdf03000 {
214 compatible = "arm,pl011", "arm,primecell";
215 reg = <0x0 0xfdf03000 0x0 0x1000>;
216 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&crg_ctrl HI3670_CLK_GATE_UART2>,
218 <&crg_ctrl HI3670_PCLK>;
219 clock-names = "uartclk", "apb_pclk";
220 pinctrl-names = "default";
221 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
225 uart3: serial@ffd74000 {
226 compatible = "arm,pl011", "arm,primecell";
227 reg = <0x0 0xffd74000 0x0 0x1000>;
228 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&crg_ctrl HI3670_CLK_GATE_UART3>,
230 <&crg_ctrl HI3670_PCLK>;
231 clock-names = "uartclk", "apb_pclk";
232 pinctrl-names = "default";
233 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
237 uart4: serial@fdf01000 {
238 compatible = "arm,pl011", "arm,primecell";
239 reg = <0x0 0xfdf01000 0x0 0x1000>;
240 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&crg_ctrl HI3670_CLK_GATE_UART4>,
242 <&crg_ctrl HI3670_PCLK>;
243 clock-names = "uartclk", "apb_pclk";
244 pinctrl-names = "default";
245 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
249 uart5: serial@fdf05000 {
250 compatible = "arm,pl011", "arm,primecell";
251 reg = <0x0 0xfdf05000 0x0 0x1000>;
252 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&crg_ctrl HI3670_CLK_GATE_UART5>,
254 <&crg_ctrl HI3670_PCLK>;
255 clock-names = "uartclk", "apb_pclk";
256 pinctrl-names = "default";
260 uart6: serial@fff32000 {
261 compatible = "arm,pl011", "arm,primecell";
262 reg = <0x0 0xfff32000 0x0 0x1000>;
263 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&crg_ctrl HI3670_CLK_UART6>,
265 <&crg_ctrl HI3670_PCLK>;
266 clock-names = "uartclk", "apb_pclk";
267 pinctrl-names = "default";
268 pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>;
272 gpio0: gpio@e8a0b000 {
273 compatible = "arm,pl061", "arm,primecell";
274 reg = <0x0 0xe8a0b000 0x0 0x1000>;
275 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
278 gpio-ranges = <&pmx0 1 0 1 &pmx0 3 1 5>;
279 interrupt-controller;
280 #interrupt-cells = <2>;
281 clocks = <&crg_ctrl HI3670_PCLK_GPIO0>;
282 clock-names = "apb_pclk";
285 gpio1: gpio@e8a0c000 {
286 compatible = "arm,pl061", "arm,primecell";
287 reg = <0x0 0xe8a0c000 0x0 0x1000>;
288 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
291 interrupt-controller;
292 #interrupt-cells = <2>;
293 clocks = <&crg_ctrl HI3670_PCLK_GPIO1>;
294 clock-names = "apb_pclk";
297 gpio2: gpio@e8a0d000 {
298 compatible = "arm,pl061", "arm,primecell";
299 reg = <0x0 0xe8a0d000 0x0 0x1000>;
300 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
303 gpio-ranges = <&pmx0 1 6 7>;
304 interrupt-controller;
305 #interrupt-cells = <2>;
306 clocks = <&crg_ctrl HI3670_PCLK_GPIO2>;
307 clock-names = "apb_pclk";
310 gpio3: gpio@e8a0e000 {
311 compatible = "arm,pl061", "arm,primecell";
312 reg = <0x0 0xe8a0e000 0x0 0x1000>;
313 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
316 gpio-ranges = <&pmx0 0 13 4 &pmx0 7 17 1>;
317 interrupt-controller;
318 #interrupt-cells = <2>;
319 clocks = <&crg_ctrl HI3670_PCLK_GPIO3>;
320 clock-names = "apb_pclk";
323 gpio4: gpio@e8a0f000 {
324 compatible = "arm,pl061", "arm,primecell";
325 reg = <0x0 0xe8a0f000 0x0 0x1000>;
326 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
329 gpio-ranges = <&pmx0 0 18 8>;
330 interrupt-controller;
331 #interrupt-cells = <2>;
332 clocks = <&crg_ctrl HI3670_PCLK_GPIO4>;
333 clock-names = "apb_pclk";
336 gpio5: gpio@e8a10000 {
337 compatible = "arm,pl061", "arm,primecell";
338 reg = <0x0 0xe8a10000 0x0 0x1000>;
339 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
342 gpio-ranges = <&pmx0 0 26 8>;
343 interrupt-controller;
344 #interrupt-cells = <2>;
345 clocks = <&crg_ctrl HI3670_PCLK_GPIO5>;
346 clock-names = "apb_pclk";
349 gpio6: gpio@e8a11000 {
350 compatible = "arm,pl061", "arm,primecell";
351 reg = <0x0 0xe8a11000 0x0 0x1000>;
352 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
355 gpio-ranges = <&pmx0 1 34 7>;
356 interrupt-controller;
357 #interrupt-cells = <2>;
358 clocks = <&crg_ctrl HI3670_PCLK_GPIO6>;
359 clock-names = "apb_pclk";
362 gpio7: gpio@e8a12000 {
363 compatible = "arm,pl061", "arm,primecell";
364 reg = <0x0 0xe8a12000 0x0 0x1000>;
365 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
368 gpio-ranges = <&pmx0 0 41 8>;
369 interrupt-controller;
370 #interrupt-cells = <2>;
371 clocks = <&crg_ctrl HI3670_PCLK_GPIO7>;
372 clock-names = "apb_pclk";
375 gpio8: gpio@e8a13000 {
376 compatible = "arm,pl061", "arm,primecell";
377 reg = <0x0 0xe8a13000 0x0 0x1000>;
378 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
381 gpio-ranges = <&pmx0 0 49 8>;
382 interrupt-controller;
383 #interrupt-cells = <2>;
384 clocks = <&crg_ctrl HI3670_PCLK_GPIO8>;
385 clock-names = "apb_pclk";
388 gpio9: gpio@e8a14000 {
389 compatible = "arm,pl061", "arm,primecell";
390 reg = <0x0 0xe8a14000 0x0 0x1000>;
391 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
394 gpio-ranges = <&pmx0 0 57 8>;
395 interrupt-controller;
396 #interrupt-cells = <2>;
397 clocks = <&crg_ctrl HI3670_PCLK_GPIO9>;
398 clock-names = "apb_pclk";
401 gpio10: gpio@e8a15000 {
402 compatible = "arm,pl061", "arm,primecell";
403 reg = <0x0 0xe8a15000 0x0 0x1000>;
404 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
407 gpio-ranges = <&pmx0 0 65 8>;
408 interrupt-controller;
409 #interrupt-cells = <2>;
410 clocks = <&crg_ctrl HI3670_PCLK_GPIO10>;
411 clock-names = "apb_pclk";
414 gpio11: gpio@e8a16000 {
415 compatible = "arm,pl061", "arm,primecell";
416 reg = <0x0 0xe8a16000 0x0 0x1000>;
417 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
420 gpio-ranges = <&pmx0 0 73 8>;
421 interrupt-controller;
422 #interrupt-cells = <2>;
423 clocks = <&crg_ctrl HI3670_PCLK_GPIO11>;
424 clock-names = "apb_pclk";
427 gpio12: gpio@e8a17000 {
428 compatible = "arm,pl061", "arm,primecell";
429 reg = <0x0 0xe8a17000 0x0 0x1000>;
430 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
433 gpio-ranges = <&pmx0 0 81 1>;
434 interrupt-controller;
435 #interrupt-cells = <2>;
436 clocks = <&crg_ctrl HI3670_PCLK_GPIO12>;
437 clock-names = "apb_pclk";
440 gpio13: gpio@e8a18000 {
441 compatible = "arm,pl061", "arm,primecell";
442 reg = <0x0 0xe8a18000 0x0 0x1000>;
443 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
446 interrupt-controller;
447 #interrupt-cells = <2>;
448 clocks = <&crg_ctrl HI3670_PCLK_GPIO13>;
449 clock-names = "apb_pclk";
452 gpio14: gpio@e8a19000 {
453 compatible = "arm,pl061", "arm,primecell";
454 reg = <0x0 0xe8a19000 0x0 0x1000>;
455 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
458 interrupt-controller;
459 #interrupt-cells = <2>;
460 clocks = <&crg_ctrl HI3670_PCLK_GPIO14>;
461 clock-names = "apb_pclk";
464 gpio15: gpio@e8a1a000 {
465 compatible = "arm,pl061", "arm,primecell";
466 reg = <0x0 0xe8a1a000 0x0 0x1000>;
467 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
470 interrupt-controller;
471 #interrupt-cells = <2>;
472 clocks = <&crg_ctrl HI3670_PCLK_GPIO15>;
473 clock-names = "apb_pclk";
476 gpio16: gpio@e8a1b000 {
477 compatible = "arm,pl061", "arm,primecell";
478 reg = <0x0 0xe8a1b000 0x0 0x1000>;
479 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
482 gpio-ranges = <&pmx5 0 0 8>;
483 interrupt-controller;
484 #interrupt-cells = <2>;
485 clocks = <&crg_ctrl HI3670_PCLK_GPIO16>;
486 clock-names = "apb_pclk";
489 gpio17: gpio@e8a1c000 {
490 compatible = "arm,pl061", "arm,primecell";
491 reg = <0x0 0xe8a1c000 0x0 0x1000>;
492 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
495 gpio-ranges = <&pmx5 0 8 2>;
496 interrupt-controller;
497 #interrupt-cells = <2>;
498 clocks = <&crg_ctrl HI3670_PCLK_GPIO17>;
499 clock-names = "apb_pclk";
502 gpio18: gpio@fff28000 {
503 compatible = "arm,pl061", "arm,primecell";
504 reg = <0x0 0xfff28000 0x0 0x1000>;
505 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
508 gpio-ranges = <&pmx1 4 42 4>;
509 interrupt-controller;
510 #interrupt-cells = <2>;
511 clocks = <&sctrl HI3670_PCLK_GPIO18>;
512 clock-names = "apb_pclk";
515 gpio19: gpio@fff29000 {
516 compatible = "arm,pl061", "arm,primecell";
517 reg = <0x0 0xfff29000 0x0 0x1000>;
518 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
521 gpio-ranges = <&pmx1 0 61 2>;
522 interrupt-controller;
523 #interrupt-cells = <2>;
524 clocks = <&sctrl HI3670_PCLK_GPIO19>;
525 clock-names = "apb_pclk";
528 gpio20: gpio@e8a1f000 {
529 compatible = "arm,pl061", "arm,primecell";
530 reg = <0x0 0xe8a1f000 0x0 0x1000>;
531 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
534 gpio-ranges = <&pmx7 0 0 8>;
535 interrupt-controller;
536 #interrupt-cells = <2>;
537 clocks = <&crg_ctrl HI3670_PCLK_GPIO20>;
538 clock-names = "apb_pclk";
541 gpio21: gpio@e8a20000 {
542 compatible = "arm,pl061", "arm,primecell";
543 reg = <0x0 0xe8a20000 0x0 0x1000>;
544 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
547 gpio-ranges = <&pmx7 0 8 4>;
548 interrupt-controller;
549 #interrupt-cells = <2>;
550 clocks = <&crg_ctrl HI3670_PCLK_GPIO21>;
551 clock-names = "apb_pclk";
554 gpio22: gpio@fff0b000 {
555 compatible = "arm,pl061", "arm,primecell";
556 reg = <0x0 0xfff0b000 0x0 0x1000>;
557 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
561 gpio-ranges = <&pmx1 2 0 6>;
562 interrupt-controller;
563 #interrupt-cells = <2>;
564 clocks = <&sctrl HI3670_PCLK_AO_GPIO0>;
565 clock-names = "apb_pclk";
568 gpio23: gpio@fff0c000 {
569 compatible = "arm,pl061", "arm,primecell";
570 reg = <0x0 0xfff0c000 0x0 0x1000>;
571 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
575 gpio-ranges = <&pmx1 0 6 8>;
576 interrupt-controller;
577 #interrupt-cells = <2>;
578 clocks = <&sctrl HI3670_PCLK_AO_GPIO1>;
579 clock-names = "apb_pclk";
582 gpio24: gpio@fff0d000 {
583 compatible = "arm,pl061", "arm,primecell";
584 reg = <0x0 0xfff0d000 0x0 0x1000>;
585 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
589 gpio-ranges = <&pmx1 0 14 8>;
590 interrupt-controller;
591 #interrupt-cells = <2>;
592 clocks = <&sctrl HI3670_PCLK_AO_GPIO2>;
593 clock-names = "apb_pclk";
596 gpio25: gpio@fff0e000 {
597 compatible = "arm,pl061", "arm,primecell";
598 reg = <0x0 0xfff0e000 0x0 0x1000>;
599 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
603 gpio-ranges = <&pmx1 0 22 8>;
604 interrupt-controller;
605 #interrupt-cells = <2>;
606 clocks = <&sctrl HI3670_PCLK_AO_GPIO3>;
607 clock-names = "apb_pclk";
610 gpio26: gpio@fff0f000 {
611 compatible = "arm,pl061", "arm,primecell";
612 reg = <0x0 0xfff0f000 0x0 0x1000>;
613 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
617 gpio-ranges = <&pmx1 0 30 1>;
618 interrupt-controller;
619 #interrupt-cells = <2>;
620 clocks = <&sctrl HI3670_PCLK_AO_GPIO4>;
621 clock-names = "apb_pclk";
624 gpio27: gpio@fff10000 {
625 compatible = "arm,pl061", "arm,primecell";
626 reg = <0x0 0xfff10000 0x0 0x1000>;
627 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
631 gpio-ranges = <&pmx1 4 31 4>;
632 interrupt-controller;
633 #interrupt-cells = <2>;
634 clocks = <&sctrl HI3670_PCLK_AO_GPIO5>;
635 clock-names = "apb_pclk";
638 gpio28: gpio@fff1d000 {
639 compatible = "arm,pl061", "arm,primecell";
640 reg = <0x0 0xfff1d000 0x0 0x1000>;
641 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
644 gpio-ranges = <&pmx1 1 35 7>;
645 interrupt-controller;
646 #interrupt-cells = <2>;
647 clocks = <&sctrl HI3670_PCLK_AO_GPIO6>;
648 clock-names = "apb_pclk";