arch/arm64/boot/dts/hisilicon/hi3670.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * dts file for Hisilicon Hi3670 SoC
   4  *
   5  * Copyright (C) 2016, Hisilicon Ltd.
   6  * Copyright (C) 2018, Linaro Ltd.
   7  */
   8
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/clock/hi3670-clock.h>
  11
  12 / {
  13         compatible = "hisilicon,hi3670";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         psci {
  19                 compatible = "arm,psci-0.2";
  20                 method = "smc";
  21         };
  22
  23         cpus {
  24                 #address-cells = <2>;
  25                 #size-cells = <0>;
  26
  27                 cpu-map {
  28                         cluster0 {
  29                                 core0 {
  30                                         cpu = <&cpu0>;
  31                                 };
  32                                 core1 {
  33                                         cpu = <&cpu1>;
  34                                 };
  35                                 core2 {
  36                                         cpu = <&cpu2>;
  37                                 };
  38                                 core3 {
  39                                         cpu = <&cpu3>;
  40                                 };
  41                         };
  42                         cluster1 {
  43                                 core0 {
  44                                         cpu = <&cpu4>;
  45                                 };
  46                                 core1 {
  47                                         cpu = <&cpu5>;
  48                                 };
  49                                 core2 {
  50                                         cpu = <&cpu6>;
  51                                 };
  52                                 core3 {
  53                                         cpu = <&cpu7>;
  54                                 };
  55                         };
  56                 };
  57
  58                 cpu0: cpu@0 {
  59                         compatible = "arm,cortex-a53";
  60                         device_type = "cpu";
  61                         reg = <0x0 0x0>;
  62                         enable-method = "psci";
  63                 };
  64
  65                 cpu1: cpu@1 {
  66                         compatible = "arm,cortex-a53";
  67                         device_type = "cpu";
  68                         reg = <0x0 0x1>;
  69                         enable-method = "psci";
  70                 };
  71
  72                 cpu2: cpu@2 {
  73                         compatible = "arm,cortex-a53";
  74                         device_type = "cpu";
  75                         reg = <0x0 0x2>;
  76                         enable-method = "psci";
  77                 };
  78
  79                 cpu3: cpu@3 {
  80                         compatible = "arm,cortex-a53";
  81                         device_type = "cpu";
  82                         reg = <0x0 0x3>;
  83                         enable-method = "psci";
  84                 };
  85
  86                 cpu4: cpu@100 {
  87                         compatible = "arm,cortex-a73";
  88                         device_type = "cpu";
  89                         reg = <0x0 0x100>;
  90                         enable-method = "psci";
  91                 };
  92
  93                 cpu5: cpu@101 {
  94                         compatible = "arm,cortex-a73";
  95                         device_type = "cpu";
  96                         reg = <0x0 0x101>;
  97                         enable-method = "psci";
  98                 };
  99
 100                 cpu6: cpu@102 {
 101                         compatible = "arm,cortex-a73";
 102                         device_type = "cpu";
 103                         reg = <0x0 0x102>;
 104                         enable-method = "psci";
 105                 };
 106
 107                 cpu7: cpu@103 {
 108                         compatible = "arm,cortex-a73";
 109                         device_type = "cpu";
 110                         reg = <0x0 0x103>;
 111                         enable-method = "psci";
 112                 };
 113         };
 114
 115         gic: interrupt-controller@e82b0000 {
 116                 compatible = "arm,gic-400";
 117                 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
 118                       <0x0 0xe82b2000 0 0x2000>, /* GICC */
 119                       <0x0 0xe82b4000 0 0x2000>, /* GICH */
 120                       <0x0 0xe82b6000 0 0x2000>; /* GICV */
 121                 #interrupt-cells = <3>;
 122                 #address-cells = <0>;
 123                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
 124                                          IRQ_TYPE_LEVEL_HIGH)>;
 125                 interrupt-controller;
 126         };
 127
 128         timer {
 129                 compatible = "arm,armv8-timer";
 130                 interrupt-parent = <&gic>;
 131                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
 132                                           IRQ_TYPE_LEVEL_LOW)>,
 133                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
 134                                           IRQ_TYPE_LEVEL_LOW)>,
 135                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
 136                                           IRQ_TYPE_LEVEL_LOW)>,
 137                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
 138                                           IRQ_TYPE_LEVEL_LOW)>;
 139                 clock-frequency = <1920000>;
 140         };
 141
 142         soc {
 143                 compatible = "simple-bus";
 144                 #address-cells = <2>;
 145                 #size-cells = <2>;
 146                 ranges;
 147
 148                 crg_ctrl: crg_ctrl@fff35000 {
 149                         compatible = "hisilicon,hi3670-crgctrl", "syscon";
 150                         reg = <0x0 0xfff35000 0x0 0x1000>;
 151                         #clock-cells = <1>;
 152                 };
 153
 154                 crg_rst: crg_rst_controller {
 155                         compatible = "hisilicon,hi3670-reset",
 156                                      "hisilicon,hi3660-reset";
 157                         #reset-cells = <2>;
 158                         hisi,rst-syscon = <&crg_ctrl>;
 159                 };
 160
 161                 pctrl: pctrl@e8a09000 {
 162                         compatible = "hisilicon,hi3670-pctrl", "syscon";
 163                         reg = <0x0 0xe8a09000 0x0 0x1000>;
 164                         #clock-cells = <1>;
 165                 };
 166
 167                 pmuctrl: crg_ctrl@fff34000 {
 168                         compatible = "hisilicon,hi3670-pmuctrl", "syscon";
 169                         reg = <0x0 0xfff34000 0x0 0x1000>;
 170                         #clock-cells = <1>;
 171                 };
 172
 173                 sctrl: sctrl@fff0a000 {
 174                         compatible = "hisilicon,hi3670-sctrl", "syscon";
 175                         reg = <0x0 0xfff0a000 0x0 0x1000>;
 176                         #clock-cells = <1>;
 177                 };
 178
 179                 iomcu: iomcu@ffd7e000 {
 180                         compatible = "hisilicon,hi3670-iomcu", "syscon";
 181                         reg = <0x0 0xffd7e000 0x0 0x1000>;
 182                         #clock-cells = <1>;
 183                 };
 184
 185                 media1_crg: media1_crgctrl@e87ff000 {
 186                         compatible = "hisilicon,hi3670-media1-crg", "syscon";
 187                         reg = <0x0 0xe87ff000 0x0 0x1000>;
 188                         #clock-cells = <1>;
 189                 };
 190
 191                 media2_crg: media2_crgctrl@e8900000 {
 192                         compatible = "hisilicon,hi3670-media2-crg","syscon";
 193                         reg = <0x0 0xe8900000 0x0 0x1000>;
 194                         #clock-cells = <1>;
 195                 };
 196
 197                 uart0: serial@fdf02000 {
 198                         compatible = "arm,pl011", "arm,primecell";
 199                         reg = <0x0 0xfdf02000 0x0 0x1000>;
 200                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 201                         clocks = <&crg_ctrl HI3670_CLK_GATE_UART0>,
 202                                  <&crg_ctrl HI3670_PCLK>;
 203                         clock-names = "uartclk", "apb_pclk";
 204                         pinctrl-names = "default";
 205                         pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
 206                         status = "disabled";
 207                 };
 208
 209                 uart1: serial@fdf00000 {
 210                         compatible = "arm,pl011", "arm,primecell";
 211                         reg = <0x0 0xfdf00000 0x0 0x1000>;
 212                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 213                         clocks = <&crg_ctrl HI3670_CLK_GATE_UART1>,
 214                                  <&crg_ctrl HI3670_PCLK>;
 215                         clock-names = "uartclk", "apb_pclk";
 216                         pinctrl-names = "default";
 217                         status = "disabled";
 218                 };
 219
 220                 uart2: serial@fdf03000 {
 221                         compatible = "arm,pl011", "arm,primecell";
 222                         reg = <0x0 0xfdf03000 0x0 0x1000>;
 223                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 224                         clocks = <&crg_ctrl HI3670_CLK_GATE_UART2>,
 225                                  <&crg_ctrl HI3670_PCLK>;
 226                         clock-names = "uartclk", "apb_pclk";
 227                         pinctrl-names = "default";
 228                         pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
 229                         status = "disabled";
 230                 };
 231
 232                 uart3: serial@ffd74000 {
 233                         compatible = "arm,pl011", "arm,primecell";
 234                         reg = <0x0 0xffd74000 0x0 0x1000>;
 235                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 236                         clocks = <&crg_ctrl HI3670_CLK_GATE_UART3>,
 237                                  <&crg_ctrl HI3670_PCLK>;
 238                         clock-names = "uartclk", "apb_pclk";
 239                         pinctrl-names = "default";
 240                         pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
 241                         status = "disabled";
 242                 };
 243
 244                 uart4: serial@fdf01000 {
 245                         compatible = "arm,pl011", "arm,primecell";
 246                         reg = <0x0 0xfdf01000 0x0 0x1000>;
 247                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 248                         clocks = <&crg_ctrl HI3670_CLK_GATE_UART4>,
 249                                  <&crg_ctrl HI3670_PCLK>;
 250                         clock-names = "uartclk", "apb_pclk";
 251                         pinctrl-names = "default";
 252                         pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
 253                         status = "disabled";
 254                 };
 255
 256                 uart5: serial@fdf05000 {
 257                         compatible = "arm,pl011", "arm,primecell";
 258                         reg = <0x0 0xfdf05000 0x0 0x1000>;
 259                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 260                         clocks = <&crg_ctrl HI3670_CLK_GATE_UART5>,
 261                                  <&crg_ctrl HI3670_PCLK>;
 262                         clock-names = "uartclk", "apb_pclk";
 263                         pinctrl-names = "default";
 264                         status = "disabled";
 265                 };
 266
 267                 uart6: serial@fff32000 {
 268                         compatible = "arm,pl011", "arm,primecell";
 269                         reg = <0x0 0xfff32000 0x0 0x1000>;
 270                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 271                         clocks = <&crg_ctrl HI3670_CLK_UART6>,
 272                                  <&crg_ctrl HI3670_PCLK>;
 273                         clock-names = "uartclk", "apb_pclk";
 274                         pinctrl-names = "default";
 275                         pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>;
 276                         status = "disabled";
 277                 };
 278
 279                 gpio0: gpio@e8a0b000 {
 280                         compatible = "arm,pl061", "arm,primecell";
 281                         reg = <0x0 0xe8a0b000 0x0 0x1000>;
 282                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 283                         gpio-controller;
 284                         #gpio-cells = <2>;
 285                         gpio-ranges = <&pmx0 1 0 1 &pmx0 3 1 5>;
 286                         interrupt-controller;
 287                         #interrupt-cells = <2>;
 288                         clocks = <&crg_ctrl HI3670_PCLK_GPIO0>;
 289                         clock-names = "apb_pclk";
 290                 };
 291
 292                 gpio1: gpio@e8a0c000 {
 293                         compatible = "arm,pl061", "arm,primecell";
 294                         reg = <0x0 0xe8a0c000 0x0 0x1000>;
 295                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 296                         gpio-controller;
 297                         #gpio-cells = <2>;
 298                         interrupt-controller;
 299                         #interrupt-cells = <2>;
 300                         clocks = <&crg_ctrl HI3670_PCLK_GPIO1>;
 301                         clock-names = "apb_pclk";
 302                 };
 303
 304                 gpio2: gpio@e8a0d000 {
 305                         compatible = "arm,pl061", "arm,primecell";
 306                         reg = <0x0 0xe8a0d000 0x0 0x1000>;
 307                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 308                         gpio-controller;
 309                         #gpio-cells = <2>;
 310                         gpio-ranges = <&pmx0 1 6 7>;
 311                         interrupt-controller;
 312                         #interrupt-cells = <2>;
 313                         clocks = <&crg_ctrl HI3670_PCLK_GPIO2>;
 314                         clock-names = "apb_pclk";
 315                 };
 316
 317                 gpio3: gpio@e8a0e000 {
 318                         compatible = "arm,pl061", "arm,primecell";
 319                         reg = <0x0 0xe8a0e000 0x0 0x1000>;
 320                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 321                         gpio-controller;
 322                         #gpio-cells = <2>;
 323                         gpio-ranges =  <&pmx0 0 13 4 &pmx0 7 17 1>;
 324                         interrupt-controller;
 325                         #interrupt-cells = <2>;
 326                         clocks = <&crg_ctrl HI3670_PCLK_GPIO3>;
 327                         clock-names = "apb_pclk";
 328                 };
 329
 330                 gpio4: gpio@e8a0f000 {
 331                         compatible = "arm,pl061", "arm,primecell";
 332                         reg = <0x0 0xe8a0f000 0x0 0x1000>;
 333                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 334                         gpio-controller;
 335                         #gpio-cells = <2>;
 336                         gpio-ranges = <&pmx0 0 18 8>;
 337                         interrupt-controller;
 338                         #interrupt-cells = <2>;
 339                         clocks = <&crg_ctrl HI3670_PCLK_GPIO4>;
 340                         clock-names = "apb_pclk";
 341                 };
 342
 343                 gpio5: gpio@e8a10000 {
 344                         compatible = "arm,pl061", "arm,primecell";
 345                         reg = <0x0 0xe8a10000 0x0 0x1000>;
 346                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 347                         gpio-controller;
 348                         #gpio-cells = <2>;
 349                         gpio-ranges = <&pmx0 0 26 8>;
 350                         interrupt-controller;
 351                         #interrupt-cells = <2>;
 352                         clocks = <&crg_ctrl HI3670_PCLK_GPIO5>;
 353                         clock-names = "apb_pclk";
 354                 };
 355
 356                 gpio6: gpio@e8a11000 {
 357                         compatible = "arm,pl061", "arm,primecell";
 358                         reg = <0x0 0xe8a11000 0x0 0x1000>;
 359                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 360                         gpio-controller;
 361                         #gpio-cells = <2>;
 362                         gpio-ranges = <&pmx0 1 34 7>;
 363                         interrupt-controller;
 364                         #interrupt-cells = <2>;
 365                         clocks = <&crg_ctrl HI3670_PCLK_GPIO6>;
 366                         clock-names = "apb_pclk";
 367                 };
 368
 369                 gpio7: gpio@e8a12000 {
 370                         compatible = "arm,pl061", "arm,primecell";
 371                         reg = <0x0 0xe8a12000 0x0 0x1000>;
 372                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 373                         gpio-controller;
 374                         #gpio-cells = <2>;
 375                         gpio-ranges = <&pmx0 0 41 8>;
 376                         interrupt-controller;
 377                         #interrupt-cells = <2>;
 378                         clocks = <&crg_ctrl HI3670_PCLK_GPIO7>;
 379                         clock-names = "apb_pclk";
 380                 };
 381
 382                 gpio8: gpio@e8a13000 {
 383                         compatible = "arm,pl061", "arm,primecell";
 384                         reg = <0x0 0xe8a13000 0x0 0x1000>;
 385                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 386                         gpio-controller;
 387                         #gpio-cells = <2>;
 388                         gpio-ranges = <&pmx0 0 49 8>;
 389                         interrupt-controller;
 390                         #interrupt-cells = <2>;
 391                         clocks = <&crg_ctrl HI3670_PCLK_GPIO8>;
 392                         clock-names = "apb_pclk";
 393                 };
 394
 395                 gpio9: gpio@e8a14000 {
 396                         compatible = "arm,pl061", "arm,primecell";
 397                         reg = <0x0 0xe8a14000 0x0 0x1000>;
 398                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 399                         gpio-controller;
 400                         #gpio-cells = <2>;
 401                         gpio-ranges = <&pmx0 0 57 8>;
 402                         interrupt-controller;
 403                         #interrupt-cells = <2>;
 404                         clocks = <&crg_ctrl HI3670_PCLK_GPIO9>;
 405                         clock-names = "apb_pclk";
 406                 };
 407
 408                 gpio10: gpio@e8a15000 {
 409                         compatible = "arm,pl061", "arm,primecell";
 410                         reg = <0x0 0xe8a15000 0x0 0x1000>;
 411                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 412                         gpio-controller;
 413                         #gpio-cells = <2>;
 414                         gpio-ranges = <&pmx0 0 65 8>;
 415                         interrupt-controller;
 416                         #interrupt-cells = <2>;
 417                         clocks = <&crg_ctrl HI3670_PCLK_GPIO10>;
 418                         clock-names = "apb_pclk";
 419                 };
 420
 421                 gpio11: gpio@e8a16000 {
 422                         compatible = "arm,pl061", "arm,primecell";
 423                         reg = <0x0 0xe8a16000 0x0 0x1000>;
 424                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 425                         gpio-controller;
 426                         #gpio-cells = <2>;
 427                         gpio-ranges = <&pmx0 0 73 8>;
 428                         interrupt-controller;
 429                         #interrupt-cells = <2>;
 430                         clocks = <&crg_ctrl HI3670_PCLK_GPIO11>;
 431                         clock-names = "apb_pclk";
 432                 };
 433
 434                 gpio12: gpio@e8a17000 {
 435                         compatible = "arm,pl061", "arm,primecell";
 436                         reg = <0x0 0xe8a17000 0x0 0x1000>;
 437                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 438                         gpio-controller;
 439                         #gpio-cells = <2>;
 440                         gpio-ranges = <&pmx0 0 81 1>;
 441                         interrupt-controller;
 442                         #interrupt-cells = <2>;
 443                         clocks = <&crg_ctrl HI3670_PCLK_GPIO12>;
 444                         clock-names = "apb_pclk";
 445                 };
 446
 447                 gpio13: gpio@e8a18000 {
 448                         compatible = "arm,pl061", "arm,primecell";
 449                         reg = <0x0 0xe8a18000 0x0 0x1000>;
 450                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 451                         gpio-controller;
 452                         #gpio-cells = <2>;
 453                         interrupt-controller;
 454                         #interrupt-cells = <2>;
 455                         clocks = <&crg_ctrl HI3670_PCLK_GPIO13>;
 456                         clock-names = "apb_pclk";
 457                 };
 458
 459                 gpio14: gpio@e8a19000 {
 460                         compatible = "arm,pl061", "arm,primecell";
 461                         reg = <0x0 0xe8a19000 0x0 0x1000>;
 462                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 463                         gpio-controller;
 464                         #gpio-cells = <2>;
 465                         interrupt-controller;
 466                         #interrupt-cells = <2>;
 467                         clocks = <&crg_ctrl HI3670_PCLK_GPIO14>;
 468                         clock-names = "apb_pclk";
 469                 };
 470
 471                 gpio15: gpio@e8a1a000 {
 472                         compatible = "arm,pl061", "arm,primecell";
 473                         reg = <0x0 0xe8a1a000 0x0 0x1000>;
 474                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 475                         gpio-controller;
 476                         #gpio-cells = <2>;
 477                         interrupt-controller;
 478                         #interrupt-cells = <2>;
 479                         clocks = <&crg_ctrl HI3670_PCLK_GPIO15>;
 480                         clock-names = "apb_pclk";
 481                 };
 482
 483                 gpio16: gpio@e8a1b000 {
 484                         compatible = "arm,pl061", "arm,primecell";
 485                         reg = <0x0 0xe8a1b000 0x0 0x1000>;
 486                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 487                         gpio-controller;
 488                         #gpio-cells = <2>;
 489                         gpio-ranges = <&pmx5 0 0 8>;
 490                         interrupt-controller;
 491                         #interrupt-cells = <2>;
 492                         clocks = <&crg_ctrl HI3670_PCLK_GPIO16>;
 493                         clock-names = "apb_pclk";
 494                 };
 495
 496                 gpio17: gpio@e8a1c000 {
 497                         compatible = "arm,pl061", "arm,primecell";
 498                         reg = <0x0 0xe8a1c000 0x0 0x1000>;
 499                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 500                         gpio-controller;
 501                         #gpio-cells = <2>;
 502                         gpio-ranges = <&pmx5 0 8 2>;
 503                         interrupt-controller;
 504                         #interrupt-cells = <2>;
 505                         clocks = <&crg_ctrl HI3670_PCLK_GPIO17>;
 506                         clock-names = "apb_pclk";
 507                 };
 508
 509                 gpio18: gpio@fff28000 {
 510                         compatible = "arm,pl061", "arm,primecell";
 511                         reg = <0x0 0xfff28000 0x0 0x1000>;
 512                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 513                         gpio-controller;
 514                         #gpio-cells = <2>;
 515                         gpio-ranges = <&pmx1 4 42 4>;
 516                         interrupt-controller;
 517                         #interrupt-cells = <2>;
 518                         clocks = <&sctrl HI3670_PCLK_GPIO18>;
 519                         clock-names = "apb_pclk";
 520                 };
 521
 522                 gpio19: gpio@fff29000 {
 523                         compatible = "arm,pl061", "arm,primecell";
 524                         reg = <0x0 0xfff29000 0x0 0x1000>;
 525                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 526                         gpio-controller;
 527                         #gpio-cells = <2>;
 528                         gpio-ranges = <&pmx1 0 61 2>;
 529                         interrupt-controller;
 530                         #interrupt-cells = <2>;
 531                         clocks = <&sctrl HI3670_PCLK_GPIO19>;
 532                         clock-names = "apb_pclk";
 533                 };
 534
 535                 gpio20: gpio@e8a1f000 {
 536                         compatible = "arm,pl061", "arm,primecell";
 537                         reg = <0x0 0xe8a1f000 0x0 0x1000>;
 538                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 539                         gpio-controller;
 540                         #gpio-cells = <2>;
 541                         gpio-ranges = <&pmx7 0 0 8>;
 542                         interrupt-controller;
 543                         #interrupt-cells = <2>;
 544                         clocks = <&crg_ctrl HI3670_PCLK_GPIO20>;
 545                         clock-names = "apb_pclk";
 546                 };
 547
 548                 gpio21: gpio@e8a20000 {
 549                         compatible = "arm,pl061", "arm,primecell";
 550                         reg = <0x0 0xe8a20000 0x0 0x1000>;
 551                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 552                         gpio-controller;
 553                         #gpio-cells = <2>;
 554                         gpio-ranges = <&pmx7 0 8 4>;
 555                         interrupt-controller;
 556                         #interrupt-cells = <2>;
 557                         clocks = <&crg_ctrl HI3670_PCLK_GPIO21>;
 558                         clock-names = "apb_pclk";
 559                 };
 560
 561                 gpio22: gpio@fff0b000 {
 562                         compatible = "arm,pl061", "arm,primecell";
 563                         reg = <0x0 0xfff0b000 0x0 0x1000>;
 564                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 565                         gpio-controller;
 566                         #gpio-cells = <2>;
 567                         /* GPIO176 */
 568                         gpio-ranges = <&pmx1 2 0 6>;
 569                         interrupt-controller;
 570                         #interrupt-cells = <2>;
 571                         clocks = <&sctrl HI3670_PCLK_AO_GPIO0>;
 572                         clock-names = "apb_pclk";
 573                 };
 574
 575                 gpio23: gpio@fff0c000 {
 576                         compatible = "arm,pl061", "arm,primecell";
 577                         reg = <0x0 0xfff0c000 0x0 0x1000>;
 578                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 579                         gpio-controller;
 580                         #gpio-cells = <2>;
 581                         /* GPIO184 */
 582                         gpio-ranges = <&pmx1 0 6 8>;
 583                         interrupt-controller;
 584                         #interrupt-cells = <2>;
 585                         clocks = <&sctrl HI3670_PCLK_AO_GPIO1>;
 586                         clock-names = "apb_pclk";
 587                 };
 588
 589                 gpio24: gpio@fff0d000 {
 590                         compatible = "arm,pl061", "arm,primecell";
 591                         reg = <0x0 0xfff0d000 0x0 0x1000>;
 592                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 593                         gpio-controller;
 594                         #gpio-cells = <2>;
 595                         /* GPIO192 */
 596                         gpio-ranges = <&pmx1 0 14 8>;
 597                         interrupt-controller;
 598                         #interrupt-cells = <2>;
 599                         clocks = <&sctrl HI3670_PCLK_AO_GPIO2>;
 600                         clock-names = "apb_pclk";
 601                 };
 602
 603                 gpio25: gpio@fff0e000 {
 604                         compatible = "arm,pl061", "arm,primecell";
 605                         reg = <0x0 0xfff0e000 0x0 0x1000>;
 606                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 607                         gpio-controller;
 608                         #gpio-cells = <2>;
 609                         /* GPIO200 */
 610                         gpio-ranges = <&pmx1 0 22 8>;
 611                         interrupt-controller;
 612                         #interrupt-cells = <2>;
 613                         clocks = <&sctrl HI3670_PCLK_AO_GPIO3>;
 614                         clock-names = "apb_pclk";
 615                 };
 616
 617                 gpio26: gpio@fff0f000 {
 618                         compatible = "arm,pl061", "arm,primecell";
 619                         reg = <0x0 0xfff0f000 0x0 0x1000>;
 620                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 621                         gpio-controller;
 622                         #gpio-cells = <2>;
 623                         /* GPIO208 */
 624                         gpio-ranges = <&pmx1 0 30 1>;
 625                         interrupt-controller;
 626                         #interrupt-cells = <2>;
 627                         clocks = <&sctrl HI3670_PCLK_AO_GPIO4>;
 628                         clock-names = "apb_pclk";
 629                 };
 630
 631                 gpio27: gpio@fff10000 {
 632                         compatible = "arm,pl061", "arm,primecell";
 633                         reg = <0x0 0xfff10000 0x0 0x1000>;
 634                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 635                         gpio-controller;
 636                         #gpio-cells = <2>;
 637                         /* GPIO216 */
 638                         gpio-ranges = <&pmx1 4 31 4>;
 639                         interrupt-controller;
 640                         #interrupt-cells = <2>;
 641                         clocks = <&sctrl HI3670_PCLK_AO_GPIO5>;
 642                         clock-names = "apb_pclk";
 643                 };
 644
 645                 gpio28: gpio@fff1d000 {
 646                         compatible = "arm,pl061", "arm,primecell";
 647                         reg = <0x0 0xfff1d000 0x0 0x1000>;
 648                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 649                         gpio-controller;
 650                         #gpio-cells = <2>;
 651                         gpio-ranges = <&pmx1 1 35 7>;
 652                         interrupt-controller;
 653                         #interrupt-cells = <2>;
 654                         clocks = <&sctrl HI3670_PCLK_AO_GPIO6>;
 655                         clock-names = "apb_pclk";
 656                 };
 657
 658                 /* UFS */
 659                 ufs: ufs@ff3c0000 {
 660                         compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
 661                         /* 0: HCI standard */
 662                         /* 1: UFS SYS CTRL */
 663                         reg = <0x0 0xff3c0000 0x0 0x1000>,
 664                                 <0x0 0xff3e0000 0x0 0x1000>;
 665                         interrupt-parent = <&gic>;
 666                         interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
 667                         clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,
 668                                 <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;
 669                         clock-names = "ref_clk", "phy_clk";
 670                         freq-table-hz = <0 0>, <0 0>;
 671                         /* offset: 0x84; bit: 12 */
 672                         resets = <&crg_rst 0x84 12>;
 673                         reset-names = "rst";
 674                 };
 675
 676                 /* SD */
 677                 dwmmc1: dwmmc1@ff37f000 {
 678                         compatible = "hisilicon,hi3670-dw-mshc",
 679                                      "hisilicon,hi3660-dw-mshc";
 680                         reg = <0x0 0xff37f000 0x0 0x1000>;
 681                         #address-cells = <1>;
 682                         #size-cells = <0>;
 683                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 684                         clocks = <&crg_ctrl HI3670_CLK_GATE_SD>,
 685                                 <&crg_ctrl HI3670_HCLK_GATE_SD>;
 686                         clock-names = "ciu", "biu";
 687                         clock-frequency = <3200000>;
 688                         resets = <&crg_rst 0x94 18>;
 689                         reset-names = "reset";
 690                         hisilicon,peripheral-syscon = <&sctrl>;
 691                         card-detect-delay = <200>;
 692                         status = "disabled";
 693                 };
 694
 695                 /* SDIO */
 696                 dwmmc2: dwmmc2@fc183000 {
 697                         compatible = "hisilicon,hi3670-dw-mshc",
 698                                      "hisilicon,hi3660-dw-mshc";
 699                         reg = <0x0 0xfc183000 0x0 0x1000>;
 700                         #address-cells = <1>;
 701                         #size-cells = <0>;
 702                         interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 703                         clocks = <&crg_ctrl HI3670_CLK_GATE_SDIO>,
 704                                 <&crg_ctrl HI3670_HCLK_GATE_SDIO>;
 705                         clock-names = "ciu", "biu";
 706                         clock-frequency = <3200000>;
 707                         resets = <&crg_rst 0x94 20>;
 708                         reset-names = "reset";
 709                         card-detect-delay = <200>;
 710                         status = "disabled";
 711                 };
 712         };
 713 };