arch/arm64/boot/dts/hisilicon/hi3660.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * dts file for Hisilicon Hi3660 SoC
   4  *
   5  * Copyright (C) 2016, HiSilicon Ltd.
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/clock/hi3660-clock.h>
  10 #include <dt-bindings/thermal/thermal.h>
  11
  12 / {
  13         compatible = "hisilicon,hi3660";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         psci {
  19                 compatible = "arm,psci-0.2";
  20                 method = "smc";
  21         };
  22
  23         cpus {
  24                 #address-cells = <2>;
  25                 #size-cells = <0>;
  26
  27                 cpu-map {
  28                         cluster0 {
  29                                 core0 {
  30                                         cpu = <&cpu0>;
  31                                 };
  32                                 core1 {
  33                                         cpu = <&cpu1>;
  34                                 };
  35                                 core2 {
  36                                         cpu = <&cpu2>;
  37                                 };
  38                                 core3 {
  39                                         cpu = <&cpu3>;
  40                                 };
  41                         };
  42                         cluster1 {
  43                                 core0 {
  44                                         cpu = <&cpu4>;
  45                                 };
  46                                 core1 {
  47                                         cpu = <&cpu5>;
  48                                 };
  49                                 core2 {
  50                                         cpu = <&cpu6>;
  51                                 };
  52                                 core3 {
  53                                         cpu = <&cpu7>;
  54                                 };
  55                         };
  56                 };
  57
  58                 cpu0: cpu@0 {
  59                         compatible = "arm,cortex-a53";
  60                         device_type = "cpu";
  61                         reg = <0x0 0x0>;
  62                         enable-method = "psci";
  63                         next-level-cache = <&A53_L2>;
  64                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
  65                         capacity-dmips-mhz = <592>;
  66                         clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
  67                         operating-points-v2 = <&cluster0_opp>;
  68                         #cooling-cells = <2>;
  69                         dynamic-power-coefficient = <110>;
  70                 };
  71
  72                 cpu1: cpu@1 {
  73                         compatible = "arm,cortex-a53";
  74                         device_type = "cpu";
  75                         reg = <0x0 0x1>;
  76                         enable-method = "psci";
  77                         next-level-cache = <&A53_L2>;
  78                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
  79                         capacity-dmips-mhz = <592>;
  80                         clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
  81                         operating-points-v2 = <&cluster0_opp>;
  82                         #cooling-cells = <2>;
  83                 };
  84
  85                 cpu2: cpu@2 {
  86                         compatible = "arm,cortex-a53";
  87                         device_type = "cpu";
  88                         reg = <0x0 0x2>;
  89                         enable-method = "psci";
  90                         next-level-cache = <&A53_L2>;
  91                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
  92                         capacity-dmips-mhz = <592>;
  93                         clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
  94                         operating-points-v2 = <&cluster0_opp>;
  95                         #cooling-cells = <2>;
  96                 };
  97
  98                 cpu3: cpu@3 {
  99                         compatible = "arm,cortex-a53";
 100                         device_type = "cpu";
 101                         reg = <0x0 0x3>;
 102                         enable-method = "psci";
 103                         next-level-cache = <&A53_L2>;
 104                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 105                         capacity-dmips-mhz = <592>;
 106                         clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
 107                         operating-points-v2 = <&cluster0_opp>;
 108                         #cooling-cells = <2>;
 109                 };
 110
 111                 cpu4: cpu@100 {
 112                         compatible = "arm,cortex-a73";
 113                         device_type = "cpu";
 114                         reg = <0x0 0x100>;
 115                         enable-method = "psci";
 116                         next-level-cache = <&A73_L2>;
 117                         cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
 118                         capacity-dmips-mhz = <1024>;
 119                         clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
 120                         operating-points-v2 = <&cluster1_opp>;
 121                         #cooling-cells = <2>;
 122                         dynamic-power-coefficient = <550>;
 123                 };
 124
 125                 cpu5: cpu@101 {
 126                         compatible = "arm,cortex-a73";
 127                         device_type = "cpu";
 128                         reg = <0x0 0x101>;
 129                         enable-method = "psci";
 130                         next-level-cache = <&A73_L2>;
 131                         cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
 132                         capacity-dmips-mhz = <1024>;
 133                         clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
 134                         operating-points-v2 = <&cluster1_opp>;
 135                         #cooling-cells = <2>;
 136                 };
 137
 138                 cpu6: cpu@102 {
 139                         compatible = "arm,cortex-a73";
 140                         device_type = "cpu";
 141                         reg = <0x0 0x102>;
 142                         enable-method = "psci";
 143                         next-level-cache = <&A73_L2>;
 144                         cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
 145                         capacity-dmips-mhz = <1024>;
 146                         clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
 147                         operating-points-v2 = <&cluster1_opp>;
 148                         #cooling-cells = <2>;
 149                 };
 150
 151                 cpu7: cpu@103 {
 152                         compatible = "arm,cortex-a73";
 153                         device_type = "cpu";
 154                         reg = <0x0 0x103>;
 155                         enable-method = "psci";
 156                         next-level-cache = <&A73_L2>;
 157                         cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
 158                         capacity-dmips-mhz = <1024>;
 159                         clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
 160                         operating-points-v2 = <&cluster1_opp>;
 161                         #cooling-cells = <2>;
 162                 };
 163
 164                 idle-states {
 165                         entry-method = "psci";
 166
 167                         CPU_SLEEP_0: cpu-sleep-0 {
 168                                 compatible = "arm,idle-state";
 169                                 local-timer-stop;
 170                                 arm,psci-suspend-param = <0x0010000>;
 171                                 entry-latency-us = <400>;
 172                                 exit-latency-us = <650>;
 173                                 min-residency-us = <1500>;
 174                         };
 175                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 176                                 compatible = "arm,idle-state";
 177                                 local-timer-stop;
 178                                 arm,psci-suspend-param = <0x1010000>;
 179                                 entry-latency-us = <500>;
 180                                 exit-latency-us = <1600>;
 181                                 min-residency-us = <3500>;
 182                         };
 183
 184
 185                         CPU_SLEEP_1: cpu-sleep-1 {
 186                                 compatible = "arm,idle-state";
 187                                 local-timer-stop;
 188                                 arm,psci-suspend-param = <0x0010000>;
 189                                 entry-latency-us = <400>;
 190                                 exit-latency-us = <550>;
 191                                 min-residency-us = <1500>;
 192                         };
 193
 194                         CLUSTER_SLEEP_1: cluster-sleep-1 {
 195                                 compatible = "arm,idle-state";
 196                                 local-timer-stop;
 197                                 arm,psci-suspend-param = <0x1010000>;
 198                                 entry-latency-us = <800>;
 199                                 exit-latency-us = <2900>;
 200                                 min-residency-us = <3500>;
 201                         };
 202                 };
 203
 204                 A53_L2: l2-cache0 {
 205                         compatible = "cache";
 206                         cache-level = <2>;
 207                         cache-unified;
 208                 };
 209
 210                 A73_L2: l2-cache1 {
 211                         compatible = "cache";
 212                         cache-level = <2>;
 213                         cache-unified;
 214                 };
 215         };
 216
 217         cluster0_opp: opp-table-0 {
 218                 compatible = "operating-points-v2";
 219                 opp-shared;
 220
 221                 opp00 {
 222                         opp-hz = /bits/ 64 <533000000>;
 223                         opp-microvolt = <700000>;
 224                         clock-latency-ns = <300000>;
 225                 };
 226
 227                 opp01 {
 228                         opp-hz = /bits/ 64 <999000000>;
 229                         opp-microvolt = <800000>;
 230                         clock-latency-ns = <300000>;
 231                 };
 232
 233                 opp02 {
 234                         opp-hz = /bits/ 64 <1402000000>;
 235                         opp-microvolt = <900000>;
 236                         clock-latency-ns = <300000>;
 237                 };
 238
 239                 opp03 {
 240                         opp-hz = /bits/ 64 <1709000000>;
 241                         opp-microvolt = <1000000>;
 242                         clock-latency-ns = <300000>;
 243                 };
 244
 245                 opp04 {
 246                         opp-hz = /bits/ 64 <1844000000>;
 247                         opp-microvolt = <1100000>;
 248                         clock-latency-ns = <300000>;
 249                 };
 250         };
 251
 252         cluster1_opp: opp-table-1 {
 253                 compatible = "operating-points-v2";
 254                 opp-shared;
 255
 256                 opp10 {
 257                         opp-hz = /bits/ 64 <903000000>;
 258                         opp-microvolt = <700000>;
 259                         clock-latency-ns = <300000>;
 260                 };
 261
 262                 opp11 {
 263                         opp-hz = /bits/ 64 <1421000000>;
 264                         opp-microvolt = <800000>;
 265                         clock-latency-ns = <300000>;
 266                 };
 267
 268                 opp12 {
 269                         opp-hz = /bits/ 64 <1805000000>;
 270                         opp-microvolt = <900000>;
 271                         clock-latency-ns = <300000>;
 272                 };
 273
 274                 opp13 {
 275                         opp-hz = /bits/ 64 <2112000000>;
 276                         opp-microvolt = <1000000>;
 277                         clock-latency-ns = <300000>;
 278                 };
 279
 280                 opp14 {
 281                         opp-hz = /bits/ 64 <2362000000>;
 282                         opp-microvolt = <1100000>;
 283                         clock-latency-ns = <300000>;
 284                 };
 285         };
 286
 287         gic: interrupt-controller@e82b0000 {
 288                 compatible = "arm,gic-400";
 289                 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
 290                       <0x0 0xe82b2000 0 0x2000>, /* GICC */
 291                       <0x0 0xe82b4000 0 0x2000>, /* GICH */
 292                       <0x0 0xe82b6000 0 0x2000>; /* GICV */
 293                 #address-cells = <0>;
 294                 #interrupt-cells = <3>;
 295                 interrupt-controller;
 296                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
 297                                          IRQ_TYPE_LEVEL_HIGH)>;
 298         };
 299
 300         a53-pmu {
 301                 compatible = "arm,cortex-a53-pmu";
 302                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
 303                              <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
 304                              <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 305                              <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 306                 interrupt-affinity = <&cpu0>,
 307                                      <&cpu1>,
 308                                      <&cpu2>,
 309                                      <&cpu3>;
 310         };
 311
 312         a73-pmu {
 313                 compatible = "arm,cortex-a73-pmu";
 314                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 315                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 316                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 317                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 318                 interrupt-affinity = <&cpu4>,
 319                                      <&cpu5>,
 320                                      <&cpu6>,
 321                                      <&cpu7>;
 322         };
 323
 324         timer {
 325                 compatible = "arm,armv8-timer";
 326                 interrupt-parent = <&gic>;
 327                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
 328                                           IRQ_TYPE_LEVEL_LOW)>,
 329                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
 330                                           IRQ_TYPE_LEVEL_LOW)>,
 331                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
 332                                           IRQ_TYPE_LEVEL_LOW)>,
 333                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
 334                                           IRQ_TYPE_LEVEL_LOW)>;
 335         };
 336
 337         soc {
 338                 compatible = "simple-bus";
 339                 #address-cells = <2>;
 340                 #size-cells = <2>;
 341                 ranges;
 342
 343                 crg_ctrl: crg_ctrl@fff35000 {
 344                         compatible = "hisilicon,hi3660-crgctrl", "syscon";
 345                         reg = <0x0 0xfff35000 0x0 0x1000>;
 346                         #clock-cells = <1>;
 347                 };
 348
 349                 crg_rst: crg_rst_controller {
 350                         compatible = "hisilicon,hi3660-reset";
 351                         #reset-cells = <2>;
 352                         hisi,rst-syscon = <&crg_ctrl>;
 353                 };
 354
 355
 356                 pctrl: pctrl@e8a09000 {
 357                         compatible = "hisilicon,hi3660-pctrl", "syscon";
 358                         reg = <0x0 0xe8a09000 0x0 0x2000>;
 359                         #clock-cells = <1>;
 360                 };
 361
 362                 pmuctrl: crg_ctrl@fff34000 {
 363                         compatible = "hisilicon,hi3660-pmuctrl", "syscon";
 364                         reg = <0x0 0xfff34000 0x0 0x1000>;
 365                         #clock-cells = <1>;
 366                 };
 367
 368                 sctrl: sctrl@fff0a000 {
 369                         compatible = "hisilicon,hi3660-sctrl", "syscon";
 370                         reg = <0x0 0xfff0a000 0x0 0x1000>;
 371                         #clock-cells = <1>;
 372                 };
 373
 374                 iomcu: iomcu@ffd7e000 {
 375                         compatible = "hisilicon,hi3660-iomcu", "syscon";
 376                         reg = <0x0 0xffd7e000 0x0 0x1000>;
 377                         #clock-cells = <1>;
 378
 379                 };
 380
 381                 iomcu_rst: reset {
 382                         compatible = "hisilicon,hi3660-reset";
 383                         hisi,rst-syscon = <&iomcu>;
 384                         #reset-cells = <2>;
 385                 };
 386
 387                 mailbox: mailbox@e896b000 {
 388                         compatible = "hisilicon,hi3660-mbox";
 389                         reg = <0x0 0xe896b000 0x0 0x1000>;
 390                         interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
 391                                      <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 392                         #mbox-cells = <3>;
 393                 };
 394
 395                 stub_clock: stub_clock@e896b500 {
 396                         compatible = "hisilicon,hi3660-stub-clk";
 397                         reg = <0x0 0xe896b500 0x0 0x0100>;
 398                         #clock-cells = <1>;
 399                         mboxes = <&mailbox 13 3 0>;
 400                 };
 401
 402                 dual_timer0: timer@fff14000 {
 403                         compatible = "arm,sp804", "arm,primecell";
 404                         reg = <0x0 0xfff14000 0x0 0x1000>;
 405                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
 406                                      <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 407                         clocks = <&crg_ctrl HI3660_OSC32K>,
 408                                  <&crg_ctrl HI3660_OSC32K>,
 409                                  <&crg_ctrl HI3660_OSC32K>;
 410                         clock-names = "timer1", "timer2", "apb_pclk";
 411                 };
 412
 413                 i2c0: i2c@ffd71000 {
 414                         compatible = "snps,designware-i2c";
 415                         reg = <0x0 0xffd71000 0x0 0x1000>;
 416                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 417                         #address-cells = <1>;
 418                         #size-cells = <0>;
 419                         clock-frequency = <400000>;
 420                         clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
 421                         resets = <&iomcu_rst 0x20 3>;
 422                         pinctrl-names = "default";
 423                         pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
 424                         status = "disabled";
 425                 };
 426
 427                 i2c1: i2c@ffd72000 {
 428                         compatible = "snps,designware-i2c";
 429                         reg = <0x0 0xffd72000 0x0 0x1000>;
 430                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 431                         #address-cells = <1>;
 432                         #size-cells = <0>;
 433                         clock-frequency = <400000>;
 434                         clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>;
 435                         resets = <&iomcu_rst 0x20 4>;
 436                         pinctrl-names = "default";
 437                         pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
 438                         status = "disabled";
 439                 };
 440
 441                 i2c3: i2c@fdf0c000 {
 442                         compatible = "snps,designware-i2c";
 443                         reg = <0x0 0xfdf0c000 0x0 0x1000>;
 444                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 445                         #address-cells = <1>;
 446                         #size-cells = <0>;
 447                         clock-frequency = <400000>;
 448                         clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>;
 449                         resets = <&crg_rst 0x78 7>;
 450                         pinctrl-names = "default";
 451                         pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>;
 452                         status = "disabled";
 453                 };
 454
 455                 i2c7: i2c@fdf0b000 {
 456                         compatible = "snps,designware-i2c";
 457                         reg = <0x0 0xfdf0b000 0x0 0x1000>;
 458                         interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
 459                         #address-cells = <1>;
 460                         #size-cells = <0>;
 461                         clock-frequency = <400000>;
 462                         clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>;
 463                         resets = <&crg_rst 0x60 14>;
 464                         pinctrl-names = "default";
 465                         pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>;
 466                         status = "disabled";
 467                 };
 468
 469                 uart0: serial@fdf02000 {
 470                         compatible = "arm,pl011", "arm,primecell";
 471                         reg = <0x0 0xfdf02000 0x0 0x1000>;
 472                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 473                         clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
 474                                  <&crg_ctrl HI3660_PCLK>;
 475                         clock-names = "uartclk", "apb_pclk";
 476                         pinctrl-names = "default";
 477                         pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
 478                         status = "disabled";
 479                 };
 480
 481                 uart1: serial@fdf00000 {
 482                         compatible = "arm,pl011", "arm,primecell";
 483                         reg = <0x0 0xfdf00000 0x0 0x1000>;
 484                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 485                         dma-names = "rx", "tx";
 486                         dmas = <&dma0 2 &dma0 3>;
 487                         clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>,
 488                                  <&crg_ctrl HI3660_CLK_GATE_UART1>;
 489                         clock-names = "uartclk", "apb_pclk";
 490                         pinctrl-names = "default";
 491                         pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
 492                         status = "disabled";
 493                 };
 494
 495                 uart2: serial@fdf03000 {
 496                         compatible = "arm,pl011", "arm,primecell";
 497                         reg = <0x0 0xfdf03000 0x0 0x1000>;
 498                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 499                         dma-names = "rx", "tx";
 500                         dmas = <&dma0 4 &dma0 5>;
 501                         clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>,
 502                                  <&crg_ctrl HI3660_PCLK>;
 503                         clock-names = "uartclk", "apb_pclk";
 504                         pinctrl-names = "default";
 505                         pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
 506                         status = "disabled";
 507                 };
 508
 509                 uart3: serial@ffd74000 {
 510                         compatible = "arm,pl011", "arm,primecell";
 511                         reg = <0x0 0xffd74000 0x0 0x1000>;
 512                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 513                         clocks = <&crg_ctrl HI3660_FACTOR_UART3>,
 514                                  <&crg_ctrl HI3660_PCLK>;
 515                         clock-names = "uartclk", "apb_pclk";
 516                         pinctrl-names = "default";
 517                         pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
 518                         status = "disabled";
 519                 };
 520
 521                 uart4: serial@fdf01000 {
 522                         compatible = "arm,pl011", "arm,primecell";
 523                         reg = <0x0 0xfdf01000 0x0 0x1000>;
 524                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 525                         dma-names = "rx", "tx";
 526                         dmas = <&dma0 6 &dma0 7>;
 527                         clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>,
 528                                  <&crg_ctrl HI3660_CLK_GATE_UART4>;
 529                         clock-names = "uartclk", "apb_pclk";
 530                         pinctrl-names = "default";
 531                         pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
 532                         status = "disabled";
 533                 };
 534
 535                 uart5: serial@fdf05000 {
 536                         compatible = "arm,pl011", "arm,primecell";
 537                         reg = <0x0 0xfdf05000 0x0 0x1000>;
 538                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 539                         dma-names = "rx", "tx";
 540                         dmas = <&dma0 8 &dma0 9>;
 541                         clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>,
 542                                  <&crg_ctrl HI3660_CLK_GATE_UART5>;
 543                         clock-names = "uartclk", "apb_pclk";
 544                         pinctrl-names = "default";
 545                         pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>;
 546                         status = "disabled";
 547                 };
 548
 549                 uart6: serial@fff32000 {
 550                         compatible = "arm,pl011", "arm,primecell";
 551                         reg = <0x0 0xfff32000 0x0 0x1000>;
 552                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 553                         clocks = <&crg_ctrl HI3660_CLK_UART6>,
 554                                  <&crg_ctrl HI3660_PCLK>;
 555                         clock-names = "uartclk", "apb_pclk";
 556                         pinctrl-names = "default";
 557                         pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>;
 558                         status = "disabled";
 559                 };
 560
 561                 dma0: dma@fdf30000 {
 562                         compatible = "hisilicon,k3-dma-1.0";
 563                         reg = <0x0 0xfdf30000 0x0 0x1000>;
 564                         #dma-cells = <1>;
 565                         dma-channels = <16>;
 566                         dma-requests = <32>;
 567                         dma-channel-mask = <0xfffe>;
 568                         interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 569                         clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>;
 570                         dma-no-cci;
 571                         dma-type = "hi3660_dma";
 572                 };
 573
 574                 asp_dmac: dma-controller@e804b000 {
 575                         compatible = "hisilicon,hisi-pcm-asp-dma-1.0";
 576                         reg = <0x0 0xe804b000 0x0 0x1000>;
 577                         #dma-cells = <1>;
 578                         dma-channels = <16>;
 579                         dma-requests = <32>;
 580                         interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
 581                         interrupt-names = "asp_dma_irq";
 582                 };
 583
 584                 rtc0: rtc@fff04000 {
 585                         compatible = "arm,pl031", "arm,primecell";
 586                         reg = <0x0 0Xfff04000 0x0 0x1000>;
 587                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 588                         clocks = <&crg_ctrl HI3660_PCLK>;
 589                         clock-names = "apb_pclk";
 590                 };
 591
 592                 gpio0: gpio@e8a0b000 {
 593                         compatible = "arm,pl061", "arm,primecell";
 594                         reg = <0 0xe8a0b000 0 0x1000>;
 595                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 596                         gpio-controller;
 597                         #gpio-cells = <2>;
 598                         gpio-ranges = <&pmx0 1 0 7>;
 599                         interrupt-controller;
 600                         #interrupt-cells = <2>;
 601                         clocks = <&crg_ctrl HI3660_PCLK_GPIO0>;
 602                         clock-names = "apb_pclk";
 603                 };
 604
 605                 gpio1: gpio@e8a0c000 {
 606                         compatible = "arm,pl061", "arm,primecell";
 607                         reg = <0 0xe8a0c000 0 0x1000>;
 608                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 609                         gpio-controller;
 610                         #gpio-cells = <2>;
 611                         gpio-ranges = <&pmx0 1 7 7>;
 612                         interrupt-controller;
 613                         #interrupt-cells = <2>;
 614                         clocks = <&crg_ctrl HI3660_PCLK_GPIO1>;
 615                         clock-names = "apb_pclk";
 616                 };
 617
 618                 gpio2: gpio@e8a0d000 {
 619                         compatible = "arm,pl061", "arm,primecell";
 620                         reg = <0 0xe8a0d000 0 0x1000>;
 621                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 622                         gpio-controller;
 623                         #gpio-cells = <2>;
 624                         gpio-ranges = <&pmx0 0 14 8>;
 625                         interrupt-controller;
 626                         #interrupt-cells = <2>;
 627                         clocks = <&crg_ctrl HI3660_PCLK_GPIO2>;
 628                         clock-names = "apb_pclk";
 629                 };
 630
 631                 gpio3: gpio@e8a0e000 {
 632                         compatible = "arm,pl061", "arm,primecell";
 633                         reg = <0 0xe8a0e000 0 0x1000>;
 634                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 635                         gpio-controller;
 636                         #gpio-cells = <2>;
 637                         gpio-ranges = <&pmx0 0 22 8>;
 638                         interrupt-controller;
 639                         #interrupt-cells = <2>;
 640                         clocks = <&crg_ctrl HI3660_PCLK_GPIO3>;
 641                         clock-names = "apb_pclk";
 642                 };
 643
 644                 gpio4: gpio@e8a0f000 {
 645                         compatible = "arm,pl061", "arm,primecell";
 646                         reg = <0 0xe8a0f000 0 0x1000>;
 647                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 648                         gpio-controller;
 649                         #gpio-cells = <2>;
 650                         gpio-ranges = <&pmx0 0 30 8>;
 651                         interrupt-controller;
 652                         #interrupt-cells = <2>;
 653                         clocks = <&crg_ctrl HI3660_PCLK_GPIO4>;
 654                         clock-names = "apb_pclk";
 655                 };
 656
 657                 gpio5: gpio@e8a10000 {
 658                         compatible = "arm,pl061", "arm,primecell";
 659                         reg = <0 0xe8a10000 0 0x1000>;
 660                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 661                         gpio-controller;
 662                         #gpio-cells = <2>;
 663                         gpio-ranges = <&pmx0 0 38 8>;
 664                         interrupt-controller;
 665                         #interrupt-cells = <2>;
 666                         clocks = <&crg_ctrl HI3660_PCLK_GPIO5>;
 667                         clock-names = "apb_pclk";
 668                 };
 669
 670                 gpio6: gpio@e8a11000 {
 671                         compatible = "arm,pl061", "arm,primecell";
 672                         reg = <0 0xe8a11000 0 0x1000>;
 673                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 674                         gpio-controller;
 675                         #gpio-cells = <2>;
 676                         gpio-ranges = <&pmx0 0 46 8>;
 677                         interrupt-controller;
 678                         #interrupt-cells = <2>;
 679                         clocks = <&crg_ctrl HI3660_PCLK_GPIO6>;
 680                         clock-names = "apb_pclk";
 681                 };
 682
 683                 gpio7: gpio@e8a12000 {
 684                         compatible = "arm,pl061", "arm,primecell";
 685                         reg = <0 0xe8a12000 0 0x1000>;
 686                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 687                         gpio-controller;
 688                         #gpio-cells = <2>;
 689                         gpio-ranges = <&pmx0 0 54 8>;
 690                         interrupt-controller;
 691                         #interrupt-cells = <2>;
 692                         clocks = <&crg_ctrl HI3660_PCLK_GPIO7>;
 693                         clock-names = "apb_pclk";
 694                 };
 695
 696                 gpio8: gpio@e8a13000 {
 697                         compatible = "arm,pl061", "arm,primecell";
 698                         reg = <0 0xe8a13000 0 0x1000>;
 699                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 700                         gpio-controller;
 701                         #gpio-cells = <2>;
 702                         gpio-ranges = <&pmx0 0 62 8>;
 703                         interrupt-controller;
 704                         #interrupt-cells = <2>;
 705                         clocks = <&crg_ctrl HI3660_PCLK_GPIO8>;
 706                         clock-names = "apb_pclk";
 707                 };
 708
 709                 gpio9: gpio@e8a14000 {
 710                         compatible = "arm,pl061", "arm,primecell";
 711                         reg = <0 0xe8a14000 0 0x1000>;
 712                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 713                         gpio-controller;
 714                         #gpio-cells = <2>;
 715                         gpio-ranges = <&pmx0 0 70 8>;
 716                         interrupt-controller;
 717                         #interrupt-cells = <2>;
 718                         clocks = <&crg_ctrl HI3660_PCLK_GPIO9>;
 719                         clock-names = "apb_pclk";
 720                 };
 721
 722                 gpio10: gpio@e8a15000 {
 723                         compatible = "arm,pl061", "arm,primecell";
 724                         reg = <0 0xe8a15000 0 0x1000>;
 725                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 726                         gpio-controller;
 727                         #gpio-cells = <2>;
 728                         gpio-ranges = <&pmx0 0 78 8>;
 729                         interrupt-controller;
 730                         #interrupt-cells = <2>;
 731                         clocks = <&crg_ctrl HI3660_PCLK_GPIO10>;
 732                         clock-names = "apb_pclk";
 733                 };
 734
 735                 gpio11: gpio@e8a16000 {
 736                         compatible = "arm,pl061", "arm,primecell";
 737                         reg = <0 0xe8a16000 0 0x1000>;
 738                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 739                         gpio-controller;
 740                         #gpio-cells = <2>;
 741                         gpio-ranges = <&pmx0 0 86 8>;
 742                         interrupt-controller;
 743                         #interrupt-cells = <2>;
 744                         clocks = <&crg_ctrl HI3660_PCLK_GPIO11>;
 745                         clock-names = "apb_pclk";
 746                 };
 747
 748                 gpio12: gpio@e8a17000 {
 749                         compatible = "arm,pl061", "arm,primecell";
 750                         reg = <0 0xe8a17000 0 0x1000>;
 751                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 752                         gpio-controller;
 753                         #gpio-cells = <2>;
 754                         gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>;
 755                         interrupt-controller;
 756                         #interrupt-cells = <2>;
 757                         clocks = <&crg_ctrl HI3660_PCLK_GPIO12>;
 758                         clock-names = "apb_pclk";
 759                 };
 760
 761                 gpio13: gpio@e8a18000 {
 762                         compatible = "arm,pl061", "arm,primecell";
 763                         reg = <0 0xe8a18000 0 0x1000>;
 764                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 765                         gpio-controller;
 766                         #gpio-cells = <2>;
 767                         gpio-ranges = <&pmx0 0 102 8>;
 768                         interrupt-controller;
 769                         #interrupt-cells = <2>;
 770                         clocks = <&crg_ctrl HI3660_PCLK_GPIO13>;
 771                         clock-names = "apb_pclk";
 772                 };
 773
 774                 gpio14: gpio@e8a19000 {
 775                         compatible = "arm,pl061", "arm,primecell";
 776                         reg = <0 0xe8a19000 0 0x1000>;
 777                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 778                         gpio-controller;
 779                         #gpio-cells = <2>;
 780                         gpio-ranges = <&pmx0 0 110 8>;
 781                         interrupt-controller;
 782                         #interrupt-cells = <2>;
 783                         clocks = <&crg_ctrl HI3660_PCLK_GPIO14>;
 784                         clock-names = "apb_pclk";
 785                 };
 786
 787                 gpio15: gpio@e8a1a000 {
 788                         compatible = "arm,pl061", "arm,primecell";
 789                         reg = <0 0xe8a1a000 0 0x1000>;
 790                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 791                         gpio-controller;
 792                         #gpio-cells = <2>;
 793                         gpio-ranges = <&pmx0 0 118 6>;
 794                         interrupt-controller;
 795                         #interrupt-cells = <2>;
 796                         clocks = <&crg_ctrl HI3660_PCLK_GPIO15>;
 797                         clock-names = "apb_pclk";
 798                 };
 799
 800                 gpio16: gpio@e8a1b000 {
 801                         compatible = "arm,pl061", "arm,primecell";
 802                         reg = <0 0xe8a1b000 0 0x1000>;
 803                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 804                         gpio-controller;
 805                         #gpio-cells = <2>;
 806                         interrupt-controller;
 807                         #interrupt-cells = <2>;
 808                         clocks = <&crg_ctrl HI3660_PCLK_GPIO16>;
 809                         clock-names = "apb_pclk";
 810                 };
 811
 812                 gpio17: gpio@e8a1c000 {
 813                         compatible = "arm,pl061", "arm,primecell";
 814                         reg = <0 0xe8a1c000 0 0x1000>;
 815                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 816                         gpio-controller;
 817                         #gpio-cells = <2>;
 818                         interrupt-controller;
 819                         #interrupt-cells = <2>;
 820                         clocks = <&crg_ctrl HI3660_PCLK_GPIO17>;
 821                         clock-names = "apb_pclk";
 822                 };
 823
 824                 gpio18: gpio@ff3b4000 {
 825                         compatible = "arm,pl061", "arm,primecell";
 826                         reg = <0 0xff3b4000 0 0x1000>;
 827                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 828                         gpio-controller;
 829                         #gpio-cells = <2>;
 830                         gpio-ranges = <&pmx2 0 0 8>;
 831                         interrupt-controller;
 832                         #interrupt-cells = <2>;
 833                         clocks = <&crg_ctrl HI3660_PCLK_GPIO18>;
 834                         clock-names = "apb_pclk";
 835                 };
 836
 837                 gpio19: gpio@ff3b5000 {
 838                         compatible = "arm,pl061", "arm,primecell";
 839                         reg = <0 0xff3b5000 0 0x1000>;
 840                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 841                         gpio-controller;
 842                         #gpio-cells = <2>;
 843                         gpio-ranges = <&pmx2 0 8 4>;
 844                         interrupt-controller;
 845                         #interrupt-cells = <2>;
 846                         clocks = <&crg_ctrl HI3660_PCLK_GPIO19>;
 847                         clock-names = "apb_pclk";
 848                 };
 849
 850                 gpio20: gpio@e8a1f000 {
 851                         compatible = "arm,pl061", "arm,primecell";
 852                         reg = <0 0xe8a1f000 0 0x1000>;
 853                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 854                         gpio-controller;
 855                         #gpio-cells = <2>;
 856                         gpio-ranges = <&pmx1 0 0 6>;
 857                         interrupt-controller;
 858                         #interrupt-cells = <2>;
 859                         clocks = <&crg_ctrl HI3660_PCLK_GPIO20>;
 860                         clock-names = "apb_pclk";
 861                 };
 862
 863                 gpio21: gpio@e8a20000 {
 864                         compatible = "arm,pl061", "arm,primecell";
 865                         reg = <0 0xe8a20000 0 0x1000>;
 866                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 867                         gpio-controller;
 868                         #gpio-cells = <2>;
 869                         interrupt-controller;
 870                         #interrupt-cells = <2>;
 871                         gpio-ranges = <&pmx3 0 0 6>;
 872                         clocks = <&crg_ctrl HI3660_PCLK_GPIO21>;
 873                         clock-names = "apb_pclk";
 874                 };
 875
 876                 gpio22: gpio@fff0b000 {
 877                         compatible = "arm,pl061", "arm,primecell";
 878                         reg = <0 0xfff0b000 0 0x1000>;
 879                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 880                         gpio-controller;
 881                         #gpio-cells = <2>;
 882                         /* GPIO176 */
 883                         gpio-ranges = <&pmx4 2 0 6>;
 884                         interrupt-controller;
 885                         #interrupt-cells = <2>;
 886                         clocks = <&sctrl HI3660_PCLK_AO_GPIO0>;
 887                         clock-names = "apb_pclk";
 888                 };
 889
 890                 gpio23: gpio@fff0c000 {
 891                         compatible = "arm,pl061", "arm,primecell";
 892                         reg = <0 0xfff0c000 0 0x1000>;
 893                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 894                         gpio-controller;
 895                         #gpio-cells = <2>;
 896                         /* GPIO184 */
 897                         gpio-ranges = <&pmx4 0 6 7>;
 898                         interrupt-controller;
 899                         #interrupt-cells = <2>;
 900                         clocks = <&sctrl HI3660_PCLK_AO_GPIO1>;
 901                         clock-names = "apb_pclk";
 902                 };
 903
 904                 gpio24: gpio@fff0d000 {
 905                         compatible = "arm,pl061", "arm,primecell";
 906                         reg = <0 0xfff0d000 0 0x1000>;
 907                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 908                         gpio-controller;
 909                         #gpio-cells = <2>;
 910                         /* GPIO192 */
 911                         gpio-ranges = <&pmx4 0 13 8>;
 912                         interrupt-controller;
 913                         #interrupt-cells = <2>;
 914                         clocks = <&sctrl HI3660_PCLK_AO_GPIO2>;
 915                         clock-names = "apb_pclk";
 916                 };
 917
 918                 gpio25: gpio@fff0e000 {
 919                         compatible = "arm,pl061", "arm,primecell";
 920                         reg = <0 0xfff0e000 0 0x1000>;
 921                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 922                         gpio-controller;
 923                         #gpio-cells = <2>;
 924                         /* GPIO200 */
 925                         gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>;
 926                         interrupt-controller;
 927                         #interrupt-cells = <2>;
 928                         clocks = <&sctrl HI3660_PCLK_AO_GPIO3>;
 929                         clock-names = "apb_pclk";
 930                 };
 931
 932                 gpio26: gpio@fff0f000 {
 933                         compatible = "arm,pl061", "arm,primecell";
 934                         reg = <0 0xfff0f000 0 0x1000>;
 935                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 936                         gpio-controller;
 937                         #gpio-cells = <2>;
 938                         /* GPIO208 */
 939                         gpio-ranges = <&pmx4 0 28 8>;
 940                         interrupt-controller;
 941                         #interrupt-cells = <2>;
 942                         clocks = <&sctrl HI3660_PCLK_AO_GPIO4>;
 943                         clock-names = "apb_pclk";
 944                 };
 945
 946                 gpio27: gpio@fff10000 {
 947                         compatible = "arm,pl061", "arm,primecell";
 948                         reg = <0 0xfff10000 0 0x1000>;
 949                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 950                         gpio-controller;
 951                         #gpio-cells = <2>;
 952                         /* GPIO216 */
 953                         gpio-ranges = <&pmx4 0 36 6>;
 954                         interrupt-controller;
 955                         #interrupt-cells = <2>;
 956                         clocks = <&sctrl HI3660_PCLK_AO_GPIO5>;
 957                         clock-names = "apb_pclk";
 958                 };
 959
 960                 gpio28: gpio@fff1d000 {
 961                         compatible = "arm,pl061", "arm,primecell";
 962                         reg = <0 0xfff1d000 0 0x1000>;
 963                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 964                         gpio-controller;
 965                         #gpio-cells = <2>;
 966                         interrupt-controller;
 967                         #interrupt-cells = <2>;
 968                         clocks = <&sctrl HI3660_PCLK_AO_GPIO6>;
 969                         clock-names = "apb_pclk";
 970                 };
 971
 972                 spi2: spi@ffd68000 {
 973                         compatible = "arm,pl022", "arm,primecell";
 974                         reg = <0x0 0xffd68000 0x0 0x1000>;
 975                         #address-cells = <1>;
 976                         #size-cells = <0>;
 977                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 978                         clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>, <&crg_ctrl HI3660_CLK_GATE_SPI2>;
 979                         clock-names = "sspclk", "apb_pclk";
 980                         pinctrl-names = "default";
 981                         pinctrl-0 = <&spi2_pmx_func &spi2_cfg_func>;
 982                         num-cs = <1>;
 983                         cs-gpios = <&gpio27 2 0>;
 984                         status = "disabled";
 985                 };
 986
 987                 spi3: spi@ff3b3000 {
 988                         compatible = "arm,pl022", "arm,primecell";
 989                         reg = <0x0 0xff3b3000 0x0 0x1000>;
 990                         #address-cells = <1>;
 991                         #size-cells = <0>;
 992                         interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
 993                         clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>, <&crg_ctrl HI3660_CLK_GATE_SPI3>;
 994                         clock-names = "sspclk", "apb_pclk";
 995                         pinctrl-names = "default";
 996                         pinctrl-0 = <&spi3_pmx_func &spi3_cfg_func>;
 997                         num-cs = <1>;
 998                         cs-gpios = <&gpio18 5 0>;
 999                         status = "disabled";
1000                 };
1001
1002                 pcie@f4000000 {
1003                         compatible = "hisilicon,kirin960-pcie";
1004                         reg = <0x0 0xf4000000 0x0 0x1000>,
1005                               <0x0 0xff3fe000 0x0 0x1000>,
1006                               <0x0 0xf3f20000 0x0 0x40000>,
1007                               <0x0 0xf5000000 0x0 0x2000>;
1008                         reg-names = "dbi", "apb", "phy", "config";
1009                         bus-range = <0x0 0xff>;
1010                         #address-cells = <3>;
1011                         #size-cells = <2>;
1012                         device_type = "pci";
1013                         ranges = <0x02000000 0x0 0x00000000
1014                                   0x0 0xf6000000
1015                                   0x0 0x02000000>;
1016                         num-lanes = <1>;
1017                         #interrupt-cells = <1>;
1018                         interrupts = <0 283 4>;
1019                         interrupt-names = "msi";
1020                         interrupt-map-mask = <0xf800 0 0 7>;
1021                         interrupt-map = <0x0 0 0 1
1022                                          &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1023                                         <0x0 0 0 2
1024                                          &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1025                                         <0x0 0 0 3
1026                                          &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1027                                         <0x0 0 0 4
1028                                          &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
1029                         clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
1030                                  <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
1031                                  <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
1032                                  <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
1033                                  <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
1034                         clock-names = "pcie_phy_ref", "pcie_aux",
1035                                       "pcie_apb_phy", "pcie_apb_sys",
1036                                       "pcie_aclk";
1037                         reset-gpios = <&gpio11 1 0 >;
1038                 };
1039
1040                 /* UFS */
1041                 ufs: ufs@ff3b0000 {
1042                         compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1";
1043                         /* 0: HCI standard */
1044                         /* 1: UFS SYS CTRL */
1045                         reg = <0x0 0xff3b0000 0x0 0x1000>,
1046                                 <0x0 0xff3b1000 0x0 0x1000>;
1047                         interrupt-parent = <&gic>;
1048                         interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
1049                         clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
1050                                 <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
1051                         clock-names = "ref_clk", "phy_clk";
1052                         freq-table-hz = <0 0>,
1053                                         <0 0>;
1054                         /* offset: 0x84; bit: 12 */
1055                         resets = <&crg_rst 0x84 12>;
1056                         reset-names = "rst";
1057                 };
1058
1059                 /* SD */
1060                 dwmmc1: dwmmc1@ff37f000 {
1061                         compatible = "hisilicon,hi3660-dw-mshc";
1062                         reg = <0x0 0xff37f000 0x0 0x1000>;
1063                         #address-cells = <1>;
1064                         #size-cells = <0>;
1065                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
1066                         clocks = <&crg_ctrl HI3660_CLK_GATE_SD>,
1067                                 <&crg_ctrl HI3660_HCLK_GATE_SD>;
1068                         clock-names = "ciu", "biu";
1069                         clock-frequency = <3200000>;
1070                         resets = <&crg_rst 0x94 18>;
1071                         reset-names = "reset";
1072                         hisilicon,peripheral-syscon = <&sctrl>;
1073                         card-detect-delay = <200>;
1074                         status = "disabled";
1075                 };
1076
1077                 /* SDIO */
1078                 dwmmc2: dwmmc2@ff3ff000 {
1079                         compatible = "hisilicon,hi3660-dw-mshc";
1080                         reg = <0x0 0xff3ff000 0x0 0x1000>;
1081                         #address-cells = <0x1>;
1082                         #size-cells = <0x0>;
1083                         interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1084                         clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>,
1085                                  <&crg_ctrl HI3660_HCLK_GATE_SDIO0>;
1086                         clock-names = "ciu", "biu";
1087                         resets = <&crg_rst 0x94 20>;
1088                         reset-names = "reset";
1089                         card-detect-delay = <200>;
1090                         status = "disabled";
1091                 };
1092
1093                 watchdog0: watchdog@e8a06000 {
1094                         compatible = "arm,sp805", "arm,primecell";
1095                         reg = <0x0 0xe8a06000 0x0 0x1000>;
1096                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1097                         clocks = <&crg_ctrl HI3660_OSC32K>,
1098                                  <&crg_ctrl HI3660_OSC32K>;
1099                         clock-names = "wdog_clk", "apb_pclk";
1100                 };
1101
1102                 watchdog1: watchdog@e8a07000 {
1103                         compatible = "arm,sp805", "arm,primecell";
1104                         reg = <0x0 0xe8a07000 0x0 0x1000>;
1105                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1106                         clocks = <&crg_ctrl HI3660_OSC32K>,
1107                                  <&crg_ctrl HI3660_OSC32K>;
1108                         clock-names = "wdog_clk", "apb_pclk";
1109                 };
1110
1111                 tsensor: tsensor@fff30000 {
1112                         compatible = "hisilicon,hi3660-tsensor";
1113                         reg = <0x0 0xfff30000 0x0 0x1000>;
1114                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
1115                         #thermal-sensor-cells = <1>;
1116                 };
1117
1118                 thermal-zones {
1119
1120                         cls0: cls0-thermal {
1121                                 polling-delay = <1000>;
1122                                 polling-delay-passive = <100>;
1123                                 sustainable-power = <4500>;
1124
1125                                 /* sensor ID */
1126                                 thermal-sensors = <&tsensor 1>;
1127
1128                                 trips {
1129                                         threshold: trip-point0 {
1130                                                 temperature = <65000>;
1131                                                 hysteresis = <1000>;
1132                                                 type = "passive";
1133                                         };
1134
1135                                         target: trip-point1 {
1136                                                 temperature = <75000>;
1137                                                 hysteresis = <1000>;
1138                                                 type = "passive";
1139                                         };
1140                                 };
1141
1142                                 cooling-maps {
1143                                         map0 {
1144                                                 trip = <&target>;
1145                                                 contribution = <1024>;
1146                                                 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1147                                                                  <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1148                                                                  <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1149                                                                  <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1150                                         };
1151                                         map1 {
1152                                                 trip = <&target>;
1153                                                 contribution = <512>;
1154                                                 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1155                                                                  <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1156                                                                  <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1157                                                                  <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1158                                         };
1159                                 };
1160                         };
1161                 };
1162
1163                 usb3_otg_bc: usb3_otg_bc@ff200000 {
1164                         compatible = "hisilicon,hi3660-usb3-otg-bc", "syscon", "simple-mfd";
1165                         reg = <0x0 0xff200000 0x0 0x1000>;
1166
1167                         usb_phy: usb-phy {
1168                                 compatible = "hisilicon,hi3660-usb-phy";
1169                                 #phy-cells = <0>;
1170                                 hisilicon,pericrg-syscon = <&crg_ctrl>;
1171                                 hisilicon,pctrl-syscon = <&pctrl>;
1172                                 hisilicon,eye-diagram-param = <0x22466e4>;
1173                         };
1174                 };
1175
1176                 dwc3: usb@ff100000 {
1177                         compatible = "snps,dwc3";
1178                         reg = <0x0 0xff100000 0x0 0x100000>;
1179
1180                         clocks = <&crg_ctrl HI3660_CLK_ABB_USB>,
1181                                  <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>;
1182                         clock-names = "ref", "bus_early";
1183
1184                         assigned-clocks = <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>;
1185                         assigned-clock-rates = <229000000>;
1186
1187                         resets = <&crg_rst 0x90 8>,
1188                                  <&crg_rst 0x90 7>,
1189                                  <&crg_rst 0x90 6>,
1190                                  <&crg_rst 0x90 5>;
1191
1192                         interrupts = <0 159 4>, <0 161 4>;
1193                         phys = <&usb_phy>;
1194                         phy-names = "usb3-phy";
1195                 };
1196         };
1197 };
1198
1199 #include "hi3660-coresight.dtsi"