arch/arm64/boot/dts/hisilicon/hi3660.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * dts file for Hisilicon Hi3660 SoC
   4  *
   5  * Copyright (C) 2016, Hisilicon Ltd.
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/clock/hi3660-clock.h>
  10
  11 / {
  12         compatible = "hisilicon,hi3660";
  13         interrupt-parent = <&gic>;
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         psci {
  18                 compatible = "arm,psci-0.2";
  19                 method = "smc";
  20         };
  21
  22         cpus {
  23                 #address-cells = <2>;
  24                 #size-cells = <0>;
  25
  26                 cpu-map {
  27                         cluster0 {
  28                                 core0 {
  29                                         cpu = <&cpu0>;
  30                                 };
  31                                 core1 {
  32                                         cpu = <&cpu1>;
  33                                 };
  34                                 core2 {
  35                                         cpu = <&cpu2>;
  36                                 };
  37                                 core3 {
  38                                         cpu = <&cpu3>;
  39                                 };
  40                         };
  41                         cluster1 {
  42                                 core0 {
  43                                         cpu = <&cpu4>;
  44                                 };
  45                                 core1 {
  46                                         cpu = <&cpu5>;
  47                                 };
  48                                 core2 {
  49                                         cpu = <&cpu6>;
  50                                 };
  51                                 core3 {
  52                                         cpu = <&cpu7>;
  53                                 };
  54                         };
  55                 };
  56
  57                 cpu0: cpu@0 {
  58                         compatible = "arm,cortex-a53", "arm,armv8";
  59                         device_type = "cpu";
  60                         reg = <0x0 0x0>;
  61                         enable-method = "psci";
  62                         next-level-cache = <&A53_L2>;
  63                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
  64                         capacity-dmips-mhz = <592>;
  65                 };
  66
  67                 cpu1: cpu@1 {
  68                         compatible = "arm,cortex-a53", "arm,armv8";
  69                         device_type = "cpu";
  70                         reg = <0x0 0x1>;
  71                         enable-method = "psci";
  72                         next-level-cache = <&A53_L2>;
  73                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
  74                         capacity-dmips-mhz = <592>;
  75                 };
  76
  77                 cpu2: cpu@2 {
  78                         compatible = "arm,cortex-a53", "arm,armv8";
  79                         device_type = "cpu";
  80                         reg = <0x0 0x2>;
  81                         enable-method = "psci";
  82                         next-level-cache = <&A53_L2>;
  83                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
  84                         capacity-dmips-mhz = <592>;
  85                 };
  86
  87                 cpu3: cpu@3 {
  88                         compatible = "arm,cortex-a53", "arm,armv8";
  89                         device_type = "cpu";
  90                         reg = <0x0 0x3>;
  91                         enable-method = "psci";
  92                         next-level-cache = <&A53_L2>;
  93                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
  94                         capacity-dmips-mhz = <592>;
  95                 };
  96
  97                 cpu4: cpu@100 {
  98                         compatible = "arm,cortex-a73", "arm,armv8";
  99                         device_type = "cpu";
 100                         reg = <0x0 0x100>;
 101                         enable-method = "psci";
 102                         next-level-cache = <&A73_L2>;
 103                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>;
 104                         capacity-dmips-mhz = <1024>;
 105                 };
 106
 107                 cpu5: cpu@101 {
 108                         compatible = "arm,cortex-a73", "arm,armv8";
 109                         device_type = "cpu";
 110                         reg = <0x0 0x101>;
 111                         enable-method = "psci";
 112                         next-level-cache = <&A73_L2>;
 113                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>;
 114                         capacity-dmips-mhz = <1024>;
 115                 };
 116
 117                 cpu6: cpu@102 {
 118                         compatible = "arm,cortex-a73", "arm,armv8";
 119                         device_type = "cpu";
 120                         reg = <0x0 0x102>;
 121                         enable-method = "psci";
 122                         next-level-cache = <&A73_L2>;
 123                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>;
 124                         capacity-dmips-mhz = <1024>;
 125                 };
 126
 127                 cpu7: cpu@103 {
 128                         compatible = "arm,cortex-a73", "arm,armv8";
 129                         device_type = "cpu";
 130                         reg = <0x0 0x103>;
 131                         enable-method = "psci";
 132                         next-level-cache = <&A73_L2>;
 133                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>;
 134                         capacity-dmips-mhz = <1024>;
 135                 };
 136
 137                 idle-states {
 138                         entry-method = "psci";
 139
 140                         CPU_SLEEP: cpu-sleep {
 141                                 compatible = "arm,idle-state";
 142                                 local-timer-stop;
 143                                 arm,psci-suspend-param = <0x0010000>;
 144                                 entry-latency-us = <40>;
 145                                 exit-latency-us = <70>;
 146                                 min-residency-us = <3000>;
 147                         };
 148
 149                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 150                                 compatible = "arm,idle-state";
 151                                 local-timer-stop;
 152                                 arm,psci-suspend-param = <0x1010000>;
 153                                 entry-latency-us = <500>;
 154                                 exit-latency-us = <5000>;
 155                                 min-residency-us = <20000>;
 156                         };
 157
 158                         CLUSTER_SLEEP_1: cluster-sleep-1 {
 159                                 compatible = "arm,idle-state";
 160                                 local-timer-stop;
 161                                 arm,psci-suspend-param = <0x1010000>;
 162                                 entry-latency-us = <1000>;
 163                                 exit-latency-us = <5000>;
 164                                 min-residency-us = <20000>;
 165                         };
 166                 };
 167
 168                 A53_L2: l2-cache0 {
 169                         compatible = "cache";
 170                 };
 171
 172                 A73_L2: l2-cache1 {
 173                         compatible = "cache";
 174                 };
 175         };
 176
 177         gic: interrupt-controller@e82b0000 {
 178                 compatible = "arm,gic-400";
 179                 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
 180                       <0x0 0xe82b2000 0 0x2000>, /* GICC */
 181                       <0x0 0xe82b4000 0 0x2000>, /* GICH */
 182                       <0x0 0xe82b6000 0 0x2000>; /* GICV */
 183                 #address-cells = <0>;
 184                 #interrupt-cells = <3>;
 185                 interrupt-controller;
 186                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
 187                                          IRQ_TYPE_LEVEL_HIGH)>;
 188         };
 189
 190         a53-pmu {
 191                 compatible = "arm,cortex-a53-pmu";
 192                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
 194                              <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 195                              <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 196                 interrupt-affinity = <&cpu0>,
 197                                      <&cpu1>,
 198                                      <&cpu2>,
 199                                      <&cpu3>;
 200         };
 201
 202         a73-pmu {
 203                 compatible = "arm,cortex-a73-pmu";
 204                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 205                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 206                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 207                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 208                 interrupt-affinity = <&cpu4>,
 209                                      <&cpu5>,
 210                                      <&cpu6>,
 211                                      <&cpu7>;
 212         };
 213
 214         timer {
 215                 compatible = "arm,armv8-timer";
 216                 interrupt-parent = <&gic>;
 217                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
 218                                           IRQ_TYPE_LEVEL_LOW)>,
 219                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
 220                                           IRQ_TYPE_LEVEL_LOW)>,
 221                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
 222                                           IRQ_TYPE_LEVEL_LOW)>,
 223                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
 224                                           IRQ_TYPE_LEVEL_LOW)>;
 225         };
 226
 227         soc {
 228                 compatible = "simple-bus";
 229                 #address-cells = <2>;
 230                 #size-cells = <2>;
 231                 ranges;
 232
 233                 crg_ctrl: crg_ctrl@fff35000 {
 234                         compatible = "hisilicon,hi3660-crgctrl", "syscon";
 235                         reg = <0x0 0xfff35000 0x0 0x1000>;
 236                         #clock-cells = <1>;
 237                 };
 238
 239                 crg_rst: crg_rst_controller {
 240                         compatible = "hisilicon,hi3660-reset";
 241                         #reset-cells = <2>;
 242                         hisi,rst-syscon = <&crg_ctrl>;
 243                 };
 244
 245
 246                 pctrl: pctrl@e8a09000 {
 247                         compatible = "hisilicon,hi3660-pctrl", "syscon";
 248                         reg = <0x0 0xe8a09000 0x0 0x2000>;
 249                         #clock-cells = <1>;
 250                 };
 251
 252                 pmuctrl: crg_ctrl@fff34000 {
 253                         compatible = "hisilicon,hi3660-pmuctrl", "syscon";
 254                         reg = <0x0 0xfff34000 0x0 0x1000>;
 255                         #clock-cells = <1>;
 256                 };
 257
 258                 sctrl: sctrl@fff0a000 {
 259                         compatible = "hisilicon,hi3660-sctrl", "syscon";
 260                         reg = <0x0 0xfff0a000 0x0 0x1000>;
 261                         #clock-cells = <1>;
 262                 };
 263
 264                 iomcu: iomcu@ffd7e000 {
 265                         compatible = "hisilicon,hi3660-iomcu", "syscon";
 266                         reg = <0x0 0xffd7e000 0x0 0x1000>;
 267                         #clock-cells = <1>;
 268
 269                 };
 270
 271                 iomcu_rst: reset {
 272                         compatible = "hisilicon,hi3660-reset";
 273                         hisi,rst-syscon = <&iomcu>;
 274                         #reset-cells = <2>;
 275                 };
 276
 277                 mailbox: mailbox@e896b000 {
 278                         compatible = "hisilicon,hi3660-mbox";
 279                         reg = <0x0 0xe896b000 0x0 0x1000>;
 280                         interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
 281                                      <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 282                         #mbox-cells = <3>;
 283                 };
 284
 285                 stub_clock: stub_clock@e896b500 {
 286                         compatible = "hisilicon,hi3660-stub-clk";
 287                         reg = <0x0 0xe896b500 0x0 0x0100>;
 288                         #clock-cells = <1>;
 289                         mboxes = <&mailbox 13 3 0>;
 290                 };
 291
 292                 dual_timer0: timer@fff14000 {
 293                         compatible = "arm,sp804", "arm,primecell";
 294                         reg = <0x0 0xfff14000 0x0 0x1000>;
 295                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
 296                                      <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 297                         clocks = <&crg_ctrl HI3660_OSC32K>,
 298                                  <&crg_ctrl HI3660_OSC32K>,
 299                                  <&crg_ctrl HI3660_OSC32K>;
 300                         clock-names = "timer1", "timer2", "apb_pclk";
 301                 };
 302
 303                 i2c0: i2c@ffd71000 {
 304                         compatible = "snps,designware-i2c";
 305                         reg = <0x0 0xffd71000 0x0 0x1000>;
 306                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 307                         #address-cells = <1>;
 308                         #size-cells = <0>;
 309                         clock-frequency = <400000>;
 310                         clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
 311                         resets = <&iomcu_rst 0x20 3>;
 312                         pinctrl-names = "default";
 313                         pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
 314                         status = "disabled";
 315                 };
 316
 317                 i2c1: i2c@ffd72000 {
 318                         compatible = "snps,designware-i2c";
 319                         reg = <0x0 0xffd72000 0x0 0x1000>;
 320                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 321                         #address-cells = <1>;
 322                         #size-cells = <0>;
 323                         clock-frequency = <400000>;
 324                         clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>;
 325                         resets = <&iomcu_rst 0x20 4>;
 326                         pinctrl-names = "default";
 327                         pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
 328                         status = "disabled";
 329                 };
 330
 331                 i2c3: i2c@fdf0c000 {
 332                         compatible = "snps,designware-i2c";
 333                         reg = <0x0 0xfdf0c000 0x0 0x1000>;
 334                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 335                         #address-cells = <1>;
 336                         #size-cells = <0>;
 337                         clock-frequency = <400000>;
 338                         clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>;
 339                         resets = <&crg_rst 0x78 7>;
 340                         pinctrl-names = "default";
 341                         pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>;
 342                         status = "disabled";
 343                 };
 344
 345                 i2c7: i2c@fdf0b000 {
 346                         compatible = "snps,designware-i2c";
 347                         reg = <0x0 0xfdf0b000 0x0 0x1000>;
 348                         interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
 349                         #address-cells = <1>;
 350                         #size-cells = <0>;
 351                         clock-frequency = <400000>;
 352                         clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>;
 353                         resets = <&crg_rst 0x60 14>;
 354                         pinctrl-names = "default";
 355                         pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>;
 356                         status = "disabled";
 357                 };
 358
 359                 uart0: serial@fdf02000 {
 360                         compatible = "arm,pl011", "arm,primecell";
 361                         reg = <0x0 0xfdf02000 0x0 0x1000>;
 362                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 363                         clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
 364                                  <&crg_ctrl HI3660_PCLK>;
 365                         clock-names = "uartclk", "apb_pclk";
 366                         pinctrl-names = "default";
 367                         pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
 368                         status = "disabled";
 369                 };
 370
 371                 uart1: serial@fdf00000 {
 372                         compatible = "arm,pl011", "arm,primecell";
 373                         reg = <0x0 0xfdf00000 0x0 0x1000>;
 374                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 375                         clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>,
 376                                  <&crg_ctrl HI3660_CLK_GATE_UART1>;
 377                         clock-names = "uartclk", "apb_pclk";
 378                         pinctrl-names = "default";
 379                         pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
 380                         status = "disabled";
 381                 };
 382
 383                 uart2: serial@fdf03000 {
 384                         compatible = "arm,pl011", "arm,primecell";
 385                         reg = <0x0 0xfdf03000 0x0 0x1000>;
 386                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 387                         clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>,
 388                                  <&crg_ctrl HI3660_PCLK>;
 389                         clock-names = "uartclk", "apb_pclk";
 390                         pinctrl-names = "default";
 391                         pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
 392                         status = "disabled";
 393                 };
 394
 395                 uart3: serial@ffd74000 {
 396                         compatible = "arm,pl011", "arm,primecell";
 397                         reg = <0x0 0xffd74000 0x0 0x1000>;
 398                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 399                         clocks = <&crg_ctrl HI3660_FACTOR_UART3>,
 400                                  <&crg_ctrl HI3660_PCLK>;
 401                         clock-names = "uartclk", "apb_pclk";
 402                         pinctrl-names = "default";
 403                         pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
 404                         status = "disabled";
 405                 };
 406
 407                 uart4: serial@fdf01000 {
 408                         compatible = "arm,pl011", "arm,primecell";
 409                         reg = <0x0 0xfdf01000 0x0 0x1000>;
 410                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 411                         clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>,
 412                                  <&crg_ctrl HI3660_CLK_GATE_UART4>;
 413                         clock-names = "uartclk", "apb_pclk";
 414                         pinctrl-names = "default";
 415                         pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
 416                         status = "disabled";
 417                 };
 418
 419                 uart5: serial@fdf05000 {
 420                         compatible = "arm,pl011", "arm,primecell";
 421                         reg = <0x0 0xfdf05000 0x0 0x1000>;
 422                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 423                         clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>,
 424                                  <&crg_ctrl HI3660_CLK_GATE_UART5>;
 425                         clock-names = "uartclk", "apb_pclk";
 426                         pinctrl-names = "default";
 427                         pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>;
 428                         status = "disabled";
 429                 };
 430
 431                 uart6: serial@fff32000 {
 432                         compatible = "arm,pl011", "arm,primecell";
 433                         reg = <0x0 0xfff32000 0x0 0x1000>;
 434                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 435                         clocks = <&crg_ctrl HI3660_CLK_UART6>,
 436                                  <&crg_ctrl HI3660_PCLK>;
 437                         clock-names = "uartclk", "apb_pclk";
 438                         pinctrl-names = "default";
 439                         pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>;
 440                         status = "disabled";
 441                 };
 442
 443                 dma0: dma@fdf30000 {
 444                         compatible = "hisilicon,k3-dma-1.0";
 445                         reg = <0x0 0xfdf30000 0x0 0x1000>;
 446                         #dma-cells = <1>;
 447                         dma-channels = <16>;
 448                         dma-requests = <32>;
 449                         dma-min-chan = <1>;
 450                         interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 451                         clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>;
 452                         dma-no-cci;
 453                         dma-type = "hi3660_dma";
 454                 };
 455
 456                 rtc0: rtc@fff04000 {
 457                         compatible = "arm,pl031", "arm,primecell";
 458                         reg = <0x0 0Xfff04000 0x0 0x1000>;
 459                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 460                         clocks = <&crg_ctrl HI3660_PCLK>;
 461                         clock-names = "apb_pclk";
 462                 };
 463
 464                 gpio0: gpio@e8a0b000 {
 465                         compatible = "arm,pl061", "arm,primecell";
 466                         reg = <0 0xe8a0b000 0 0x1000>;
 467                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 468                         gpio-controller;
 469                         #gpio-cells = <2>;
 470                         gpio-ranges = <&pmx0 1 0 7>;
 471                         interrupt-controller;
 472                         #interrupt-cells = <2>;
 473                         clocks = <&crg_ctrl HI3660_PCLK_GPIO0>;
 474                         clock-names = "apb_pclk";
 475                 };
 476
 477                 gpio1: gpio@e8a0c000 {
 478                         compatible = "arm,pl061", "arm,primecell";
 479                         reg = <0 0xe8a0c000 0 0x1000>;
 480                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 481                         gpio-controller;
 482                         #gpio-cells = <2>;
 483                         gpio-ranges = <&pmx0 1 7 7>;
 484                         interrupt-controller;
 485                         #interrupt-cells = <2>;
 486                         clocks = <&crg_ctrl HI3660_PCLK_GPIO1>;
 487                         clock-names = "apb_pclk";
 488                 };
 489
 490                 gpio2: gpio@e8a0d000 {
 491                         compatible = "arm,pl061", "arm,primecell";
 492                         reg = <0 0xe8a0d000 0 0x1000>;
 493                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 494                         gpio-controller;
 495                         #gpio-cells = <2>;
 496                         gpio-ranges = <&pmx0 0 14 8>;
 497                         interrupt-controller;
 498                         #interrupt-cells = <2>;
 499                         clocks = <&crg_ctrl HI3660_PCLK_GPIO2>;
 500                         clock-names = "apb_pclk";
 501                 };
 502
 503                 gpio3: gpio@e8a0e000 {
 504                         compatible = "arm,pl061", "arm,primecell";
 505                         reg = <0 0xe8a0e000 0 0x1000>;
 506                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 507                         gpio-controller;
 508                         #gpio-cells = <2>;
 509                         gpio-ranges = <&pmx0 0 22 8>;
 510                         interrupt-controller;
 511                         #interrupt-cells = <2>;
 512                         clocks = <&crg_ctrl HI3660_PCLK_GPIO3>;
 513                         clock-names = "apb_pclk";
 514                 };
 515
 516                 gpio4: gpio@e8a0f000 {
 517                         compatible = "arm,pl061", "arm,primecell";
 518                         reg = <0 0xe8a0f000 0 0x1000>;
 519                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 520                         gpio-controller;
 521                         #gpio-cells = <2>;
 522                         gpio-ranges = <&pmx0 0 30 8>;
 523                         interrupt-controller;
 524                         #interrupt-cells = <2>;
 525                         clocks = <&crg_ctrl HI3660_PCLK_GPIO4>;
 526                         clock-names = "apb_pclk";
 527                 };
 528
 529                 gpio5: gpio@e8a10000 {
 530                         compatible = "arm,pl061", "arm,primecell";
 531                         reg = <0 0xe8a10000 0 0x1000>;
 532                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 533                         gpio-controller;
 534                         #gpio-cells = <2>;
 535                         gpio-ranges = <&pmx0 0 38 8>;
 536                         interrupt-controller;
 537                         #interrupt-cells = <2>;
 538                         clocks = <&crg_ctrl HI3660_PCLK_GPIO5>;
 539                         clock-names = "apb_pclk";
 540                 };
 541
 542                 gpio6: gpio@e8a11000 {
 543                         compatible = "arm,pl061", "arm,primecell";
 544                         reg = <0 0xe8a11000 0 0x1000>;
 545                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 546                         gpio-controller;
 547                         #gpio-cells = <2>;
 548                         gpio-ranges = <&pmx0 0 46 8>;
 549                         interrupt-controller;
 550                         #interrupt-cells = <2>;
 551                         clocks = <&crg_ctrl HI3660_PCLK_GPIO6>;
 552                         clock-names = "apb_pclk";
 553                 };
 554
 555                 gpio7: gpio@e8a12000 {
 556                         compatible = "arm,pl061", "arm,primecell";
 557                         reg = <0 0xe8a12000 0 0x1000>;
 558                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 559                         gpio-controller;
 560                         #gpio-cells = <2>;
 561                         gpio-ranges = <&pmx0 0 54 8>;
 562                         interrupt-controller;
 563                         #interrupt-cells = <2>;
 564                         clocks = <&crg_ctrl HI3660_PCLK_GPIO7>;
 565                         clock-names = "apb_pclk";
 566                 };
 567
 568                 gpio8: gpio@e8a13000 {
 569                         compatible = "arm,pl061", "arm,primecell";
 570                         reg = <0 0xe8a13000 0 0x1000>;
 571                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 572                         gpio-controller;
 573                         #gpio-cells = <2>;
 574                         gpio-ranges = <&pmx0 0 62 8>;
 575                         interrupt-controller;
 576                         #interrupt-cells = <2>;
 577                         clocks = <&crg_ctrl HI3660_PCLK_GPIO8>;
 578                         clock-names = "apb_pclk";
 579                 };
 580
 581                 gpio9: gpio@e8a14000 {
 582                         compatible = "arm,pl061", "arm,primecell";
 583                         reg = <0 0xe8a14000 0 0x1000>;
 584                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 585                         gpio-controller;
 586                         #gpio-cells = <2>;
 587                         gpio-ranges = <&pmx0 0 70 8>;
 588                         interrupt-controller;
 589                         #interrupt-cells = <2>;
 590                         clocks = <&crg_ctrl HI3660_PCLK_GPIO9>;
 591                         clock-names = "apb_pclk";
 592                 };
 593
 594                 gpio10: gpio@e8a15000 {
 595                         compatible = "arm,pl061", "arm,primecell";
 596                         reg = <0 0xe8a15000 0 0x1000>;
 597                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 598                         gpio-controller;
 599                         #gpio-cells = <2>;
 600                         gpio-ranges = <&pmx0 0 78 8>;
 601                         interrupt-controller;
 602                         #interrupt-cells = <2>;
 603                         clocks = <&crg_ctrl HI3660_PCLK_GPIO10>;
 604                         clock-names = "apb_pclk";
 605                 };
 606
 607                 gpio11: gpio@e8a16000 {
 608                         compatible = "arm,pl061", "arm,primecell";
 609                         reg = <0 0xe8a16000 0 0x1000>;
 610                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 611                         gpio-controller;
 612                         #gpio-cells = <2>;
 613                         gpio-ranges = <&pmx0 0 86 8>;
 614                         interrupt-controller;
 615                         #interrupt-cells = <2>;
 616                         clocks = <&crg_ctrl HI3660_PCLK_GPIO11>;
 617                         clock-names = "apb_pclk";
 618                 };
 619
 620                 gpio12: gpio@e8a17000 {
 621                         compatible = "arm,pl061", "arm,primecell";
 622                         reg = <0 0xe8a17000 0 0x1000>;
 623                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 624                         gpio-controller;
 625                         #gpio-cells = <2>;
 626                         gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>;
 627                         interrupt-controller;
 628                         #interrupt-cells = <2>;
 629                         clocks = <&crg_ctrl HI3660_PCLK_GPIO12>;
 630                         clock-names = "apb_pclk";
 631                 };
 632
 633                 gpio13: gpio@e8a18000 {
 634                         compatible = "arm,pl061", "arm,primecell";
 635                         reg = <0 0xe8a18000 0 0x1000>;
 636                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 637                         gpio-controller;
 638                         #gpio-cells = <2>;
 639                         gpio-ranges = <&pmx0 0 102 8>;
 640                         interrupt-controller;
 641                         #interrupt-cells = <2>;
 642                         clocks = <&crg_ctrl HI3660_PCLK_GPIO13>;
 643                         clock-names = "apb_pclk";
 644                 };
 645
 646                 gpio14: gpio@e8a19000 {
 647                         compatible = "arm,pl061", "arm,primecell";
 648                         reg = <0 0xe8a19000 0 0x1000>;
 649                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 650                         gpio-controller;
 651                         #gpio-cells = <2>;
 652                         gpio-ranges = <&pmx0 0 110 8>;
 653                         interrupt-controller;
 654                         #interrupt-cells = <2>;
 655                         clocks = <&crg_ctrl HI3660_PCLK_GPIO14>;
 656                         clock-names = "apb_pclk";
 657                 };
 658
 659                 gpio15: gpio@e8a1a000 {
 660                         compatible = "arm,pl061", "arm,primecell";
 661                         reg = <0 0xe8a1a000 0 0x1000>;
 662                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 663                         gpio-controller;
 664                         #gpio-cells = <2>;
 665                         gpio-ranges = <&pmx0 0 118 6>;
 666                         interrupt-controller;
 667                         #interrupt-cells = <2>;
 668                         clocks = <&crg_ctrl HI3660_PCLK_GPIO15>;
 669                         clock-names = "apb_pclk";
 670                 };
 671
 672                 gpio16: gpio@e8a1b000 {
 673                         compatible = "arm,pl061", "arm,primecell";
 674                         reg = <0 0xe8a1b000 0 0x1000>;
 675                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 676                         gpio-controller;
 677                         #gpio-cells = <2>;
 678                         interrupt-controller;
 679                         #interrupt-cells = <2>;
 680                         clocks = <&crg_ctrl HI3660_PCLK_GPIO16>;
 681                         clock-names = "apb_pclk";
 682                 };
 683
 684                 gpio17: gpio@e8a1c000 {
 685                         compatible = "arm,pl061", "arm,primecell";
 686                         reg = <0 0xe8a1c000 0 0x1000>;
 687                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 688                         gpio-controller;
 689                         #gpio-cells = <2>;
 690                         interrupt-controller;
 691                         #interrupt-cells = <2>;
 692                         clocks = <&crg_ctrl HI3660_PCLK_GPIO17>;
 693                         clock-names = "apb_pclk";
 694                 };
 695
 696                 gpio18: gpio@ff3b4000 {
 697                         compatible = "arm,pl061", "arm,primecell";
 698                         reg = <0 0xff3b4000 0 0x1000>;
 699                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 700                         gpio-controller;
 701                         #gpio-cells = <2>;
 702                         gpio-ranges = <&pmx2 0 0 8>;
 703                         interrupt-controller;
 704                         #interrupt-cells = <2>;
 705                         clocks = <&crg_ctrl HI3660_PCLK_GPIO18>;
 706                         clock-names = "apb_pclk";
 707                 };
 708
 709                 gpio19: gpio@ff3b5000 {
 710                         compatible = "arm,pl061", "arm,primecell";
 711                         reg = <0 0xff3b5000 0 0x1000>;
 712                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 713                         gpio-controller;
 714                         #gpio-cells = <2>;
 715                         gpio-ranges = <&pmx2 0 8 4>;
 716                         interrupt-controller;
 717                         #interrupt-cells = <2>;
 718                         clocks = <&crg_ctrl HI3660_PCLK_GPIO19>;
 719                         clock-names = "apb_pclk";
 720                 };
 721
 722                 gpio20: gpio@e8a1f000 {
 723                         compatible = "arm,pl061", "arm,primecell";
 724                         reg = <0 0xe8a1f000 0 0x1000>;
 725                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 726                         gpio-controller;
 727                         #gpio-cells = <2>;
 728                         gpio-ranges = <&pmx1 0 0 6>;
 729                         interrupt-controller;
 730                         #interrupt-cells = <2>;
 731                         clocks = <&crg_ctrl HI3660_PCLK_GPIO20>;
 732                         clock-names = "apb_pclk";
 733                 };
 734
 735                 gpio21: gpio@e8a20000 {
 736                         compatible = "arm,pl061", "arm,primecell";
 737                         reg = <0 0xe8a20000 0 0x1000>;
 738                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 739                         gpio-controller;
 740                         #gpio-cells = <2>;
 741                         interrupt-controller;
 742                         #interrupt-cells = <2>;
 743                         gpio-ranges = <&pmx3 0 0 6>;
 744                         clocks = <&crg_ctrl HI3660_PCLK_GPIO21>;
 745                         clock-names = "apb_pclk";
 746                 };
 747
 748                 gpio22: gpio@fff0b000 {
 749                         compatible = "arm,pl061", "arm,primecell";
 750                         reg = <0 0xfff0b000 0 0x1000>;
 751                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 752                         gpio-controller;
 753                         #gpio-cells = <2>;
 754                         /* GPIO176 */
 755                         gpio-ranges = <&pmx4 2 0 6>;
 756                         interrupt-controller;
 757                         #interrupt-cells = <2>;
 758                         clocks = <&sctrl HI3660_PCLK_AO_GPIO0>;
 759                         clock-names = "apb_pclk";
 760                 };
 761
 762                 gpio23: gpio@fff0c000 {
 763                         compatible = "arm,pl061", "arm,primecell";
 764                         reg = <0 0xfff0c000 0 0x1000>;
 765                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 766                         gpio-controller;
 767                         #gpio-cells = <2>;
 768                         /* GPIO184 */
 769                         gpio-ranges = <&pmx4 0 6 7>;
 770                         interrupt-controller;
 771                         #interrupt-cells = <2>;
 772                         clocks = <&sctrl HI3660_PCLK_AO_GPIO1>;
 773                         clock-names = "apb_pclk";
 774                 };
 775
 776                 gpio24: gpio@fff0d000 {
 777                         compatible = "arm,pl061", "arm,primecell";
 778                         reg = <0 0xfff0d000 0 0x1000>;
 779                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 780                         gpio-controller;
 781                         #gpio-cells = <2>;
 782                         /* GPIO192 */
 783                         gpio-ranges = <&pmx4 0 13 8>;
 784                         interrupt-controller;
 785                         #interrupt-cells = <2>;
 786                         clocks = <&sctrl HI3660_PCLK_AO_GPIO2>;
 787                         clock-names = "apb_pclk";
 788                 };
 789
 790                 gpio25: gpio@fff0e000 {
 791                         compatible = "arm,pl061", "arm,primecell";
 792                         reg = <0 0xfff0e000 0 0x1000>;
 793                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 794                         gpio-controller;
 795                         #gpio-cells = <2>;
 796                         /* GPIO200 */
 797                         gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>;
 798                         interrupt-controller;
 799                         #interrupt-cells = <2>;
 800                         clocks = <&sctrl HI3660_PCLK_AO_GPIO3>;
 801                         clock-names = "apb_pclk";
 802                 };
 803
 804                 gpio26: gpio@fff0f000 {
 805                         compatible = "arm,pl061", "arm,primecell";
 806                         reg = <0 0xfff0f000 0 0x1000>;
 807                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 808                         gpio-controller;
 809                         #gpio-cells = <2>;
 810                         /* GPIO208 */
 811                         gpio-ranges = <&pmx4 0 28 8>;
 812                         interrupt-controller;
 813                         #interrupt-cells = <2>;
 814                         clocks = <&sctrl HI3660_PCLK_AO_GPIO4>;
 815                         clock-names = "apb_pclk";
 816                 };
 817
 818                 gpio27: gpio@fff10000 {
 819                         compatible = "arm,pl061", "arm,primecell";
 820                         reg = <0 0xfff10000 0 0x1000>;
 821                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 822                         gpio-controller;
 823                         #gpio-cells = <2>;
 824                         /* GPIO216 */
 825                         gpio-ranges = <&pmx4 0 36 6>;
 826                         interrupt-controller;
 827                         #interrupt-cells = <2>;
 828                         clocks = <&sctrl HI3660_PCLK_AO_GPIO5>;
 829                         clock-names = "apb_pclk";
 830                 };
 831
 832                 gpio28: gpio@fff1d000 {
 833                         compatible = "arm,pl061", "arm,primecell";
 834                         reg = <0 0xfff1d000 0 0x1000>;
 835                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 836                         gpio-controller;
 837                         #gpio-cells = <2>;
 838                         interrupt-controller;
 839                         #interrupt-cells = <2>;
 840                         clocks = <&sctrl HI3660_PCLK_AO_GPIO6>;
 841                         clock-names = "apb_pclk";
 842                 };
 843
 844                 spi2: spi@ffd68000 {
 845                         compatible = "arm,pl022", "arm,primecell";
 846                         reg = <0x0 0xffd68000 0x0 0x1000>;
 847                         #address-cells = <1>;
 848                         #size-cells = <0>;
 849                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 850                         clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>;
 851                         clock-names = "apb_pclk";
 852                         pinctrl-names = "default";
 853                         pinctrl-0 = <&spi2_pmx_func>;
 854                         num-cs = <1>;
 855                         cs-gpios = <&gpio27 2 0>;
 856                         status = "disabled";
 857                 };
 858
 859                 spi3: spi@ff3b3000 {
 860                         compatible = "arm,pl022", "arm,primecell";
 861                         reg = <0x0 0xff3b3000 0x0 0x1000>;
 862                         #address-cells = <1>;
 863                         #size-cells = <0>;
 864                         interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
 865                         clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>;
 866                         clock-names = "apb_pclk";
 867                         pinctrl-names = "default";
 868                         pinctrl-0 = <&spi3_pmx_func>;
 869                         num-cs = <1>;
 870                         cs-gpios = <&gpio18 5 0>;
 871                         status = "disabled";
 872                 };
 873
 874                 pcie@f4000000 {
 875                         compatible = "hisilicon,kirin960-pcie";
 876                         reg = <0x0 0xf4000000 0x0 0x1000>,
 877                               <0x0 0xff3fe000 0x0 0x1000>,
 878                               <0x0 0xf3f20000 0x0 0x40000>,
 879                               <0x0 0xf5000000 0x0 0x2000>;
 880                         reg-names = "dbi", "apb", "phy", "config";
 881                         bus-range = <0x0  0x1>;
 882                         #address-cells = <3>;
 883                         #size-cells = <2>;
 884                         device_type = "pci";
 885                         ranges = <0x02000000 0x0 0x00000000
 886                                   0x0 0xf6000000
 887                                   0x0 0x02000000>;
 888                         num-lanes = <1>;
 889                         #interrupt-cells = <1>;
 890                         interrupt-map-mask = <0xf800 0 0 7>;
 891                         interrupt-map = <0x0 0 0 1
 892                                          &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
 893                                         <0x0 0 0 2
 894                                          &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
 895                                         <0x0 0 0 3
 896                                          &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
 897                                         <0x0 0 0 4
 898                                          &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
 899                         clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
 900                                  <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
 901                                  <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
 902                                  <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
 903                                  <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
 904                         clock-names = "pcie_phy_ref", "pcie_aux",
 905                                       "pcie_apb_phy", "pcie_apb_sys",
 906                                       "pcie_aclk";
 907                         reset-gpios = <&gpio11 1 0 >;
 908                 };
 909
 910                 /* SD */
 911                 dwmmc1: dwmmc1@ff37f000 {
 912                         #address-cells = <1>;
 913                         #size-cells = <0>;
 914                         cd-inverted;
 915                         compatible = "hisilicon,hi3660-dw-mshc";
 916                         bus-width = <0x4>;
 917                         disable-wp;
 918                         cap-sd-highspeed;
 919                         supports-highspeed;
 920                         card-detect-delay = <200>;
 921                         reg = <0x0 0xff37f000 0x0 0x1000>;
 922                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 923                         clocks = <&crg_ctrl HI3660_CLK_GATE_SD>,
 924                                 <&crg_ctrl HI3660_HCLK_GATE_SD>;
 925                         clock-names = "ciu", "biu";
 926                         clock-frequency = <3200000>;
 927                         resets = <&crg_rst 0x94 18>;
 928                         reset-names = "reset";
 929                         cd-gpios = <&gpio25 3 0>;
 930                         hisilicon,peripheral-syscon = <&sctrl>;
 931                         pinctrl-names = "default";
 932                         pinctrl-0 = <&sd_pmx_func
 933                                      &sd_clk_cfg_func
 934                                      &sd_cfg_func>;
 935                         sd-uhs-sdr12;
 936                         sd-uhs-sdr25;
 937                         sd-uhs-sdr50;
 938                         sd-uhs-sdr104;
 939                         status = "disabled";
 940
 941                         slot@0 {
 942                                 reg = <0x0>;
 943                                 bus-width = <4>;
 944                                 disable-wp;
 945                         };
 946                 };
 947
 948                 /* SDIO */
 949                 dwmmc2: dwmmc2@ff3ff000 {
 950                         compatible = "hisilicon,hi3660-dw-mshc";
 951                         reg = <0x0 0xff3ff000 0x0 0x1000>;
 952                         interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 953                         clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>,
 954                                  <&crg_ctrl HI3660_HCLK_GATE_SDIO0>;
 955                         clock-names = "ciu", "biu";
 956                         resets = <&crg_rst 0x94 20>;
 957                         reset-names = "reset";
 958                         card-detect-delay = <200>;
 959                         supports-highspeed;
 960                         keep-power-in-suspend;
 961                         pinctrl-names = "default";
 962                         pinctrl-0 = <&sdio_pmx_func
 963                                      &sdio_clk_cfg_func
 964                                      &sdio_cfg_func>;
 965                         status = "disabled";
 966                 };
 967
 968                 watchdog0: watchdog@e8a06000 {
 969                         compatible = "arm,sp805-wdt", "arm,primecell";
 970                         reg = <0x0 0xe8a06000 0x0 0x1000>;
 971                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 972                         clocks = <&crg_ctrl HI3660_OSC32K>;
 973                         clock-names = "apb_pclk";
 974                 };
 975
 976                 watchdog1: watchdog@e8a07000 {
 977                         compatible = "arm,sp805-wdt", "arm,primecell";
 978                         reg = <0x0 0xe8a07000 0x0 0x1000>;
 979                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 980                         clocks = <&crg_ctrl HI3660_OSC32K>;
 981                         clock-names = "apb_pclk";
 982                 };
 983
 984                 tsensor: tsensor@fff30000 {
 985                         compatible = "hisilicon,hi3660-tsensor";
 986                         reg = <0x0 0xfff30000 0x0 0x1000>;
 987                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 988                         #thermal-sensor-cells = <1>;
 989                 };
 990         };
 991 };