1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP
5 * Dong Aisheng <aisheng.dong@nxp.com>
8 #include <dt-bindings/clock/imx8-clock.h>
9 #include <dt-bindings/firmware/imx/rsrc.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
14 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
34 serial0 = &adma_lpuart0;
35 serial1 = &adma_lpuart1;
36 serial2 = &adma_lpuart2;
37 serial3 = &adma_lpuart3;
44 /* We have 1 clusters with 4 Cortex-A35 cores */
47 compatible = "arm,cortex-a35";
49 enable-method = "psci";
50 next-level-cache = <&A35_L2>;
51 clocks = <&clk IMX_A35_CLK>;
52 operating-points-v2 = <&a35_opp_table>;
58 compatible = "arm,cortex-a35";
60 enable-method = "psci";
61 next-level-cache = <&A35_L2>;
62 clocks = <&clk IMX_A35_CLK>;
63 operating-points-v2 = <&a35_opp_table>;
69 compatible = "arm,cortex-a35";
71 enable-method = "psci";
72 next-level-cache = <&A35_L2>;
73 clocks = <&clk IMX_A35_CLK>;
74 operating-points-v2 = <&a35_opp_table>;
80 compatible = "arm,cortex-a35";
82 enable-method = "psci";
83 next-level-cache = <&A35_L2>;
84 clocks = <&clk IMX_A35_CLK>;
85 operating-points-v2 = <&a35_opp_table>;
94 a35_opp_table: opp-table {
95 compatible = "operating-points-v2";
99 opp-hz = /bits/ 64 <900000000>;
100 opp-microvolt = <1000000>;
101 clock-latency-ns = <150000>;
105 opp-hz = /bits/ 64 <1200000000>;
106 opp-microvolt = <1100000>;
107 clock-latency-ns = <150000>;
112 gic: interrupt-controller@51a00000 {
113 compatible = "arm,gic-v3";
114 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
115 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
116 #interrupt-cells = <3>;
117 interrupt-controller;
118 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
122 #address-cells = <2>;
126 dsp_reserved: dsp@92400000 {
127 reg = <0 0x92400000 0 0x2000000>;
133 compatible = "arm,armv8-pmuv3";
134 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
138 compatible = "arm,psci-1.0";
143 compatible = "fsl,imx-scu";
144 mbox-names = "tx0", "tx1", "tx2", "tx3",
145 "rx0", "rx1", "rx2", "rx3",
147 mboxes = <&lsio_mu1 0 0
157 clk: clock-controller {
158 compatible = "fsl,imx8qxp-clk";
160 clocks = <&xtal32k &xtal24m>;
161 clock-names = "xtal_32KHz", "xtal_24Mhz";
165 compatible = "fsl,imx8qxp-iomuxc";
168 ocotp: imx8qx-ocotp {
169 compatible = "fsl,imx8qxp-scu-ocotp";
170 #address-cells = <1>;
175 compatible = "fsl,imx8qxp-scu-pd";
176 #power-domain-cells = <1>;
180 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
181 linux,keycodes = <KEY_POWER>;
186 compatible = "fsl,imx8qxp-sc-rtc";
190 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
194 tsens: thermal-sensor {
195 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
196 #thermal-sensor-cells = <1>;
201 compatible = "arm,armv8-timer";
202 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
203 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
204 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
205 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
208 xtal32k: clock-xtal32k {
209 compatible = "fixed-clock";
211 clock-frequency = <32768>;
212 clock-output-names = "xtal_32KHz";
215 xtal24m: clock-xtal24m {
216 compatible = "fixed-clock";
218 clock-frequency = <24000000>;
219 clock-output-names = "xtal_24MHz";
222 adma_subsys: bus@59000000 {
223 compatible = "simple-bus";
224 #address-cells = <1>;
226 ranges = <0x59000000 0x0 0x59000000 0x2000000>;
228 adma_lpcg: clock-controller@59000000 {
229 compatible = "fsl,imx8qxp-lpcg-adma";
230 reg = <0x59000000 0x2000000>;
234 adma_dsp: dsp@596e8000 {
235 compatible = "fsl,imx8qxp-dsp";
236 reg = <0x596e8000 0x88000>;
237 clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>,
238 <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,
239 <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;
240 clock-names = "ipg", "ocram", "core";
241 power-domains = <&pd IMX_SC_R_MU_13A>,
242 <&pd IMX_SC_R_MU_13B>,
244 <&pd IMX_SC_R_DSP_RAM>;
245 mbox-names = "txdb0", "txdb1",
247 mboxes = <&lsio_mu13 2 0>,
251 memory-region = <&dsp_reserved>;
255 adma_lpuart0: serial@5a060000 {
256 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
257 reg = <0x5a060000 0x1000>;
258 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>,
260 <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>;
261 clock-names = "ipg", "baud";
262 power-domains = <&pd IMX_SC_R_UART_0>;
266 adma_lpuart1: serial@5a070000 {
267 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
268 reg = <0x5a070000 0x1000>;
269 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>,
271 <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>;
272 clock-names = "ipg", "baud";
273 power-domains = <&pd IMX_SC_R_UART_1>;
277 adma_lpuart2: serial@5a080000 {
278 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
279 reg = <0x5a080000 0x1000>;
280 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>,
282 <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>;
283 clock-names = "ipg", "baud";
284 power-domains = <&pd IMX_SC_R_UART_2>;
288 adma_lpuart3: serial@5a090000 {
289 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
290 reg = <0x5a090000 0x1000>;
291 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>,
293 <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>;
294 clock-names = "ipg", "baud";
295 power-domains = <&pd IMX_SC_R_UART_3>;
299 adma_i2c0: i2c@5a800000 {
300 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
301 reg = <0x5a800000 0x4000>;
302 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>;
305 assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>;
306 assigned-clock-rates = <24000000>;
307 power-domains = <&pd IMX_SC_R_I2C_0>;
311 adma_i2c1: i2c@5a810000 {
312 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
313 reg = <0x5a810000 0x4000>;
314 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>;
317 assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>;
318 assigned-clock-rates = <24000000>;
319 power-domains = <&pd IMX_SC_R_I2C_1>;
323 adma_i2c2: i2c@5a820000 {
324 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
325 reg = <0x5a820000 0x4000>;
326 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
327 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>;
329 assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>;
330 assigned-clock-rates = <24000000>;
331 power-domains = <&pd IMX_SC_R_I2C_2>;
335 adma_i2c3: i2c@5a830000 {
336 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
337 reg = <0x5a830000 0x4000>;
338 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
339 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>;
341 assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>;
342 assigned-clock-rates = <24000000>;
343 power-domains = <&pd IMX_SC_R_I2C_3>;
348 conn_subsys: bus@5b000000 {
349 compatible = "simple-bus";
350 #address-cells = <1>;
352 ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
354 conn_lpcg: clock-controller@5b200000 {
355 compatible = "fsl,imx8qxp-lpcg-conn";
356 reg = <0x5b200000 0xb0000>;
360 usdhc1: mmc@5b010000 {
361 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
362 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
363 reg = <0x5b010000 0x10000>;
364 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
365 <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
366 <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
367 clock-names = "ipg", "per", "ahb";
368 power-domains = <&pd IMX_SC_R_SDHC_0>;
372 usdhc2: mmc@5b020000 {
373 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
374 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
375 reg = <0x5b020000 0x10000>;
376 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>,
377 <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>,
378 <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>;
379 clock-names = "ipg", "per", "ahb";
380 power-domains = <&pd IMX_SC_R_SDHC_1>;
381 fsl,tuning-start-tap = <20>;
382 fsl,tuning-step= <2>;
386 usdhc3: mmc@5b030000 {
387 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
388 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
389 reg = <0x5b030000 0x10000>;
390 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>,
391 <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>,
392 <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>;
393 clock-names = "ipg", "per", "ahb";
394 power-domains = <&pd IMX_SC_R_SDHC_2>;
398 fec1: ethernet@5b040000 {
399 compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";
400 reg = <0x5b040000 0x10000>;
401 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>,
406 <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>,
407 <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>,
408 <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>;
409 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
410 fsl,num-tx-queues=<3>;
411 fsl,num-rx-queues=<3>;
412 power-domains = <&pd IMX_SC_R_ENET_0>;
416 fec2: ethernet@5b050000 {
417 compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";
418 reg = <0x5b050000 0x10000>;
419 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
420 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
421 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
422 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
423 clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>,
424 <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>,
425 <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>,
426 <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>;
427 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
428 fsl,num-tx-queues=<3>;
429 fsl,num-rx-queues=<3>;
430 power-domains = <&pd IMX_SC_R_ENET_1>;
435 ddr_subsyss: bus@5c000000 {
436 compatible = "simple-bus";
437 #address-cells = <1>;
439 ranges = <0x5c000000 0x0 0x5c000000 0x1000000>;
442 compatible = "fsl,imx8-ddr-pmu";
443 reg = <0x5c020000 0x10000>;
444 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
448 lsio_subsys: bus@5d000000 {
449 compatible = "simple-bus";
450 #address-cells = <1>;
452 ranges = <0x5d000000 0x0 0x5d000000 0x1000000>;
454 lsio_gpio0: gpio@5d080000 {
455 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
456 reg = <0x5d080000 0x10000>;
457 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
460 interrupt-controller;
461 #interrupt-cells = <2>;
462 power-domains = <&pd IMX_SC_R_GPIO_0>;
465 lsio_gpio1: gpio@5d090000 {
466 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
467 reg = <0x5d090000 0x10000>;
468 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
471 interrupt-controller;
472 #interrupt-cells = <2>;
473 power-domains = <&pd IMX_SC_R_GPIO_1>;
476 lsio_gpio2: gpio@5d0a0000 {
477 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
478 reg = <0x5d0a0000 0x10000>;
479 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
482 interrupt-controller;
483 #interrupt-cells = <2>;
484 power-domains = <&pd IMX_SC_R_GPIO_2>;
487 lsio_gpio3: gpio@5d0b0000 {
488 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
489 reg = <0x5d0b0000 0x10000>;
490 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
493 interrupt-controller;
494 #interrupt-cells = <2>;
495 power-domains = <&pd IMX_SC_R_GPIO_3>;
498 lsio_gpio4: gpio@5d0c0000 {
499 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
500 reg = <0x5d0c0000 0x10000>;
501 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
504 interrupt-controller;
505 #interrupt-cells = <2>;
506 power-domains = <&pd IMX_SC_R_GPIO_4>;
509 lsio_gpio5: gpio@5d0d0000 {
510 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
511 reg = <0x5d0d0000 0x10000>;
512 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
515 interrupt-controller;
516 #interrupt-cells = <2>;
517 power-domains = <&pd IMX_SC_R_GPIO_5>;
520 lsio_gpio6: gpio@5d0e0000 {
521 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
522 reg = <0x5d0e0000 0x10000>;
523 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
526 interrupt-controller;
527 #interrupt-cells = <2>;
528 power-domains = <&pd IMX_SC_R_GPIO_6>;
531 lsio_gpio7: gpio@5d0f0000 {
532 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
533 reg = <0x5d0f0000 0x10000>;
534 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
537 interrupt-controller;
538 #interrupt-cells = <2>;
539 power-domains = <&pd IMX_SC_R_GPIO_7>;
542 lsio_mu0: mailbox@5d1b0000 {
543 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
544 reg = <0x5d1b0000 0x10000>;
545 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
550 lsio_mu1: mailbox@5d1c0000 {
551 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
552 reg = <0x5d1c0000 0x10000>;
553 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
557 lsio_mu2: mailbox@5d1d0000 {
558 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
559 reg = <0x5d1d0000 0x10000>;
560 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
565 lsio_mu3: mailbox@5d1e0000 {
566 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
567 reg = <0x5d1e0000 0x10000>;
568 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
573 lsio_mu4: mailbox@5d1f0000 {
574 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
575 reg = <0x5d1f0000 0x10000>;
576 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
581 lsio_mu13: mailbox@5d280000 {
582 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
583 reg = <0x5d280000 0x10000>;
584 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
586 power-domains = <&pd IMX_SC_R_MU_13A>;
589 lsio_lpcg: clock-controller@5d400000 {
590 compatible = "fsl,imx8qxp-lpcg-lsio";
591 reg = <0x5d400000 0x400000>;
596 thermal_zones: thermal-zones {
598 polling-delay-passive = <250>;
599 polling-delay = <2000>;
600 thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
604 temperature = <107000>;
610 temperature = <127000>;
618 trip = <&cpu_alert0>;
620 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
621 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
622 <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
623 <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;