1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2020 NXP
5 * Dong Aisheng <aisheng.dong@nxp.com>
8 #include <dt-bindings/clock/imx8-clock.h>
9 #include <dt-bindings/clock/imx8-lpcg.h>
10 #include <dt-bindings/firmware/imx/rsrc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
15 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
55 /* We have 1 clusters with 4 Cortex-A35 cores */
58 compatible = "arm,cortex-a35";
60 enable-method = "psci";
61 next-level-cache = <&A35_L2>;
62 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
63 operating-points-v2 = <&a35_opp_table>;
69 compatible = "arm,cortex-a35";
71 enable-method = "psci";
72 next-level-cache = <&A35_L2>;
73 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
74 operating-points-v2 = <&a35_opp_table>;
80 compatible = "arm,cortex-a35";
82 enable-method = "psci";
83 next-level-cache = <&A35_L2>;
84 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
85 operating-points-v2 = <&a35_opp_table>;
91 compatible = "arm,cortex-a35";
93 enable-method = "psci";
94 next-level-cache = <&A35_L2>;
95 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
96 operating-points-v2 = <&a35_opp_table>;
101 compatible = "cache";
105 a35_opp_table: opp-table {
106 compatible = "operating-points-v2";
110 opp-hz = /bits/ 64 <900000000>;
111 opp-microvolt = <1000000>;
112 clock-latency-ns = <150000>;
116 opp-hz = /bits/ 64 <1200000000>;
117 opp-microvolt = <1100000>;
118 clock-latency-ns = <150000>;
123 gic: interrupt-controller@51a00000 {
124 compatible = "arm,gic-v3";
125 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
126 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
127 #interrupt-cells = <3>;
128 interrupt-controller;
129 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
133 #address-cells = <2>;
137 dsp_reserved: dsp@92400000 {
138 reg = <0 0x92400000 0 0x2000000>;
144 compatible = "arm,armv8-pmuv3";
145 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
149 compatible = "arm,psci-1.0";
154 compatible = "fsl,imx-scu";
158 mboxes = <&lsio_mu1 0 0
163 compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
164 #power-domain-cells = <1>;
167 clk: clock-controller {
168 compatible = "fsl,imx8qxp-clk";
170 clocks = <&xtal32k &xtal24m>;
171 clock-names = "xtal_32KHz", "xtal_24Mhz";
175 compatible = "fsl,imx8qxp-iomuxc";
178 ocotp: imx8qx-ocotp {
179 compatible = "fsl,imx8qxp-scu-ocotp";
180 #address-cells = <1>;
185 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
186 linux,keycodes = <KEY_POWER>;
191 compatible = "fsl,imx8qxp-sc-rtc";
195 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
199 tsens: thermal-sensor {
200 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
201 #thermal-sensor-cells = <1>;
206 compatible = "arm,armv8-timer";
207 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
208 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
209 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
210 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
213 xtal32k: clock-xtal32k {
214 compatible = "fixed-clock";
216 clock-frequency = <32768>;
217 clock-output-names = "xtal_32KHz";
220 xtal24m: clock-xtal24m {
221 compatible = "fixed-clock";
223 clock-frequency = <24000000>;
224 clock-output-names = "xtal_24MHz";
227 thermal_zones: thermal-zones {
229 polling-delay-passive = <250>;
230 polling-delay = <2000>;
231 thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
235 temperature = <107000>;
241 temperature = <127000>;
249 trip = <&cpu_alert0>;
251 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
252 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
253 <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
254 <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
260 /* sorted in register address */
261 #include "imx8-ss-adma.dtsi"
262 #include "imx8-ss-conn.dtsi"
263 #include "imx8-ss-ddr.dtsi"
264 #include "imx8-ss-lsio.dtsi"
267 #include "imx8qxp-ss-adma.dtsi"
268 #include "imx8qxp-ss-conn.dtsi"
269 #include "imx8qxp-ss-lsio.dtsi"