1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017~2018 NXP
8 #include "imx8qxp.dtsi"
11 model = "Freescale i.MX8QXP MEK";
12 compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
15 stdout-path = &lpuart0;
19 device_type = "memory";
20 reg = <0x00000000 0x80000000 0 0x40000000>;
23 reg_usdhc2_vmmc: usdhc2-vmmc {
24 compatible = "regulator-fixed";
25 regulator-name = "SD1_SPWR";
26 regulator-min-microvolt = <3000000>;
27 regulator-max-microvolt = <3000000>;
28 gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_fec1>;
40 phy-mode = "rgmii-id";
41 phy-handle = <ðphy0>;
49 ethphy0: ethernet-phy@0 {
50 compatible = "ethernet-phy-ieee802.3-c22";
59 clock-frequency = <100000>;
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>;
65 compatible = "nxp,pca9646", "nxp,pca9546";
69 reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>;
77 compatible = "maxim,max7322";
96 compatible = "fsl,mpl3115";
102 #address-cells = <1>;
107 compatible = "nxp,pca9557";
114 compatible = "nxp,pca9557";
121 pinctrl-names = "default";
122 pinctrl-0 = <&pinctrl_isl29023>;
123 compatible = "isil,isl29023";
125 interrupt-parent = <&lsio_gpio1>;
126 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
133 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_lpuart0>;
144 polling-delay-passive = <250>;
145 polling-delay = <2000>;
146 thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
150 temperature = <110000>;
156 temperature = <125000>;
164 trip = <&pmic_alert0>;
166 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
167 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
168 <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
169 <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
176 assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>;
177 assigned-clock-rates = <200000000>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_usdhc1>;
188 assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>;
189 assigned-clock-rates = <200000000>;
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_usdhc2>;
193 vmmc-supply = <®_usdhc2_vmmc>;
194 cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
195 wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
200 pinctrl_fec1: fec1grp {
202 IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020
203 IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
204 IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
205 IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
206 IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
207 IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
208 IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
209 IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
210 IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
211 IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
212 IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
213 IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
214 IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
215 IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
219 pinctrl_ioexp_rst: ioexprstgrp {
221 IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021
225 pinctrl_isl29023: isl29023grp {
227 IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021
231 pinctrl_lpi2c1: lpi2c1grp {
233 IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021
234 IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021
238 pinctrl_lpuart0: lpuart0grp {
240 IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020
241 IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020
245 pinctrl_usdhc1: usdhc1grp {
247 IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
248 IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
249 IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
250 IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
251 IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
252 IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
253 IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
254 IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
255 IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
256 IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
257 IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
261 pinctrl_usdhc2: usdhc2grp {
263 IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
264 IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
265 IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
266 IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
267 IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
268 IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
269 IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021