arch/arm64/boot/dts/freescale/imx8mq.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2017 NXP
   4  * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
   5  */
   6
   7 #include <dt-bindings/clock/imx8mq-clock.h>
   8 #include <dt-bindings/power/imx8mq-power.h>
   9 #include <dt-bindings/reset/imx8mq-reset.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include "dt-bindings/input/input.h"
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14 #include "imx8mq-pinfunc.h"
  15
  16 / {
  17         interrupt-parent = <&gpc>;
  18
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 gpio0 = &gpio1;
  24                 gpio1 = &gpio2;
  25                 gpio2 = &gpio3;
  26                 gpio3 = &gpio4;
  27                 gpio4 = &gpio5;
  28                 i2c0 = &i2c1;
  29                 i2c1 = &i2c2;
  30                 i2c2 = &i2c3;
  31                 i2c3 = &i2c4;
  32                 serial0 = &uart1;
  33                 serial1 = &uart2;
  34                 serial2 = &uart3;
  35                 serial3 = &uart4;
  36                 spi0 = &ecspi1;
  37                 spi1 = &ecspi2;
  38                 spi2 = &ecspi3;
  39         };
  40
  41         ckil: clock-ckil {
  42                 compatible = "fixed-clock";
  43                 #clock-cells = <0>;
  44                 clock-frequency = <32768>;
  45                 clock-output-names = "ckil";
  46         };
  47
  48         osc_25m: clock-osc-25m {
  49                 compatible = "fixed-clock";
  50                 #clock-cells = <0>;
  51                 clock-frequency = <25000000>;
  52                 clock-output-names = "osc_25m";
  53         };
  54
  55         osc_27m: clock-osc-27m {
  56                 compatible = "fixed-clock";
  57                 #clock-cells = <0>;
  58                 clock-frequency = <27000000>;
  59                 clock-output-names = "osc_27m";
  60         };
  61
  62         clk_ext1: clock-ext1 {
  63                 compatible = "fixed-clock";
  64                 #clock-cells = <0>;
  65                 clock-frequency = <133000000>;
  66                 clock-output-names = "clk_ext1";
  67         };
  68
  69         clk_ext2: clock-ext2 {
  70                 compatible = "fixed-clock";
  71                 #clock-cells = <0>;
  72                 clock-frequency = <133000000>;
  73                 clock-output-names = "clk_ext2";
  74         };
  75
  76         clk_ext3: clock-ext3 {
  77                 compatible = "fixed-clock";
  78                 #clock-cells = <0>;
  79                 clock-frequency = <133000000>;
  80                 clock-output-names = "clk_ext3";
  81         };
  82
  83         clk_ext4: clock-ext4 {
  84                 compatible = "fixed-clock";
  85                 #clock-cells = <0>;
  86                 clock-frequency= <133000000>;
  87                 clock-output-names = "clk_ext4";
  88         };
  89
  90         cpus {
  91                 #address-cells = <1>;
  92                 #size-cells = <0>;
  93
  94                 A53_0: cpu@0 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a53";
  97                         reg = <0x0>;
  98                         clock-latency = <61036>; /* two CLK32 periods */
  99                         clocks = <&clk IMX8MQ_CLK_ARM>;
 100                         enable-method = "psci";
 101                         next-level-cache = <&A53_L2>;
 102                         operating-points-v2 = <&a53_opp_table>;
 103                         #cooling-cells = <2>;
 104                         nvmem-cells = <&cpu_speed_grade>;
 105                         nvmem-cell-names = "speed_grade";
 106                 };
 107
 108                 A53_1: cpu@1 {
 109                         device_type = "cpu";
 110                         compatible = "arm,cortex-a53";
 111                         reg = <0x1>;
 112                         clock-latency = <61036>; /* two CLK32 periods */
 113                         clocks = <&clk IMX8MQ_CLK_ARM>;
 114                         enable-method = "psci";
 115                         next-level-cache = <&A53_L2>;
 116                         operating-points-v2 = <&a53_opp_table>;
 117                         #cooling-cells = <2>;
 118                 };
 119
 120                 A53_2: cpu@2 {
 121                         device_type = "cpu";
 122                         compatible = "arm,cortex-a53";
 123                         reg = <0x2>;
 124                         clock-latency = <61036>; /* two CLK32 periods */
 125                         clocks = <&clk IMX8MQ_CLK_ARM>;
 126                         enable-method = "psci";
 127                         next-level-cache = <&A53_L2>;
 128                         operating-points-v2 = <&a53_opp_table>;
 129                         #cooling-cells = <2>;
 130                 };
 131
 132                 A53_3: cpu@3 {
 133                         device_type = "cpu";
 134                         compatible = "arm,cortex-a53";
 135                         reg = <0x3>;
 136                         clock-latency = <61036>; /* two CLK32 periods */
 137                         clocks = <&clk IMX8MQ_CLK_ARM>;
 138                         enable-method = "psci";
 139                         next-level-cache = <&A53_L2>;
 140                         operating-points-v2 = <&a53_opp_table>;
 141                         #cooling-cells = <2>;
 142                 };
 143
 144                 A53_L2: l2-cache0 {
 145                         compatible = "cache";
 146                 };
 147         };
 148
 149         a53_opp_table: opp-table {
 150                 compatible = "operating-points-v2";
 151                 opp-shared;
 152
 153                 opp-800000000 {
 154                         opp-hz = /bits/ 64 <800000000>;
 155                         opp-microvolt = <900000>;
 156                         /* Industrial only */
 157                         opp-supported-hw = <0xf>, <0x4>;
 158                         clock-latency-ns = <150000>;
 159                         opp-suspend;
 160                 };
 161
 162                 opp-1000000000 {
 163                         opp-hz = /bits/ 64 <1000000000>;
 164                         opp-microvolt = <900000>;
 165                         /* Consumer only */
 166                         opp-supported-hw = <0xe>, <0x3>;
 167                         clock-latency-ns = <150000>;
 168                         opp-suspend;
 169                 };
 170
 171                 opp-1300000000 {
 172                         opp-hz = /bits/ 64 <1300000000>;
 173                         opp-microvolt = <1000000>;
 174                         opp-supported-hw = <0xc>, <0x4>;
 175                         clock-latency-ns = <150000>;
 176                         opp-suspend;
 177                 };
 178
 179                 opp-1500000000 {
 180                         opp-hz = /bits/ 64 <1500000000>;
 181                         opp-microvolt = <1000000>;
 182                         opp-supported-hw = <0x8>, <0x3>;
 183                         clock-latency-ns = <150000>;
 184                         opp-suspend;
 185                 };
 186         };
 187
 188         pmu {
 189                 compatible = "arm,cortex-a53-pmu";
 190                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 191                 interrupt-parent = <&gic>;
 192                 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
 193         };
 194
 195         psci {
 196                 compatible = "arm,psci-1.0";
 197                 method = "smc";
 198         };
 199
 200         thermal-zones {
 201                 cpu_thermal: cpu-thermal {
 202                         polling-delay-passive = <250>;
 203                         polling-delay = <2000>;
 204                         thermal-sensors = <&tmu 0>;
 205
 206                         trips {
 207                                 cpu_alert: cpu-alert {
 208                                         temperature = <80000>;
 209                                         hysteresis = <2000>;
 210                                         type = "passive";
 211                                 };
 212
 213                                 cpu-crit {
 214                                         temperature = <90000>;
 215                                         hysteresis = <2000>;
 216                                         type = "critical";
 217                                 };
 218                         };
 219
 220                         cooling-maps {
 221                                 map0 {
 222                                         trip = <&cpu_alert>;
 223                                         cooling-device =
 224                                                 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 225                                                 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 226                                                 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 227                                                 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 228                                 };
 229                         };
 230                 };
 231
 232                 gpu-thermal {
 233                         polling-delay-passive = <250>;
 234                         polling-delay = <2000>;
 235                         thermal-sensors = <&tmu 1>;
 236
 237                         trips {
 238                                 gpu_alert: gpu-alert {
 239                                         temperature = <80000>;
 240                                         hysteresis = <2000>;
 241                                         type = "passive";
 242                                 };
 243
 244                                 gpu-crit {
 245                                         temperature = <90000>;
 246                                         hysteresis = <2000>;
 247                                         type = "critical";
 248                                 };
 249                         };
 250
 251                         cooling-maps {
 252                                 map0 {
 253                                         trip = <&gpu_alert>;
 254                                         cooling-device =
 255                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 256                                 };
 257                         };
 258                 };
 259
 260                 vpu-thermal {
 261                         polling-delay-passive = <250>;
 262                         polling-delay = <2000>;
 263                         thermal-sensors = <&tmu 2>;
 264
 265                         trips {
 266                                 vpu-crit {
 267                                         temperature = <90000>;
 268                                         hysteresis = <2000>;
 269                                         type = "critical";
 270                                 };
 271                         };
 272                 };
 273         };
 274
 275         timer {
 276                 compatible = "arm,armv8-timer";
 277                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
 278                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
 279                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
 280                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
 281                 interrupt-parent = <&gic>;
 282                 arm,no-tick-in-suspend;
 283         };
 284
 285         soc@0 {
 286                 compatible = "simple-bus";
 287                 #address-cells = <1>;
 288                 #size-cells = <1>;
 289                 ranges = <0x0 0x0 0x0 0x3e000000>;
 290                 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
 291
 292                 bus@30000000 { /* AIPS1 */
 293                         compatible = "fsl,aips-bus", "simple-bus";
 294                         reg = <0x301f0000 0x10000>;
 295                         #address-cells = <1>;
 296                         #size-cells = <1>;
 297                         ranges = <0x30000000 0x30000000 0x400000>;
 298
 299                         sai1: sai@30010000 {
 300                                 #sound-dai-cells = <0>;
 301                                 compatible = "fsl,imx8mq-sai";
 302                                 reg = <0x30010000 0x10000>;
 303                                 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 304                                 clocks = <&clk IMX8MQ_CLK_SAI1_IPG>,
 305                                          <&clk IMX8MQ_CLK_SAI1_ROOT>,
 306                                          <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
 307                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 308                                 dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>;
 309                                 dma-names = "rx", "tx";
 310                                 status = "disabled";
 311                         };
 312
 313                         sai6: sai@30030000 {
 314                                 #sound-dai-cells = <0>;
 315                                 compatible = "fsl,imx8mq-sai";
 316                                 reg = <0x30030000 0x10000>;
 317                                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 318                                 clocks = <&clk IMX8MQ_CLK_SAI6_IPG>,
 319                                          <&clk IMX8MQ_CLK_SAI6_ROOT>,
 320                                          <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
 321                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 322                                 dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>;
 323                                 dma-names = "rx", "tx";
 324                                 status = "disabled";
 325                         };
 326
 327                         sai5: sai@30040000 {
 328                                 #sound-dai-cells = <0>;
 329                                 compatible = "fsl,imx8mq-sai";
 330                                 reg = <0x30040000 0x10000>;
 331                                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 332                                 clocks = <&clk IMX8MQ_CLK_SAI5_IPG>,
 333                                          <&clk IMX8MQ_CLK_SAI5_ROOT>,
 334                                          <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
 335                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 336                                 dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>;
 337                                 dma-names = "rx", "tx";
 338                                 status = "disabled";
 339                         };
 340
 341                         sai4: sai@30050000 {
 342                                 #sound-dai-cells = <0>;
 343                                 compatible = "fsl,imx8mq-sai";
 344                                 reg = <0x30050000 0x10000>;
 345                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 346                                 clocks = <&clk IMX8MQ_CLK_SAI4_IPG>,
 347                                          <&clk IMX8MQ_CLK_SAI4_ROOT>,
 348                                          <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
 349                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 350                                 dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>;
 351                                 dma-names = "rx", "tx";
 352                                 status = "disabled";
 353                         };
 354
 355                         gpio1: gpio@30200000 {
 356                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 357                                 reg = <0x30200000 0x10000>;
 358                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 359                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 360                                 clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>;
 361                                 gpio-controller;
 362                                 #gpio-cells = <2>;
 363                                 interrupt-controller;
 364                                 #interrupt-cells = <2>;
 365                                 gpio-ranges = <&iomuxc 0 10 30>;
 366                         };
 367
 368                         gpio2: gpio@30210000 {
 369                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 370                                 reg = <0x30210000 0x10000>;
 371                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 372                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 373                                 clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>;
 374                                 gpio-controller;
 375                                 #gpio-cells = <2>;
 376                                 interrupt-controller;
 377                                 #interrupt-cells = <2>;
 378                                 gpio-ranges = <&iomuxc 0 40 21>;
 379                         };
 380
 381                         gpio3: gpio@30220000 {
 382                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 383                                 reg = <0x30220000 0x10000>;
 384                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 385                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 386                                 clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>;
 387                                 gpio-controller;
 388                                 #gpio-cells = <2>;
 389                                 interrupt-controller;
 390                                 #interrupt-cells = <2>;
 391                                 gpio-ranges = <&iomuxc 0 61 26>;
 392                         };
 393
 394                         gpio4: gpio@30230000 {
 395                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 396                                 reg = <0x30230000 0x10000>;
 397                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 398                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 399                                 clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>;
 400                                 gpio-controller;
 401                                 #gpio-cells = <2>;
 402                                 interrupt-controller;
 403                                 #interrupt-cells = <2>;
 404                                 gpio-ranges = <&iomuxc 0 87 32>;
 405                         };
 406
 407                         gpio5: gpio@30240000 {
 408                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 409                                 reg = <0x30240000 0x10000>;
 410                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 411                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 412                                 clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>;
 413                                 gpio-controller;
 414                                 #gpio-cells = <2>;
 415                                 interrupt-controller;
 416                                 #interrupt-cells = <2>;
 417                                 gpio-ranges = <&iomuxc 0 119 30>;
 418                         };
 419
 420                         tmu: tmu@30260000 {
 421                                 compatible = "fsl,imx8mq-tmu";
 422                                 reg = <0x30260000 0x10000>;
 423                                 interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 424                                 clocks = <&clk IMX8MQ_CLK_TMU_ROOT>;
 425                                 little-endian;
 426                                 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
 427                                 fsl,tmu-calibration = <0x00000000 0x00000023
 428                                                        0x00000001 0x00000029
 429                                                        0x00000002 0x0000002f
 430                                                        0x00000003 0x00000035
 431                                                        0x00000004 0x0000003d
 432                                                        0x00000005 0x00000043
 433                                                        0x00000006 0x0000004b
 434                                                        0x00000007 0x00000051
 435                                                        0x00000008 0x00000057
 436                                                        0x00000009 0x0000005f
 437                                                        0x0000000a 0x00000067
 438                                                        0x0000000b 0x0000006f
 439
 440                                                        0x00010000 0x0000001b
 441                                                        0x00010001 0x00000023
 442                                                        0x00010002 0x0000002b
 443                                                        0x00010003 0x00000033
 444                                                        0x00010004 0x0000003b
 445                                                        0x00010005 0x00000043
 446                                                        0x00010006 0x0000004b
 447                                                        0x00010007 0x00000055
 448                                                        0x00010008 0x0000005d
 449                                                        0x00010009 0x00000067
 450                                                        0x0001000a 0x00000070
 451
 452                                                        0x00020000 0x00000017
 453                                                        0x00020001 0x00000023
 454                                                        0x00020002 0x0000002d
 455                                                        0x00020003 0x00000037
 456                                                        0x00020004 0x00000041
 457                                                        0x00020005 0x0000004b
 458                                                        0x00020006 0x00000057
 459                                                        0x00020007 0x00000063
 460                                                        0x00020008 0x0000006f
 461
 462                                                        0x00030000 0x00000015
 463                                                        0x00030001 0x00000021
 464                                                        0x00030002 0x0000002d
 465                                                        0x00030003 0x00000039
 466                                                        0x00030004 0x00000045
 467                                                        0x00030005 0x00000053
 468                                                        0x00030006 0x0000005f
 469                                                        0x00030007 0x00000071>;
 470                                 #thermal-sensor-cells =  <1>;
 471                         };
 472
 473                         wdog1: watchdog@30280000 {
 474                                 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
 475                                 reg = <0x30280000 0x10000>;
 476                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 477                                 clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
 478                                 status = "disabled";
 479                         };
 480
 481                         wdog2: watchdog@30290000 {
 482                                 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
 483                                 reg = <0x30290000 0x10000>;
 484                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 485                                 clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
 486                                 status = "disabled";
 487                         };
 488
 489                         wdog3: watchdog@302a0000 {
 490                                 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
 491                                 reg = <0x302a0000 0x10000>;
 492                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 493                                 clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
 494                                 status = "disabled";
 495                         };
 496
 497                         sdma2: sdma@302c0000 {
 498                                 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
 499                                 reg = <0x302c0000 0x10000>;
 500                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 501                                 clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>,
 502                                          <&clk IMX8MQ_CLK_SDMA2_ROOT>;
 503                                 clock-names = "ipg", "ahb";
 504                                 #dma-cells = <3>;
 505                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
 506                         };
 507
 508                         lcdif: lcd-controller@30320000 {
 509                                 compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
 510                                 reg = <0x30320000 0x10000>;
 511                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 512                                 clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
 513                                 clock-names = "pix";
 514                                 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
 515                                                   <&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
 516                                                   <&clk IMX8MQ_CLK_LCDIF_PIXEL>,
 517                                                   <&clk IMX8MQ_VIDEO_PLL1>;
 518                                 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
 519                                                   <&clk IMX8MQ_VIDEO_PLL1>,
 520                                                   <&clk IMX8MQ_VIDEO_PLL1_OUT>;
 521                                 assigned-clock-rates = <0>, <0>, <0>, <594000000>;
 522                                 status = "disabled";
 523                         };
 524
 525                         iomuxc: pinctrl@30330000 {
 526                                 compatible = "fsl,imx8mq-iomuxc";
 527                                 reg = <0x30330000 0x10000>;
 528                         };
 529
 530                         iomuxc_gpr: syscon@30340000 {
 531                                 compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr",
 532                                              "syscon", "simple-mfd";
 533                                 reg = <0x30340000 0x10000>;
 534
 535                                 mux: mux-controller {
 536                                         compatible = "mmio-mux";
 537                                         #mux-control-cells = <1>;
 538                                         mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */
 539                                 };
 540                         };
 541
 542                         ocotp: ocotp-ctrl@30350000 {
 543                                 compatible = "fsl,imx8mq-ocotp", "syscon";
 544                                 reg = <0x30350000 0x10000>;
 545                                 clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
 546                                 #address-cells = <1>;
 547                                 #size-cells = <1>;
 548
 549                                 cpu_speed_grade: speed-grade@10 {
 550                                         reg = <0x10 4>;
 551                                 };
 552                         };
 553
 554                         anatop: syscon@30360000 {
 555                                 compatible = "fsl,imx8mq-anatop", "syscon";
 556                                 reg = <0x30360000 0x10000>;
 557                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 558                         };
 559
 560                         snvs: snvs@30370000 {
 561                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 562                                 reg = <0x30370000 0x10000>;
 563
 564                                 snvs_rtc: snvs-rtc-lp{
 565                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 566                                         regmap =<&snvs>;
 567                                         offset = <0x34>;
 568                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 569                                                 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 570                                         clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
 571                                         clock-names = "snvs-rtc";
 572                                 };
 573
 574                                 snvs_pwrkey: snvs-powerkey {
 575                                         compatible = "fsl,sec-v4.0-pwrkey";
 576                                         regmap = <&snvs>;
 577                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 578                                         clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
 579                                         clock-names = "snvs-pwrkey";
 580                                         linux,keycode = <KEY_POWER>;
 581                                         wakeup-source;
 582                                         status = "disabled";
 583                                 };
 584                         };
 585
 586                         clk: clock-controller@30380000 {
 587                                 compatible = "fsl,imx8mq-ccm";
 588                                 reg = <0x30380000 0x10000>;
 589                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 590                                              <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 591                                 #clock-cells = <1>;
 592                                 clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
 593                                          <&clk_ext1>, <&clk_ext2>,
 594                                          <&clk_ext3>, <&clk_ext4>;
 595                                 clock-names = "ckil", "osc_25m", "osc_27m",
 596                                               "clk_ext1", "clk_ext2",
 597                                               "clk_ext3", "clk_ext4";
 598                                 assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>,
 599                                                   <&clk IMX8MQ_CLK_A53_CORE>,
 600                                                   <&clk IMX8MQ_CLK_NOC>;
 601                                 assigned-clock-rates = <0>, <0>,
 602                                                        <800000000>;
 603                                 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
 604                                                          <&clk IMX8MQ_ARM_PLL_OUT>;
 605                         };
 606
 607                         src: reset-controller@30390000 {
 608                                 compatible = "fsl,imx8mq-src", "syscon";
 609                                 reg = <0x30390000 0x10000>;
 610                                 #reset-cells = <1>;
 611                         };
 612
 613                         gpc: gpc@303a0000 {
 614                                 compatible = "fsl,imx8mq-gpc";
 615                                 reg = <0x303a0000 0x10000>;
 616                                 interrupt-parent = <&gic>;
 617                                 interrupt-controller;
 618                                 #interrupt-cells = <3>;
 619
 620                                 pgc {
 621                                         #address-cells = <1>;
 622                                         #size-cells = <0>;
 623
 624                                         pgc_mipi: power-domain@0 {
 625                                                 #power-domain-cells = <0>;
 626                                                 reg = <IMX8M_POWER_DOMAIN_MIPI>;
 627                                         };
 628
 629                                         /*
 630                                          * As per comment in ATF source code:
 631                                          *
 632                                          * PCIE1 and PCIE2 share the
 633                                          * same reset signal, if we
 634                                          * power down PCIE2, PCIE1
 635                                          * will be held in reset too.
 636                                          *
 637                                          * So instead of creating two
 638                                          * separate power domains for
 639                                          * PCIE1 and PCIE2 we create a
 640                                          * link between both and use
 641                                          * it as a shared PCIE power
 642                                          * domain.
 643                                          */
 644                                         pgc_pcie: power-domain@1 {
 645                                                 #power-domain-cells = <0>;
 646                                                 reg = <IMX8M_POWER_DOMAIN_PCIE1>;
 647                                                 power-domains = <&pgc_pcie2>;
 648                                         };
 649
 650                                         pgc_otg1: power-domain@2 {
 651                                                 #power-domain-cells = <0>;
 652                                                 reg = <IMX8M_POWER_DOMAIN_USB_OTG1>;
 653                                         };
 654
 655                                         pgc_otg2: power-domain@3 {
 656                                                 #power-domain-cells = <0>;
 657                                                 reg = <IMX8M_POWER_DOMAIN_USB_OTG2>;
 658                                         };
 659
 660                                         pgc_ddr1: power-domain@4 {
 661                                                 #power-domain-cells = <0>;
 662                                                 reg = <IMX8M_POWER_DOMAIN_DDR1>;
 663                                         };
 664
 665                                         pgc_gpu: power-domain@5 {
 666                                                 #power-domain-cells = <0>;
 667                                                 reg = <IMX8M_POWER_DOMAIN_GPU>;
 668                                                 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
 669                                                          <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
 670                                                          <&clk IMX8MQ_CLK_GPU_AXI>,
 671                                                          <&clk IMX8MQ_CLK_GPU_AHB>;
 672                                         };
 673
 674                                         pgc_vpu: power-domain@6 {
 675                                                 #power-domain-cells = <0>;
 676                                                 reg = <IMX8M_POWER_DOMAIN_VPU>;
 677                                         };
 678
 679                                         pgc_disp: power-domain@7 {
 680                                                 #power-domain-cells = <0>;
 681                                                 reg = <IMX8M_POWER_DOMAIN_DISP>;
 682                                         };
 683
 684                                         pgc_mipi_csi1: power-domain@8 {
 685                                                 #power-domain-cells = <0>;
 686                                                 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>;
 687                                         };
 688
 689                                         pgc_mipi_csi2: power-domain@9 {
 690                                                 #power-domain-cells = <0>;
 691                                                 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>;
 692                                         };
 693
 694                                         pgc_pcie2: power-domain@a {
 695                                                 #power-domain-cells = <0>;
 696                                                 reg = <IMX8M_POWER_DOMAIN_PCIE2>;
 697                                         };
 698                                 };
 699                         };
 700                 };
 701
 702                 bus@30400000 { /* AIPS2 */
 703                         compatible = "fsl,aips-bus", "simple-bus";
 704                         reg = <0x305f0000 0x10000>;
 705                         #address-cells = <1>;
 706                         #size-cells = <1>;
 707                         ranges = <0x30400000 0x30400000 0x400000>;
 708
 709                         pwm1: pwm@30660000 {
 710                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 711                                 reg = <0x30660000 0x10000>;
 712                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 713                                 clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>,
 714                                          <&clk IMX8MQ_CLK_PWM1_ROOT>;
 715                                 clock-names = "ipg", "per";
 716                                 #pwm-cells = <2>;
 717                                 status = "disabled";
 718                         };
 719
 720                         pwm2: pwm@30670000 {
 721                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 722                                 reg = <0x30670000 0x10000>;
 723                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 724                                 clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
 725                                          <&clk IMX8MQ_CLK_PWM2_ROOT>;
 726                                 clock-names = "ipg", "per";
 727                                 #pwm-cells = <2>;
 728                                 status = "disabled";
 729                         };
 730
 731                         pwm3: pwm@30680000 {
 732                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 733                                 reg = <0x30680000 0x10000>;
 734                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 735                                 clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>,
 736                                          <&clk IMX8MQ_CLK_PWM3_ROOT>;
 737                                 clock-names = "ipg", "per";
 738                                 #pwm-cells = <2>;
 739                                 status = "disabled";
 740                         };
 741
 742                         pwm4: pwm@30690000 {
 743                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 744                                 reg = <0x30690000 0x10000>;
 745                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 746                                 clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>,
 747                                          <&clk IMX8MQ_CLK_PWM4_ROOT>;
 748                                 clock-names = "ipg", "per";
 749                                 #pwm-cells = <2>;
 750                                 status = "disabled";
 751                         };
 752
 753                         system_counter: timer@306a0000 {
 754                                 compatible = "nxp,sysctr-timer";
 755                                 reg = <0x306a0000 0x20000>;
 756                                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 757                                 clocks = <&osc_25m>;
 758                                 clock-names = "per";
 759                         };
 760                 };
 761
 762                 bus@30800000 { /* AIPS3 */
 763                         compatible = "fsl,aips-bus", "simple-bus";
 764                         reg = <0x309f0000 0x10000>;
 765                         #address-cells = <1>;
 766                         #size-cells = <1>;
 767                         ranges = <0x30800000 0x30800000 0x400000>,
 768                                  <0x08000000 0x08000000 0x10000000>;
 769
 770                         ecspi1: spi@30820000 {
 771                                 #address-cells = <1>;
 772                                 #size-cells = <0>;
 773                                 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
 774                                 reg = <0x30820000 0x10000>;
 775                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 776                                 clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
 777                                          <&clk IMX8MQ_CLK_ECSPI1_ROOT>;
 778                                 clock-names = "ipg", "per";
 779                                 status = "disabled";
 780                         };
 781
 782                         ecspi2: spi@30830000 {
 783                                 #address-cells = <1>;
 784                                 #size-cells = <0>;
 785                                 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
 786                                 reg = <0x30830000 0x10000>;
 787                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 788                                 clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>,
 789                                          <&clk IMX8MQ_CLK_ECSPI2_ROOT>;
 790                                 clock-names = "ipg", "per";
 791                                 status = "disabled";
 792                         };
 793
 794                         ecspi3: spi@30840000 {
 795                                 #address-cells = <1>;
 796                                 #size-cells = <0>;
 797                                 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
 798                                 reg = <0x30840000 0x10000>;
 799                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 800                                 clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>,
 801                                          <&clk IMX8MQ_CLK_ECSPI3_ROOT>;
 802                                 clock-names = "ipg", "per";
 803                                 status = "disabled";
 804                         };
 805
 806                         uart1: serial@30860000 {
 807                                 compatible = "fsl,imx8mq-uart",
 808                                              "fsl,imx6q-uart";
 809                                 reg = <0x30860000 0x10000>;
 810                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 811                                 clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
 812                                          <&clk IMX8MQ_CLK_UART1_ROOT>;
 813                                 clock-names = "ipg", "per";
 814                                 status = "disabled";
 815                         };
 816
 817                         uart3: serial@30880000 {
 818                                 compatible = "fsl,imx8mq-uart",
 819                                              "fsl,imx6q-uart";
 820                                 reg = <0x30880000 0x10000>;
 821                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 822                                 clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
 823                                          <&clk IMX8MQ_CLK_UART3_ROOT>;
 824                                 clock-names = "ipg", "per";
 825                                 status = "disabled";
 826                         };
 827
 828                         uart2: serial@30890000 {
 829                                 compatible = "fsl,imx8mq-uart",
 830                                              "fsl,imx6q-uart";
 831                                 reg = <0x30890000 0x10000>;
 832                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 833                                 clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
 834                                          <&clk IMX8MQ_CLK_UART2_ROOT>;
 835                                 clock-names = "ipg", "per";
 836                                 status = "disabled";
 837                         };
 838
 839                         sai2: sai@308b0000 {
 840                                 #sound-dai-cells = <0>;
 841                                 compatible = "fsl,imx8mq-sai";
 842                                 reg = <0x308b0000 0x10000>;
 843                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 844                                 clocks = <&clk IMX8MQ_CLK_SAI2_IPG>,
 845                                          <&clk IMX8MQ_CLK_SAI2_ROOT>,
 846                                          <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
 847                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 848                                 dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;
 849                                 dma-names = "rx", "tx";
 850                                 status = "disabled";
 851                         };
 852
 853                         sai3: sai@308c0000 {
 854                                 #sound-dai-cells = <0>;
 855                                 compatible = "fsl,imx8mq-sai";
 856                                 reg = <0x308c0000 0x10000>;
 857                                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 858                                 clocks = <&clk IMX8MQ_CLK_SAI3_IPG>,
 859                                          <&clk IMX8MQ_CLK_SAI3_ROOT>,
 860                                          <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
 861                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 862                                 dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>;
 863                                 dma-names = "rx", "tx";
 864                                 status = "disabled";
 865                         };
 866
 867                         crypto: crypto@30900000 {
 868                                 compatible = "fsl,sec-v4.0";
 869                                 #address-cells = <1>;
 870                                 #size-cells = <1>;
 871                                 reg = <0x30900000 0x40000>;
 872                                 ranges = <0 0x30900000 0x40000>;
 873                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 874                                 clocks = <&clk IMX8MQ_CLK_AHB>,
 875                                          <&clk IMX8MQ_CLK_IPG_ROOT>;
 876                                 clock-names = "aclk", "ipg";
 877
 878                                 sec_jr0: jr@1000 {
 879                                         compatible = "fsl,sec-v4.0-job-ring";
 880                                         reg = <0x1000 0x1000>;
 881                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 882                                 };
 883
 884                                 sec_jr1: jr@2000 {
 885                                         compatible = "fsl,sec-v4.0-job-ring";
 886                                         reg = <0x2000 0x1000>;
 887                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 888                                 };
 889
 890                                 sec_jr2: jr@3000 {
 891                                         compatible = "fsl,sec-v4.0-job-ring";
 892                                         reg = <0x3000 0x1000>;
 893                                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 894                                 };
 895                         };
 896
 897                         dphy: dphy@30a00300 {
 898                                 compatible = "fsl,imx8mq-mipi-dphy";
 899                                 reg = <0x30a00300 0x100>;
 900                                 clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
 901                                 clock-names = "phy_ref";
 902                                 assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
 903                                 assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
 904                                 assigned-clock-rates = <24000000>;
 905                                 #phy-cells = <0>;
 906                                 power-domains = <&pgc_mipi>;
 907                                 status = "disabled";
 908                         };
 909
 910                         i2c1: i2c@30a20000 {
 911                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
 912                                 reg = <0x30a20000 0x10000>;
 913                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 914                                 clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
 915                                 #address-cells = <1>;
 916                                 #size-cells = <0>;
 917                                 status = "disabled";
 918                         };
 919
 920                         i2c2: i2c@30a30000 {
 921                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
 922                                 reg = <0x30a30000 0x10000>;
 923                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 924                                 clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
 925                                 #address-cells = <1>;
 926                                 #size-cells = <0>;
 927                                 status = "disabled";
 928                         };
 929
 930                         i2c3: i2c@30a40000 {
 931                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
 932                                 reg = <0x30a40000 0x10000>;
 933                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 934                                 clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
 935                                 #address-cells = <1>;
 936                                 #size-cells = <0>;
 937                                 status = "disabled";
 938                         };
 939
 940                         i2c4: i2c@30a50000 {
 941                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
 942                                 reg = <0x30a50000 0x10000>;
 943                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 944                                 clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
 945                                 #address-cells = <1>;
 946                                 #size-cells = <0>;
 947                                 status = "disabled";
 948                         };
 949
 950                         uart4: serial@30a60000 {
 951                                 compatible = "fsl,imx8mq-uart",
 952                                              "fsl,imx6q-uart";
 953                                 reg = <0x30a60000 0x10000>;
 954                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 955                                 clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
 956                                          <&clk IMX8MQ_CLK_UART4_ROOT>;
 957                                 clock-names = "ipg", "per";
 958                                 status = "disabled";
 959                         };
 960
 961                         usdhc1: mmc@30b40000 {
 962                                 compatible = "fsl,imx8mq-usdhc",
 963                                              "fsl,imx7d-usdhc";
 964                                 reg = <0x30b40000 0x10000>;
 965                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 966                                 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
 967                                          <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
 968                                          <&clk IMX8MQ_CLK_USDHC1_ROOT>;
 969                                 clock-names = "ipg", "ahb", "per";
 970                                 fsl,tuning-start-tap = <20>;
 971                                 fsl,tuning-step = <2>;
 972                                 bus-width = <4>;
 973                                 status = "disabled";
 974                         };
 975
 976                         usdhc2: mmc@30b50000 {
 977                                 compatible = "fsl,imx8mq-usdhc",
 978                                              "fsl,imx7d-usdhc";
 979                                 reg = <0x30b50000 0x10000>;
 980                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 981                                 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
 982                                          <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
 983                                          <&clk IMX8MQ_CLK_USDHC2_ROOT>;
 984                                 clock-names = "ipg", "ahb", "per";
 985                                 fsl,tuning-start-tap = <20>;
 986                                 fsl,tuning-step = <2>;
 987                                 bus-width = <4>;
 988                                 status = "disabled";
 989                         };
 990
 991                         qspi0: spi@30bb0000 {
 992                                 #address-cells = <1>;
 993                                 #size-cells = <0>;
 994                                 compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi";
 995                                 reg = <0x30bb0000 0x10000>,
 996                                       <0x08000000 0x10000000>;
 997                                 reg-names = "QuadSPI", "QuadSPI-memory";
 998                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 999                                 clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
1000                                          <&clk IMX8MQ_CLK_QSPI_ROOT>;
1001                                 clock-names = "qspi_en", "qspi";
1002                                 status = "disabled";
1003                         };
1004
1005                         sdma1: sdma@30bd0000 {
1006                                 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
1007                                 reg = <0x30bd0000 0x10000>;
1008                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1009                                 clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
1010                                          <&clk IMX8MQ_CLK_AHB>;
1011                                 clock-names = "ipg", "ahb";
1012                                 #dma-cells = <3>;
1013                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1014                         };
1015
1016                         fec1: ethernet@30be0000 {
1017                                 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1018                                 reg = <0x30be0000 0x10000>;
1019                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1020                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1021                                              <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1022                                 clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
1023                                          <&clk IMX8MQ_CLK_ENET1_ROOT>,
1024                                          <&clk IMX8MQ_CLK_ENET_TIMER>,
1025                                          <&clk IMX8MQ_CLK_ENET_REF>,
1026                                          <&clk IMX8MQ_CLK_ENET_PHY_REF>;
1027                                 clock-names = "ipg", "ahb", "ptp",
1028                                               "enet_clk_ref", "enet_out";
1029                                 fsl,num-tx-queues = <3>;
1030                                 fsl,num-rx-queues = <3>;
1031                                 status = "disabled";
1032                         };
1033                 };
1034
1035                 bus@32c00000 { /* AIPS4 */
1036                         compatible = "fsl,aips-bus", "simple-bus";
1037                         reg = <0x32df0000 0x10000>;
1038                         #address-cells = <1>;
1039                         #size-cells = <1>;
1040                         ranges = <0x32c00000 0x32c00000 0x400000>;
1041
1042                         irqsteer: interrupt-controller@32e2d000 {
1043                                 compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
1044                                 reg = <0x32e2d000 0x1000>;
1045                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1046                                 clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
1047                                 clock-names = "ipg";
1048                                 fsl,channel = <0>;
1049                                 fsl,num-irqs = <64>;
1050                                 interrupt-controller;
1051                                 #interrupt-cells = <1>;
1052                         };
1053                 };
1054
1055                 gpu: gpu@38000000 {
1056                         compatible = "vivante,gc";
1057                         reg = <0x38000000 0x40000>;
1058                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1059                         clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
1060                                  <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
1061                                  <&clk IMX8MQ_CLK_GPU_AXI>,
1062                                  <&clk IMX8MQ_CLK_GPU_AHB>;
1063                         clock-names = "core", "shader", "bus", "reg";
1064                         #cooling-cells = <2>;
1065                         assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
1066                                           <&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
1067                                           <&clk IMX8MQ_CLK_GPU_AXI>,
1068                                           <&clk IMX8MQ_CLK_GPU_AHB>,
1069                                           <&clk IMX8MQ_GPU_PLL_BYPASS>;
1070                         assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
1071                                                  <&clk IMX8MQ_GPU_PLL_OUT>,
1072                                                  <&clk IMX8MQ_GPU_PLL_OUT>,
1073                                                  <&clk IMX8MQ_GPU_PLL_OUT>,
1074                                                  <&clk IMX8MQ_GPU_PLL>;
1075                         assigned-clock-rates = <800000000>, <800000000>,
1076                                                <800000000>, <800000000>, <0>;
1077                         power-domains = <&pgc_gpu>;
1078                 };
1079
1080                 usb_dwc3_0: usb@38100000 {
1081                         compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
1082                         reg = <0x38100000 0x10000>;
1083                         clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>,
1084                                  <&clk IMX8MQ_CLK_USB_CORE_REF>,
1085                                  <&clk IMX8MQ_CLK_32K>;
1086                         clock-names = "bus_early", "ref", "suspend";
1087                         assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
1088                                           <&clk IMX8MQ_CLK_USB_CORE_REF>;
1089                         assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
1090                                                  <&clk IMX8MQ_SYS1_PLL_100M>;
1091                         assigned-clock-rates = <500000000>, <100000000>;
1092                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1093                         phys = <&usb3_phy0>, <&usb3_phy0>;
1094                         phy-names = "usb2-phy", "usb3-phy";
1095                         power-domains = <&pgc_otg1>;
1096                         usb3-resume-missing-cas;
1097                         status = "disabled";
1098                 };
1099
1100                 usb3_phy0: usb-phy@381f0040 {
1101                         compatible = "fsl,imx8mq-usb-phy";
1102                         reg = <0x381f0040 0x40>;
1103                         clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
1104                         clock-names = "phy";
1105                         assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1106                         assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1107                         assigned-clock-rates = <100000000>;
1108                         #phy-cells = <0>;
1109                         status = "disabled";
1110                 };
1111
1112                 usb_dwc3_1: usb@38200000 {
1113                         compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
1114                         reg = <0x38200000 0x10000>;
1115                         clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>,
1116                                  <&clk IMX8MQ_CLK_USB_CORE_REF>,
1117                                  <&clk IMX8MQ_CLK_32K>;
1118                         clock-names = "bus_early", "ref", "suspend";
1119                         assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
1120                                           <&clk IMX8MQ_CLK_USB_CORE_REF>;
1121                         assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
1122                                                  <&clk IMX8MQ_SYS1_PLL_100M>;
1123                         assigned-clock-rates = <500000000>, <100000000>;
1124                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1125                         phys = <&usb3_phy1>, <&usb3_phy1>;
1126                         phy-names = "usb2-phy", "usb3-phy";
1127                         power-domains = <&pgc_otg2>;
1128                         usb3-resume-missing-cas;
1129                         status = "disabled";
1130                 };
1131
1132                 usb3_phy1: usb-phy@382f0040 {
1133                         compatible = "fsl,imx8mq-usb-phy";
1134                         reg = <0x382f0040 0x40>;
1135                         clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
1136                         clock-names = "phy";
1137                         assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1138                         assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1139                         assigned-clock-rates = <100000000>;
1140                         #phy-cells = <0>;
1141                         status = "disabled";
1142                 };
1143
1144                 pcie0: pcie@33800000 {
1145                         compatible = "fsl,imx8mq-pcie";
1146                         reg = <0x33800000 0x400000>,
1147                               <0x1ff00000 0x80000>;
1148                         reg-names = "dbi", "config";
1149                         #address-cells = <3>;
1150                         #size-cells = <2>;
1151                         device_type = "pci";
1152                         bus-range = <0x00 0xff>;
1153                         ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
1154                                   0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1155                         num-lanes = <1>;
1156                         num-viewport = <4>;
1157                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1158                         interrupt-names = "msi";
1159                         #interrupt-cells = <1>;
1160                         interrupt-map-mask = <0 0 0 0x7>;
1161                         interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1162                                         <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1163                                         <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1164                                         <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1165                         fsl,max-link-speed = <2>;
1166                         power-domains = <&pgc_pcie>;
1167                         resets = <&src IMX8MQ_RESET_PCIEPHY>,
1168                                  <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
1169                                  <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
1170                         reset-names = "pciephy", "apps", "turnoff";
1171                         status = "disabled";
1172                 };
1173
1174                 pcie1: pcie@33c00000 {
1175                         compatible = "fsl,imx8mq-pcie";
1176                         reg = <0x33c00000 0x400000>,
1177                               <0x27f00000 0x80000>;
1178                         reg-names = "dbi", "config";
1179                         #address-cells = <3>;
1180                         #size-cells = <2>;
1181                         device_type = "pci";
1182                         ranges =  <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */
1183                                    0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
1184                         num-lanes = <1>;
1185                         num-viewport = <4>;
1186                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1187                         interrupt-names = "msi";
1188                         #interrupt-cells = <1>;
1189                         interrupt-map-mask = <0 0 0 0x7>;
1190                         interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
1191                                         <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
1192                                         <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1193                                         <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1194                         fsl,max-link-speed = <2>;
1195                         power-domains = <&pgc_pcie>;
1196                         resets = <&src IMX8MQ_RESET_PCIEPHY2>,
1197                                  <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
1198                                  <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
1199                         reset-names = "pciephy", "apps", "turnoff";
1200                         status = "disabled";
1201                 };
1202
1203                 gic: interrupt-controller@38800000 {
1204                         compatible = "arm,gic-v3";
1205                         reg = <0x38800000 0x10000>,     /* GIC Dist */
1206                               <0x38880000 0xc0000>,     /* GICR */
1207                               <0x31000000 0x2000>,      /* GICC */
1208                               <0x31010000 0x2000>,      /* GICV */
1209                               <0x31020000 0x2000>;      /* GICH */
1210                         #interrupt-cells = <3>;
1211                         interrupt-controller;
1212                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1213                         interrupt-parent = <&gic>;
1214                 };
1215
1216                 ddrc: memory-controller@3d400000 {
1217                         compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc";
1218                         reg = <0x3d400000 0x400000>;
1219                         clock-names = "core", "pll", "alt", "apb";
1220                         clocks = <&clk IMX8MQ_CLK_DRAM_CORE>,
1221                                  <&clk IMX8MQ_DRAM_PLL_OUT>,
1222                                  <&clk IMX8MQ_CLK_DRAM_ALT>,
1223                                  <&clk IMX8MQ_CLK_DRAM_APB>;
1224                 };
1225
1226                 ddr-pmu@3d800000 {
1227                         compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu";
1228                         reg = <0x3d800000 0x400000>;
1229                         interrupt-parent = <&gic>;
1230                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1231                 };
1232         };
1233 };