arch/arm64/boot/dts/freescale/imx8mq.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2017 NXP
   4  * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
   5  */
   6
   7 #include <dt-bindings/clock/imx8mq-clock.h>
   8 #include <dt-bindings/power/imx8mq-power.h>
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include "imx8mq-pinfunc.h"
  12
  13 / {
  14         /* This should really be the GPC, but we need a driver for this first */
  15         interrupt-parent = <&gic>;
  16
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         aliases {
  21                 i2c0 = &i2c1;
  22                 i2c1 = &i2c2;
  23                 i2c2 = &i2c3;
  24                 i2c3 = &i2c4;
  25                 serial0 = &uart1;
  26                 serial1 = &uart2;
  27                 serial2 = &uart3;
  28                 serial3 = &uart4;
  29         };
  30
  31         ckil: clock-ckil {
  32                 compatible = "fixed-clock";
  33                 #clock-cells = <0>;
  34                 clock-frequency = <32768>;
  35                 clock-output-names = "ckil";
  36         };
  37
  38         osc_25m: clock-osc-25m {
  39                 compatible = "fixed-clock";
  40                 #clock-cells = <0>;
  41                 clock-frequency = <25000000>;
  42                 clock-output-names = "osc_25m";
  43         };
  44
  45         osc_27m: clock-osc-27m {
  46                 compatible = "fixed-clock";
  47                 #clock-cells = <0>;
  48                 clock-frequency = <27000000>;
  49                 clock-output-names = "osc_27m";
  50         };
  51
  52         clk_ext1: clock-ext1 {
  53                 compatible = "fixed-clock";
  54                 #clock-cells = <0>;
  55                 clock-frequency = <133000000>;
  56                 clock-output-names = "clk_ext1";
  57         };
  58
  59         clk_ext2: clock-ext2 {
  60                 compatible = "fixed-clock";
  61                 #clock-cells = <0>;
  62                 clock-frequency = <133000000>;
  63                 clock-output-names = "clk_ext2";
  64         };
  65
  66         clk_ext3: clock-ext3 {
  67                 compatible = "fixed-clock";
  68                 #clock-cells = <0>;
  69                 clock-frequency = <133000000>;
  70                 clock-output-names = "clk_ext3";
  71         };
  72
  73         clk_ext4: clock-ext4 {
  74                 compatible = "fixed-clock";
  75                 #clock-cells = <0>;
  76                 clock-frequency= <133000000>;
  77                 clock-output-names = "clk_ext4";
  78         };
  79
  80         cpus {
  81                 #address-cells = <1>;
  82                 #size-cells = <0>;
  83
  84                 A53_0: cpu@0 {
  85                         device_type = "cpu";
  86                         compatible = "arm,cortex-a53";
  87                         reg = <0x0>;
  88                         enable-method = "psci";
  89                         next-level-cache = <&A53_L2>;
  90                 };
  91
  92                 A53_1: cpu@1 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a53";
  95                         reg = <0x1>;
  96                         enable-method = "psci";
  97                         next-level-cache = <&A53_L2>;
  98                 };
  99
 100                 A53_2: cpu@2 {
 101                         device_type = "cpu";
 102                         compatible = "arm,cortex-a53";
 103                         reg = <0x2>;
 104                         enable-method = "psci";
 105                         next-level-cache = <&A53_L2>;
 106                 };
 107
 108                 A53_3: cpu@3 {
 109                         device_type = "cpu";
 110                         compatible = "arm,cortex-a53";
 111                         reg = <0x3>;
 112                         enable-method = "psci";
 113                         next-level-cache = <&A53_L2>;
 114                 };
 115
 116                 A53_L2: l2-cache0 {
 117                         compatible = "cache";
 118                 };
 119         };
 120
 121         psci {
 122                 compatible = "arm,psci-1.0";
 123                 method = "smc";
 124         };
 125
 126         timer {
 127                 compatible = "arm,armv8-timer";
 128                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
 129                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
 130                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
 131                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
 132                 interrupt-parent = <&gic>;
 133                 arm,no-tick-in-suspend;
 134         };
 135
 136         soc@0 {
 137                 compatible = "simple-bus";
 138                 #address-cells = <1>;
 139                 #size-cells = <1>;
 140                 ranges = <0x0 0x0 0x0 0x3e000000>;
 141
 142                 bus@30000000 { /* AIPS1 */
 143                         compatible = "fsl,imx8mq-aips-bus", "simple-bus";
 144                         #address-cells = <1>;
 145                         #size-cells = <1>;
 146                         ranges = <0x30000000 0x30000000 0x400000>;
 147
 148                         gpio1: gpio@30200000 {
 149                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 150                                 reg = <0x30200000 0x10000>;
 151                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 152                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 153                                 gpio-controller;
 154                                 #gpio-cells = <2>;
 155                                 interrupt-controller;
 156                                 #interrupt-cells = <2>;
 157                         };
 158
 159                         gpio2: gpio@30210000 {
 160                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 161                                 reg = <0x30210000 0x10000>;
 162                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 163                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 164                                 gpio-controller;
 165                                 #gpio-cells = <2>;
 166                                 interrupt-controller;
 167                                 #interrupt-cells = <2>;
 168                         };
 169
 170                         gpio3: gpio@30220000 {
 171                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 172                                 reg = <0x30220000 0x10000>;
 173                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 174                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 175                                 gpio-controller;
 176                                 #gpio-cells = <2>;
 177                                 interrupt-controller;
 178                                 #interrupt-cells = <2>;
 179                         };
 180
 181                         gpio4: gpio@30230000 {
 182                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 183                                 reg = <0x30230000 0x10000>;
 184                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 185                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 186                                 gpio-controller;
 187                                 #gpio-cells = <2>;
 188                                 interrupt-controller;
 189                                 #interrupt-cells = <2>;
 190                         };
 191
 192                         gpio5: gpio@30240000 {
 193                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 194                                 reg = <0x30240000 0x10000>;
 195                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 196                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 197                                 gpio-controller;
 198                                 #gpio-cells = <2>;
 199                                 interrupt-controller;
 200                                 #interrupt-cells = <2>;
 201                         };
 202
 203                         wdog1: watchdog@30280000 {
 204                                 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
 205                                 reg = <0x30280000 0x10000>;
 206                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 207                                 clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
 208                                 status = "disabled";
 209                         };
 210
 211                         wdog2: watchdog@30290000 {
 212                                 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
 213                                 reg = <0x30290000 0x10000>;
 214                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 215                                 clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
 216                                 status = "disabled";
 217                         };
 218
 219                         wdog3: watchdog@302a0000 {
 220                                 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
 221                                 reg = <0x302a0000 0x10000>;
 222                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 223                                 clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
 224                                 status = "disabled";
 225                         };
 226
 227                         iomuxc: iomuxc@30330000 {
 228                                 compatible = "fsl,imx8mq-iomuxc";
 229                                 reg = <0x30330000 0x10000>;
 230                         };
 231
 232                         iomuxc_gpr: syscon@30340000 {
 233                                 compatible = "fsl,imx8mq-iomuxc-gpr", "syscon";
 234                                 reg = <0x30340000 0x10000>;
 235                         };
 236
 237                         anatop: syscon@30360000 {
 238                                 compatible = "fsl,imx8mq-anatop", "syscon";
 239                                 reg = <0x30360000 0x10000>;
 240                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 241                         };
 242
 243                         clk: clock-controller@30380000 {
 244                                 compatible = "fsl,imx8mq-ccm";
 245                                 reg = <0x30380000 0x10000>;
 246                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 247                                              <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 248                                 #clock-cells = <1>;
 249                                 clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
 250                                          <&clk_ext1>, <&clk_ext2>,
 251                                          <&clk_ext3>, <&clk_ext4>;
 252                                 clock-names = "ckil", "osc_25m", "osc_27m",
 253                                               "clk_ext1", "clk_ext2",
 254                                               "clk_ext3", "clk_ext4";
 255                         };
 256
 257                         gpc: gpc@303a0000 {
 258                                 compatible = "fsl,imx8mq-gpc";
 259                                 reg = <0x303a0000 0x10000>;
 260
 261                                 pgc {
 262                                         #address-cells = <1>;
 263                                         #size-cells = <0>;
 264
 265                                         pgc_mipi: power-domain@0 {
 266                                                 #power-domain-cells = <0>;
 267                                                 reg = <IMX8M_POWER_DOMAIN_MIPI>;
 268                                         };
 269
 270                                         pgc_pcie1: power-domain@1 {
 271                                                 #power-domain-cells = <0>;
 272                                                 reg = <IMX8M_POWER_DOMAIN_PCIE1>;
 273                                         };
 274
 275                                         pgc_otg1: power-domain@2 {
 276                                                 #power-domain-cells = <0>;
 277                                                 reg = <IMX8M_POWER_DOMAIN_USB_OTG1>;
 278                                         };
 279
 280                                         pgc_otg2: power-domain@3 {
 281                                                 #power-domain-cells = <0>;
 282                                                 reg = <IMX8M_POWER_DOMAIN_USB_OTG2>;
 283                                         };
 284
 285                                         pgc_ddr1: power-domain@4 {
 286                                                 #power-domain-cells = <0>;
 287                                                 reg = <IMX8M_POWER_DOMAIN_DDR1>;
 288                                         };
 289
 290                                         pgc_gpu: power-domain@5 {
 291                                                 #power-domain-cells = <0>;
 292                                                 reg = <IMX8M_POWER_DOMAIN_GPU>;
 293                                                 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
 294                                                          <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
 295                                                          <&clk IMX8MQ_CLK_GPU_AXI>,
 296                                                          <&clk IMX8MQ_CLK_GPU_AHB>;
 297                                         };
 298
 299                                         pgc_vpu: power-domain@6 {
 300                                                 #power-domain-cells = <0>;
 301                                                 reg = <IMX8M_POWER_DOMAIN_VPU>;
 302                                         };
 303
 304                                         pgc_disp: power-domain@7 {
 305                                                 #power-domain-cells = <0>;
 306                                                 reg = <IMX8M_POWER_DOMAIN_DISP>;
 307                                         };
 308
 309                                         pgc_mipi_csi1: power-domain@8 {
 310                                                 #power-domain-cells = <0>;
 311                                                 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>;
 312                                         };
 313
 314                                         pgc_mipi_csi2: power-domain@9 {
 315                                                 #power-domain-cells = <0>;
 316                                                 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>;
 317                                         };
 318
 319                                         pgc_pcie2: power-domain@a {
 320                                                 #power-domain-cells = <0>;
 321                                                 reg = <IMX8M_POWER_DOMAIN_PCIE2>;
 322                                         };
 323                                 };
 324                         };
 325                 };
 326
 327                 bus@30400000 { /* AIPS2 */
 328                         compatible = "fsl,imx8mq-aips-bus", "simple-bus";
 329                         #address-cells = <1>;
 330                         #size-cells = <1>;
 331                         ranges = <0x30400000 0x30400000 0x400000>;
 332
 333                         pwm1: pwm@30660000 {
 334                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 335                                 reg = <0x30660000 0x10000>;
 336                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 337                                 clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>,
 338                                          <&clk IMX8MQ_CLK_PWM1_ROOT>;
 339                                 clock-names = "ipg", "per";
 340                                 #pwm-cells = <2>;
 341                                 status = "disabled";
 342                         };
 343
 344                         pwm2: pwm@30670000 {
 345                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 346                                 reg = <0x30670000 0x10000>;
 347                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 348                                 clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
 349                                          <&clk IMX8MQ_CLK_PWM2_ROOT>;
 350                                 clock-names = "ipg", "per";
 351                                 #pwm-cells = <2>;
 352                                 status = "disabled";
 353                         };
 354
 355                         pwm3: pwm@30680000 {
 356                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 357                                 reg = <0x30680000 0x10000>;
 358                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 359                                 clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>,
 360                                          <&clk IMX8MQ_CLK_PWM3_ROOT>;
 361                                 clock-names = "ipg", "per";
 362                                 #pwm-cells = <2>;
 363                                 status = "disabled";
 364                         };
 365
 366                         pwm4: pwm@30690000 {
 367                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 368                                 reg = <0x30690000 0x10000>;
 369                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 370                                 clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>,
 371                                          <&clk IMX8MQ_CLK_PWM4_ROOT>;
 372                                 clock-names = "ipg", "per";
 373                                 #pwm-cells = <2>;
 374                                 status = "disabled";
 375                         };
 376                 };
 377
 378                 bus@30800000 { /* AIPS3 */
 379                         compatible = "fsl,imx8mq-aips-bus", "simple-bus";
 380                         #address-cells = <1>;
 381                         #size-cells = <1>;
 382                         ranges = <0x30800000 0x30800000 0x400000>;
 383
 384                         uart1: serial@30860000 {
 385                                 compatible = "fsl,imx8mq-uart",
 386                                              "fsl,imx6q-uart";
 387                                 reg = <0x30860000 0x10000>;
 388                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 389                                 clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
 390                                          <&clk IMX8MQ_CLK_UART1_ROOT>;
 391                                 clock-names = "ipg", "per";
 392                                 status = "disabled";
 393                         };
 394
 395                         uart3: serial@30880000 {
 396                                 compatible = "fsl,imx8mq-uart",
 397                                              "fsl,imx6q-uart";
 398                                 reg = <0x30880000 0x10000>;
 399                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 400                                 clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
 401                                          <&clk IMX8MQ_CLK_UART3_ROOT>;
 402                                 clock-names = "ipg", "per";
 403                                 status = "disabled";
 404                         };
 405
 406                         uart2: serial@30890000 {
 407                                 compatible = "fsl,imx8mq-uart",
 408                                              "fsl,imx6q-uart";
 409                                 reg = <0x30890000 0x10000>;
 410                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 411                                 clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
 412                                          <&clk IMX8MQ_CLK_UART2_ROOT>;
 413                                 clock-names = "ipg", "per";
 414                                 status = "disabled";
 415                         };
 416
 417                         i2c1: i2c@30a20000 {
 418                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
 419                                 reg = <0x30a20000 0x10000>;
 420                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 421                                 clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
 422                                 #address-cells = <1>;
 423                                 #size-cells = <0>;
 424                                 status = "disabled";
 425                         };
 426
 427                         i2c2: i2c@30a30000 {
 428                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
 429                                 reg = <0x30a30000 0x10000>;
 430                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 431                                 clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
 432                                 #address-cells = <1>;
 433                                 #size-cells = <0>;
 434                                 status = "disabled";
 435                         };
 436
 437                         i2c3: i2c@30a40000 {
 438                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
 439                                 reg = <0x30a40000 0x10000>;
 440                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 441                                 clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
 442                                 #address-cells = <1>;
 443                                 #size-cells = <0>;
 444                                 status = "disabled";
 445                         };
 446
 447                         i2c4: i2c@30a50000 {
 448                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
 449                                 reg = <0x30a50000 0x10000>;
 450                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 451                                 clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
 452                                 #address-cells = <1>;
 453                                 #size-cells = <0>;
 454                                 status = "disabled";
 455                         };
 456
 457                         uart4: serial@30a60000 {
 458                                 compatible = "fsl,imx8mq-uart",
 459                                              "fsl,imx6q-uart";
 460                                 reg = <0x30a60000 0x10000>;
 461                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 462                                 clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
 463                                          <&clk IMX8MQ_CLK_UART4_ROOT>;
 464                                 clock-names = "ipg", "per";
 465                                 status = "disabled";
 466                         };
 467
 468                         usdhc1: mmc@30b40000 {
 469                                 compatible = "fsl,imx8mq-usdhc",
 470                                              "fsl,imx7d-usdhc";
 471                                 reg = <0x30b40000 0x10000>;
 472                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 473                                 clocks = <&clk IMX8MQ_CLK_DUMMY>,
 474                                          <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
 475                                          <&clk IMX8MQ_CLK_USDHC1_ROOT>;
 476                                 clock-names = "ipg", "ahb", "per";
 477                                 fsl,tuning-start-tap = <20>;
 478                                 fsl,tuning-step = <2>;
 479                                 bus-width = <4>;
 480                                 status = "disabled";
 481                         };
 482
 483                         usdhc2: mmc@30b50000 {
 484                                 compatible = "fsl,imx8mq-usdhc",
 485                                              "fsl,imx7d-usdhc";
 486                                 reg = <0x30b50000 0x10000>;
 487                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 488                                 clocks = <&clk IMX8MQ_CLK_DUMMY>,
 489                                          <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
 490                                          <&clk IMX8MQ_CLK_USDHC2_ROOT>;
 491                                 clock-names = "ipg", "ahb", "per";
 492                                 fsl,tuning-start-tap = <20>;
 493                                 fsl,tuning-step = <2>;
 494                                 bus-width = <4>;
 495                                 status = "disabled";
 496                         };
 497
 498                         fec1: ethernet@30be0000 {
 499                                 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
 500                                 reg = <0x30be0000 0x10000>;
 501                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 502                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 503                                              <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 504                                 clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
 505                                          <&clk IMX8MQ_CLK_ENET1_ROOT>,
 506                                          <&clk IMX8MQ_CLK_ENET_TIMER>,
 507                                          <&clk IMX8MQ_CLK_ENET_REF>,
 508                                          <&clk IMX8MQ_CLK_ENET_PHY_REF>;
 509                                 clock-names = "ipg", "ahb", "ptp",
 510                                               "enet_clk_ref", "enet_out";
 511                                 fsl,num-tx-queues = <3>;
 512                                 fsl,num-rx-queues = <3>;
 513                                 status = "disabled";
 514                         };
 515                 };
 516
 517                 gic: interrupt-controller@38800000 {
 518                         compatible = "arm,gic-v3";
 519                         reg = <0x38800000 0x10000>,     /* GIC Dist */
 520                               <0x38880000 0xc0000>,     /* GICR */
 521                               <0x31000000 0x2000>,      /* GICC */
 522                               <0x31010000 0x2000>,      /* GICV */
 523                               <0x31020000 0x2000>;      /* GICH */
 524                         #interrupt-cells = <3>;
 525                         interrupt-controller;
 526                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 527                         interrupt-parent = <&gic>;
 528                 };
 529         };
 530 };