arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (C) 2019 Zodiac Inflight Innovations
   4  */
   5
   6 #include "imx8mq.dtsi"
   7
   8 / {
   9         aliases {
  10                 mdio-gpio0 = &mdio0;
  11                 rtc0 = &ds1341;
  12         };
  13
  14         chosen {
  15                 stdout-path = &uart1;
  16         };
  17
  18         mdio0: bitbang-mdio {
  19                 compatible = "virtual,mdio-gpio";
  20                 pinctrl-names = "default";
  21                 pinctrl-0 = <&pinctrl_mdio_bitbang>, <&pinctrl_fec1_phy_reset>;
  22                 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>, /* MDC */
  23                         <&gpio1 14 GPIO_ACTIVE_HIGH>; /* MDIO */
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 phy0: ethernet-phy@0 {
  28                         reg = <0>;
  29                         reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
  30                 };
  31         };
  32
  33         pcie0_refclk: clock-pcie0-refclk {
  34                 compatible = "fixed-clock";
  35                 #clock-cells = <0>;
  36                 clock-frequency = <100000000>;
  37         };
  38
  39         pcie1_refclk: clock-pcie1-refclk {
  40                 compatible = "fixed-clock";
  41                 #clock-cells = <0>;
  42                 clock-frequency = <100000000>;
  43         };
  44
  45         reg_12p0_main: regulator-12p0-main {
  46                 compatible = "regulator-fixed";
  47                 regulator-name = "12V_MAIN";
  48                 regulator-min-microvolt = <5000000>;
  49                 regulator-max-microvolt = <5000000>;
  50                 regulator-always-on;
  51         };
  52
  53         reg_5p0_main: regulator-5p0-main {
  54                 compatible = "regulator-fixed";
  55                 vin-supply = <&reg_12p0_main>;
  56                 regulator-name = "5V_MAIN";
  57                 regulator-min-microvolt = <5000000>;
  58                 regulator-max-microvolt = <5000000>;
  59                 regulator-always-on;
  60         };
  61
  62         reg_3p3_main: regulator-3p3-main {
  63                 compatible = "regulator-fixed";
  64                 vin-supply = <&reg_12p0_main>;
  65                 regulator-name = "3V3_MAIN";
  66                 regulator-min-microvolt = <3300000>;
  67                 regulator-max-microvolt = <3300000>;
  68                 regulator-always-on;
  69         };
  70
  71         reg_gen_3p3: regulator-gen-3p3 {
  72                 compatible = "regulator-fixed";
  73                 vin-supply = <&reg_3p3_main>;
  74                 regulator-name = "GEN_3V3";
  75                 regulator-min-microvolt = <3300000>;
  76                 regulator-max-microvolt = <3300000>;
  77                 regulator-always-on;
  78         };
  79
  80         reg_3p3v: regulator-3p3v {
  81                 compatible = "regulator-fixed";
  82                 vin-supply = <&reg_3p3_main>;
  83                 regulator-name = "GEN_3V3";
  84                 regulator-min-microvolt = <3300000>;
  85                 regulator-max-microvolt = <3300000>;
  86                 regulator-always-on;
  87         };
  88
  89         reg_usdhc2_vmmc: regulator-vsd-3v3 {
  90                 pinctrl-names = "default";
  91                 pinctrl-0 = <&pinctrl_reg_usdhc2>;
  92                 compatible = "regulator-fixed";
  93                 vin-supply = <&reg_gen_3p3>;
  94                 regulator-name = "3V3_SD";
  95                 regulator-min-microvolt = <3300000>;
  96                 regulator-max-microvolt = <3300000>;
  97                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  98                 enable-active-high;
  99         };
 100
 101         reg_arm: regulator-arm {
 102                 pinctrl-names = "default";
 103                 pinctrl-0 = <&pinctrl_reg_arm>;
 104                 compatible = "regulator-gpio";
 105                 vin-supply = <&reg_12p0_main>;
 106                 regulator-name = "0V9_ARM";
 107                 regulator-min-microvolt = <900000>;
 108                 regulator-max-microvolt = <1000000>;
 109                 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
 110                 states = <1000000 0x1
 111                            900000 0x0>;
 112                 regulator-always-on;
 113         };
 114
 115         cs2000_ref: cs2000-ref {
 116                 compatible = "fixed-clock";
 117                 #clock-cells = <0>;
 118                 clock-frequency = <24576000>;
 119         };
 120
 121         cs2000_in_dummy: cs2000-in-dummy {
 122                 compatible = "fixed-clock";
 123                 #clock-cells = <0>;
 124                 clock-frequency = <0>;
 125         };
 126 };
 127
 128 &A53_0 {
 129         cpu-supply = <&reg_arm>;
 130 };
 131
 132 &A53_1 {
 133         cpu-supply = <&reg_arm>;
 134 };
 135
 136 &A53_2 {
 137         cpu-supply = <&reg_arm>;
 138 };
 139
 140 &A53_3 {
 141         cpu-supply = <&reg_arm>;
 142 };
 143
 144 &fec1 {
 145         pinctrl-names = "default";
 146         pinctrl-0 = <&pinctrl_fec1>;
 147
 148         phy-handle = <&phy0>;
 149         phy-mode = "rmii";
 150         status = "okay";
 151
 152         mdio {
 153                 #address-cells = <1>;
 154                 #size-cells = <0>;
 155                 clock-frequency = <12500000>;
 156                 suppress-preamble;
 157                 status = "okay";
 158
 159                 switch: switch@0 {
 160                         compatible = "marvell,mv88e6085";
 161                         pinctrl-0 = <&pinctrl_switch_irq>;
 162                         pinctrl-names = "default";
 163                         reg = <0>;
 164                         dsa,member = <0 0>;
 165                         eeprom-length = <512>;
 166                         interrupt-parent = <&gpio1>;
 167                         interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
 168                         interrupt-controller;
 169                         #interrupt-cells = <2>;
 170
 171                         ports {
 172                                 #address-cells = <1>;
 173                                 #size-cells = <0>;
 174
 175                                 port@0 {
 176                                         reg = <0>;
 177                                         label = "gigabit_proc";
 178                                         phy-handle = <&switchphy0>;
 179                                 };
 180
 181                                 port@1 {
 182                                         reg = <1>;
 183                                         label = "netaux";
 184                                         phy-handle = <&switchphy1>;
 185                                 };
 186
 187                                 port@2 {
 188                                         reg = <2>;
 189                                         label = "cpu";
 190                                         ethernet = <&fec1>;
 191
 192                                         fixed-link {
 193                                                 speed = <100>;
 194                                                 full-duplex;
 195                                         };
 196                                 };
 197
 198                                 port@3 {
 199                                         reg = <3>;
 200                                         label = "netright";
 201                                         phy-handle = <&switchphy3>;
 202                                 };
 203
 204                                 port@4 {
 205                                         reg = <4>;
 206                                         label = "netleft";
 207                                         phy-handle = <&switchphy4>;
 208                                 };
 209                         };
 210
 211                         mdio {
 212                                 #address-cells = <1>;
 213                                 #size-cells = <0>;
 214
 215                                 switchphy0: switchphy@0 {
 216                                         reg = <0>;
 217                                         interrupt-parent = <&switch>;
 218                                         interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
 219                                 };
 220
 221                                 switchphy1: switchphy@1 {
 222                                         reg = <1>;
 223                                         interrupt-parent = <&switch>;
 224                                         interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
 225                                 };
 226
 227                                 switchphy2: switchphy@2 {
 228                                         reg = <2>;
 229                                         interrupt-parent = <&switch>;
 230                                         interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 231                                 };
 232
 233                                 switchphy3: switchphy@3 {
 234                                         reg = <3>;
 235                                         interrupt-parent = <&switch>;
 236                                         interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
 237                                 };
 238
 239                                 switchphy4: switchphy@4 {
 240                                         reg = <4>;
 241                                         interrupt-parent = <&switch>;
 242                                         interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
 243                                 };
 244                         };
 245                 };
 246         };
 247 };
 248
 249 &gpio3 {
 250         pinctrl-names = "default";
 251         pinctrl-0 = <&pinctrl_gpio3_hog>;
 252
 253         usb-emulation-hog {
 254                 gpio-hog;
 255                 gpios = <10 GPIO_ACTIVE_HIGH>;
 256                 output-low;
 257                 line-name = "usb-emulation";
 258         };
 259
 260         usb-mode1-hog {
 261                 gpio-hog;
 262                 gpios = <11 GPIO_ACTIVE_HIGH>;
 263                 output-high;
 264                 line-name = "usb-mode1";
 265         };
 266
 267         usb-pwr-hog {
 268                 gpio-hog;
 269                 gpios = <12 GPIO_ACTIVE_LOW>;
 270                 output-high;
 271                 line-name = "usb-pwr-ctrl-en-n";
 272         };
 273
 274         usb-mode2-hog {
 275                 gpio-hog;
 276                 gpios = <13 GPIO_ACTIVE_HIGH>;
 277                 output-high;
 278                 line-name = "usb-mode2";
 279         };
 280 };
 281
 282 &i2c1 {
 283         clock-frequency = <400000>;
 284         pinctrl-names = "default";
 285         pinctrl-0 = <&pinctrl_i2c1>;
 286         status = "okay";
 287
 288         accelerometer@1c {
 289                 compatible = "fsl,mma8451";
 290                 pinctrl-names = "default";
 291                 pinctrl-0 = <&pinctrl_accel>;
 292                 reg = <0x1c>;
 293                 interrupt-parent = <&gpio3>;
 294                 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
 295                 interrupt-names = "INT2";
 296                 vdd-supply = <&reg_gen_3p3>;
 297                 vddio-supply = <&reg_gen_3p3>;
 298         };
 299
 300         ucs1002: charger@32 {
 301                 compatible = "microchip,ucs1002";
 302                 pinctrl-names = "default";
 303                 pinctrl-0 = <&pinctrl_ucs1002>;
 304                 reg = <0x32>;
 305                 interrupt-parent = <&gpio3>;
 306                 interrupts = <17 IRQ_TYPE_EDGE_BOTH>,
 307                              <18 IRQ_TYPE_EDGE_FALLING>;
 308                 interrupt-names = "a_det", "alert";
 309         };
 310
 311         hpa2: amp@60 {
 312                 compatible = "ti,tpa6130a2";
 313                 pinctrl-names = "default";
 314                 pinctrl-0 = <&pinctrl_tpa2>;
 315                 reg = <0x60>;
 316                 power-gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
 317                 Vdd-supply = <&reg_5p0_main>;
 318                 sound-name-prefix = "HPA2";
 319         };
 320 };
 321
 322 &i2c2 {
 323         clock-frequency = <400000>;
 324         pinctrl-names = "default";
 325         pinctrl-0 = <&pinctrl_i2c2>;
 326         status = "okay";
 327
 328         pmic@8 {
 329                 compatible = "fsl,pfuze100";
 330                 reg = <0x8>;
 331
 332                 regulators {
 333                         sw1a_reg: sw1ab {
 334                                 regulator-min-microvolt = <825000>;
 335                                 regulator-max-microvolt = <1100000>;
 336                         };
 337
 338                         sw1c_reg: sw1c {
 339                                 regulator-min-microvolt = <825000>;
 340                                 regulator-max-microvolt = <1100000>;
 341                         };
 342
 343                         sw2_reg: sw2 {
 344                                 regulator-min-microvolt = <1100000>;
 345                                 regulator-max-microvolt = <1100000>;
 346                                 regulator-always-on;
 347                         };
 348
 349                         sw3a_reg: sw3ab {
 350                                 regulator-min-microvolt = <825000>;
 351                                 regulator-max-microvolt = <1100000>;
 352                                 regulator-always-on;
 353                         };
 354
 355                         sw4_reg: sw4 {
 356                                 regulator-min-microvolt = <1800000>;
 357                                 regulator-max-microvolt = <1800000>;
 358                                 regulator-always-on;
 359                         };
 360
 361                         swbst_reg: swbst {
 362                                 regulator-min-microvolt = <5000000>;
 363                                 regulator-max-microvolt = <5150000>;
 364                         };
 365
 366                         snvs_reg: vsnvs {
 367                                 regulator-min-microvolt = <1000000>;
 368                                 regulator-max-microvolt = <3000000>;
 369                                 regulator-always-on;
 370                         };
 371
 372                         vref_reg: vrefddr {
 373                                 regulator-always-on;
 374                         };
 375
 376                         vgen1_reg: vgen1 {
 377                                 regulator-min-microvolt = <800000>;
 378                                 regulator-max-microvolt = <1550000>;
 379                         };
 380
 381                         vgen2_reg: vgen2 {
 382                                 regulator-min-microvolt = <850000>;
 383                                 regulator-max-microvolt = <975000>;
 384                                 regulator-always-on;
 385                         };
 386
 387                         vgen3_reg: vgen3 {
 388                                 regulator-min-microvolt = <1675000>;
 389                                 regulator-max-microvolt = <1975000>;
 390                                 regulator-always-on;
 391                         };
 392
 393                         vgen4_reg: vgen4 {
 394                                 regulator-min-microvolt = <1625000>;
 395                                 regulator-max-microvolt = <1875000>;
 396                                 regulator-always-on;
 397                         };
 398
 399                         vgen5_reg: vgen5 {
 400                                 regulator-min-microvolt = <3075000>;
 401                                 regulator-max-microvolt = <3625000>;
 402                                 regulator-always-on;
 403                         };
 404
 405                         vgen6_reg: vgen6 {
 406                                 regulator-min-microvolt = <1800000>;
 407                                 regulator-max-microvolt = <3300000>;
 408                         };
 409                 };
 410         };
 411
 412         codec1: codec@18 {
 413                 compatible = "ti,tlv320dac3100";
 414                 pinctrl-names = "default";
 415                 pinctrl-0 = <&pinctrl_codec1>;
 416                 reg = <0x18>;
 417                 #sound-dai-cells = <0>;
 418                 HPVDD-supply = <&reg_3p3v>;
 419                 SPRVDD-supply = <&reg_3p3v>;
 420                 SPLVDD-supply = <&reg_3p3v>;
 421                 AVDD-supply = <&reg_3p3v>;
 422                 IOVDD-supply = <&reg_3p3v>;
 423                 DVDD-supply = <&vgen4_reg>;
 424                 reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>;
 425         };
 426
 427         eeprom@54 {
 428                 compatible = "atmel,24c128";
 429                 reg = <0x54>;
 430         };
 431
 432         hpa1: amp@60 {
 433                 compatible = "ti,tpa6130a2";
 434                 pinctrl-names = "default";
 435                 pinctrl-0 = <&pinctrl_tpa1>;
 436                 reg = <0x60>;
 437                 power-gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>;
 438                 Vdd-supply = <&reg_5p0_main>;
 439                 sound-name-prefix = "HPA1";
 440         };
 441
 442         ds1341: rtc@68 {
 443                 compatible = "dallas,ds1341";
 444                 reg = <0x68>;
 445         };
 446 };
 447
 448 &i2c3 {
 449         clock-frequency = <100000>;
 450         pinctrl-names = "default";
 451         pinctrl-0 = <&pinctrl_i2c3>;
 452         status = "okay";
 453
 454         usbhub: usbhub@2c {
 455                 compatible ="microchip,usb2513b";
 456                 pinctrl-names = "default";
 457                 pinctrl-0 = <&pinctrl_usbhub>;
 458                 reg = <0x2c>;
 459                 reset-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
 460         };
 461
 462         watchdog@38 {
 463                 compatible = "zii,rave-wdt";
 464                 reg = <0x38>;
 465         };
 466
 467         cs2000: clkgen@4e {
 468                 compatible = "cirrus,cs2000-cp";
 469                 reg = <0x4e>;
 470                 #clock-cells = <0>;
 471                 clock-names = "clk_in", "ref_clk";
 472                 clocks = <&cs2000_in_dummy>, <&cs2000_ref>;
 473                 assigned-clocks = <&cs2000>;
 474                 assigned-clock-rates = <24000000>;
 475         };
 476 };
 477
 478 &i2c4 {
 479         clock-frequency = <400000>;
 480         pinctrl-names = "default";
 481         pinctrl-0 = <&pinctrl_i2c4>;
 482         status = "okay";
 483 };
 484
 485 &sai2 {
 486         pinctrl-names = "default";
 487         pinctrl-0 = <&pinctrl_sai2>;
 488         status = "okay";
 489 };
 490
 491 &uart1 {
 492         pinctrl-names = "default";
 493         pinctrl-0 = <&pinctrl_uart1>;
 494         status = "okay";
 495 };
 496
 497 &uart2 {
 498         pinctrl-names = "default";
 499         pinctrl-0 = <&pinctrl_uart2>;
 500         status = "okay";
 501
 502         rave-sp {
 503                 compatible = "zii,rave-sp-rdu2";
 504                 current-speed = <1000000>;
 505                 #address-cells = <1>;
 506                 #size-cells = <1>;
 507
 508                 watchdog {
 509                         compatible = "zii,rave-sp-watchdog";
 510                 };
 511
 512                 backlight {
 513                         compatible = "zii,rave-sp-backlight";
 514                 };
 515
 516                 pwrbutton {
 517                         compatible = "zii,rave-sp-pwrbutton";
 518                 };
 519
 520                 eeprom@a3 {
 521                         compatible = "zii,rave-sp-eeprom";
 522                         reg = <0xa3 0x4000>;
 523                         zii,eeprom-name = "dds-eeprom";
 524                 };
 525
 526                 eeprom@a4 {
 527                         compatible = "zii,rave-sp-eeprom";
 528                         reg = <0xa4 0x4000>;
 529                         #address-cells = <1>;
 530                         #size-cells = <1>;
 531                         zii,eeprom-name = "main-eeprom";
 532                 };
 533         };
 534 };
 535
 536 &usb3_phy0 {
 537         vbus-supply = <&ucs1002>;
 538         status = "okay";
 539 };
 540
 541 &usb_dwc3_0 {
 542         dr_mode = "host";
 543         maximum-speed = "high-speed";
 544         status = "okay";
 545 };
 546
 547 &usb3_phy1 {
 548         vbus-supply = <&reg_5p0_main>;
 549         status = "okay";
 550 };
 551
 552 &usb_dwc3_1 {
 553         dr_mode = "host";
 554         maximum-speed = "high-speed";
 555         status = "okay";
 556 };
 557
 558 &pcie0 {
 559         pinctrl-names = "default";
 560         pinctrl-0 = <&pinctrl_pcie0>;
 561         reset-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
 562         clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
 563                  <&clk IMX8MQ_CLK_PCIE1_AUX>,
 564                  <&clk IMX8MQ_CLK_PCIE1_PHY>,
 565                  <&pcie0_refclk>;
 566         clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
 567         status = "okay";
 568 };
 569
 570 &pcie1 {
 571         pinctrl-names = "default";
 572         pinctrl-0 = <&pinctrl_pcie1>;
 573         reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
 574         clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
 575                  <&clk IMX8MQ_CLK_PCIE2_AUX>,
 576                  <&clk IMX8MQ_CLK_PCIE2_PHY>,
 577                  <&pcie1_refclk>;
 578         clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
 579         status = "okay";
 580 };
 581
 582 &pgc_gpu {
 583         power-supply = <&sw1a_reg>;
 584 };
 585
 586 &pgc_vpu {
 587         power-supply = <&sw1c_reg>;
 588 };
 589
 590 &usdhc1 {
 591         assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
 592         assigned-clock-rates = <400000000>;
 593         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 594         pinctrl-0 = <&pinctrl_usdhc1>;
 595         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 596         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 597         vqmmc-supply = <&sw4_reg>;
 598         bus-width = <8>;
 599         non-removable;
 600         no-sd;
 601         no-sdio;
 602         status = "okay";
 603 };
 604
 605 &usdhc2 {
 606         assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
 607         assigned-clock-rates = <200000000>;
 608         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 609         pinctrl-0 = <&pinctrl_usdhc2>;
 610         pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
 611         pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
 612         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 613         vmmc-supply = <&reg_usdhc2_vmmc>;
 614         status = "okay";
 615 };
 616
 617 &snvs_rtc {
 618         status = "disabled";
 619 };
 620
 621 &iomuxc {
 622         pinctrl_accel: accelgrp {
 623                 fsl,pins = <
 624                         MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20                0x41
 625                 >;
 626         };
 627
 628         pinctrl_codec1: dac1grp {
 629                 fsl,pins = <
 630                         MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3               0x41
 631                 >;
 632         };
 633
 634         pinctrl_fec1: fec1grp {
 635                 fsl,pins = <
 636                         MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
 637                         MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO               0x23
 638                         MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x1f
 639                         MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x1f
 640                         MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91
 641                         MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91
 642                         MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK              0x1f
 643                         MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER               0x91
 644                         MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 645                         MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 646                 >;
 647         };
 648
 649         pinctrl_fec1_phy_reset: fec1phyresetgrp {
 650                 fsl,pins = <
 651                         MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29                0x11
 652                 >;
 653         };
 654
 655         pinctrl_gpio3_hog: gpio3hoggrp {
 656                 fsl,pins = <
 657                         MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10             0x6
 658                         MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11             0x6
 659                         MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12             0x6
 660                         MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13             0x6
 661                 >;
 662         };
 663
 664         pinctrl_i2c1: i2c1grp {
 665                 fsl,pins = <
 666                         MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL                  0x40000022
 667                         MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA                  0x400000a2
 668                 >;
 669         };
 670
 671         pinctrl_i2c2: i2c2grp {
 672                 fsl,pins = <
 673                         MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL                  0x40000022
 674                         MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA                  0x400000a2
 675                 >;
 676         };
 677
 678         pinctrl_i2c3: i2c3grp {
 679                 fsl,pins = <
 680                         MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL                  0x40000022
 681                         MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA                  0x400000a2
 682                 >;
 683         };
 684
 685         pinctrl_i2c4: i2c4grp {
 686                 fsl,pins = <
 687                         MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL                  0x40000022
 688                         MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA                  0x400000a2
 689                 >;
 690         };
 691
 692         pinctrl_mdio_bitbang: bitbangmdiogrp {
 693                 fsl,pins = <
 694                         MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13              0x44
 695                         MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14              0x64
 696                 >;
 697         };
 698
 699         pinctrl_pcie0: pcie0grp {
 700                 fsl,pins = <
 701                         MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B           0x66
 702                         MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3               0x6
 703                 >;
 704         };
 705
 706         pinctrl_pcie1: pcie1grp {
 707                 fsl,pins = <
 708                         MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B           0x66
 709                         MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6               0x6
 710                 >;
 711         };
 712
 713         pinctrl_reg_arm: regarmgrp {
 714                 fsl,pins = <
 715                         MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16            0x19
 716                 >;
 717         };
 718
 719         pinctrl_reg_usdhc2: regusdhc2grp {
 720                 fsl,pins = <
 721                         MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19             0x41
 722                 >;
 723         };
 724
 725         pinctrl_sai2: sai2grp {
 726                 fsl,pins = <
 727                         MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC             0xd6
 728                         MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK              0xd6
 729                         MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0            0xd6
 730                 >;
 731         };
 732
 733         pinctrl_switch_irq: switchgrp {
 734                 fsl,pins = <
 735                         MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15              0x41
 736                 >;
 737         };
 738
 739         pinctrl_tpa1: tpa6130-1grp {
 740                 fsl,pins = <
 741                         MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10               0x41
 742                 >;
 743         };
 744
 745         pinctrl_tpa2: tpa6130-2grp {
 746                 fsl,pins = <
 747                         MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8               0x41
 748                 >;
 749         };
 750
 751         pinctrl_ts: tsgrp {
 752                 fsl,pins = <
 753                         MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11              0x96
 754                         MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12              0x96
 755                 >;
 756         };
 757
 758         pinctrl_uart1: uart1grp {
 759                 fsl,pins = <
 760                         MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX             0x49
 761                         MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX             0x49
 762                 >;
 763         };
 764
 765         pinctrl_uart2: uart2grp {
 766                 fsl,pins = <
 767                         MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX             0x49
 768                         MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX             0x49
 769                 >;
 770         };
 771
 772         pinctrl_ucs1002: ucs1002grp {
 773                 fsl,pins = <
 774                         MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17               0x41
 775                         MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18               0x41
 776                 >;
 777         };
 778
 779         pinctrl_usbhub: usbhubgrp {
 780                 fsl,pins = <
 781                         MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25               0x41
 782                 >;
 783         };
 784
 785         pinctrl_usdhc1: usdhc1grp {
 786                 fsl,pins = <
 787                         MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x83
 788                         MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xc3
 789                         MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xc3
 790                         MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xc3
 791                         MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xc3
 792                         MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xc3
 793                         MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xc3
 794                         MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xc3
 795                         MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xc3
 796                         MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xc3
 797                         MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x83
 798                         MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
 799                 >;
 800         };
 801
 802         pinctrl_usdhc1_100mhz: usdhc1-100grp {
 803                 fsl,pins = <
 804                         MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x8d
 805                         MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xcd
 806                         MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xcd
 807                         MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xcd
 808                         MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xcd
 809                         MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xcd
 810                         MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xcd
 811                         MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xcd
 812                         MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xcd
 813                         MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xcd
 814                         MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x8d
 815                         MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
 816                 >;
 817         };
 818
 819         pinctrl_usdhc1_200mhz: usdhc1-200grp {
 820                 fsl,pins = <
 821                         MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x9f
 822                         MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xdf
 823                         MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xdf
 824                         MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xdf
 825                         MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xdf
 826                         MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xdf
 827                         MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xdf
 828                         MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xdf
 829                         MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xdf
 830                         MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xdf
 831                         MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x9f
 832                         MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
 833                 >;
 834         };
 835
 836         pinctrl_usdhc2: usdhc2grp {
 837                 fsl,pins = <
 838                         MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x83
 839                         MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc3
 840                         MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0             0xc3
 841                         MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1             0xc3
 842                         MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2             0xc3
 843                         MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3             0xc3
 844                         MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
 845                 >;
 846         };
 847
 848         pinctrl_usdhc2_100mhz: usdhc2-100grp {
 849                 fsl,pins = <
 850                         MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x85
 851                         MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc5
 852                         MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0             0xc5
 853                         MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1             0xc5
 854                         MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2             0xc5
 855                         MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3             0xc5
 856                         MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
 857                 >;
 858         };
 859
 860         pinctrl_usdhc2_200mhz: usdhc2-200grp {
 861                 fsl,pins = <
 862                         MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x87
 863                         MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc7
 864                         MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0             0xc7
 865                         MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1             0xc7
 866                         MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2             0xc7
 867                         MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3             0xc7
 868                         MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
 869                 >;
 870         };
 871 };