1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright 2017-2019 NXP
11 model = "Google i.MX8MQ Phanbell";
12 compatible = "google,imx8mq-phanbell", "fsl,imx8mq";
19 device_type = "memory";
20 reg = <0x00000000 0x40000000 0 0x40000000>;
23 pmic_osc: clock-pmic {
24 compatible = "fixed-clock";
26 clock-frequency = <32768>;
27 clock-output-names = "pmic_osc";
30 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
31 compatible = "regulator-fixed";
32 regulator-name = "VSD_3V3";
33 regulator-min-microvolt = <3300000>;
34 regulator-max-microvolt = <3300000>;
35 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
40 compatible = "gpio-fan";
41 gpio-fan,speed-map = <0 0 8600 1>;
42 gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>;
44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_gpio_fan>;
51 cpu-supply = <&buck2>;
55 cpu-supply = <&buck2>;
59 cpu-supply = <&buck2>;
63 cpu-supply = <&buck2>;
69 temperature = <75000>;
75 temperature = <80000>;
81 temperature = <90000>;
87 temperature = <65000>;
97 <&A53_0 0 1>; /* Exclude highest OPP */
101 trip = <&cpu_alert1>;
103 <&A53_0 0 2>; /* Exclude two highest OPPs */
107 trip = <&fan_toggle0>;
108 cooling-device = <&fan 0 1>;
114 clock-frequency = <400000>;
115 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_i2c1>;
120 compatible = "rohm,bd71837";
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_pmic>;
125 clocks = <&pmic_osc>;
126 clock-output-names = "pmic_clk";
127 interrupt-parent = <&gpio1>;
128 interrupts = <3 GPIO_ACTIVE_LOW>;
132 regulator-name = "buck1";
133 regulator-min-microvolt = <700000>;
134 regulator-max-microvolt = <1300000>;
137 regulator-ramp-delay = <1250>;
138 rohm,dvs-run-voltage = <900000>;
139 rohm,dvs-idle-voltage = <900000>;
140 rohm,dvs-suspend-voltage = <800000>;
144 regulator-name = "buck2";
145 regulator-min-microvolt = <850000>;
146 regulator-max-microvolt = <1000000>;
149 rohm,dvs-run-voltage = <1000000>;
150 rohm,dvs-idle-voltage = <900000>;
154 regulator-name = "buck3";
155 regulator-min-microvolt = <700000>;
156 regulator-max-microvolt = <1300000>;
158 rohm,dvs-run-voltage = <900000>;
162 regulator-name = "buck4";
163 regulator-min-microvolt = <700000>;
164 regulator-max-microvolt = <1300000>;
167 rohm,dvs-run-voltage = <900000>;
171 regulator-name = "buck5";
172 regulator-min-microvolt = <700000>;
173 regulator-max-microvolt = <1350000>;
179 regulator-name = "buck6";
180 regulator-min-microvolt = <3000000>;
181 regulator-max-microvolt = <3300000>;
187 regulator-name = "buck7";
188 regulator-min-microvolt = <1605000>;
189 regulator-max-microvolt = <1995000>;
195 regulator-name = "buck8";
196 regulator-min-microvolt = <800000>;
197 regulator-max-microvolt = <1400000>;
203 regulator-name = "ldo1";
204 regulator-min-microvolt = <3000000>;
205 regulator-max-microvolt = <3300000>;
211 regulator-name = "ldo2";
212 regulator-min-microvolt = <900000>;
213 regulator-max-microvolt = <900000>;
219 regulator-name = "ldo3";
220 regulator-min-microvolt = <1800000>;
221 regulator-max-microvolt = <3300000>;
227 regulator-name = "ldo4";
228 regulator-min-microvolt = <900000>;
229 regulator-max-microvolt = <1800000>;
235 regulator-name = "ldo5";
236 regulator-min-microvolt = <1800000>;
237 regulator-max-microvolt = <3300000>;
243 regulator-name = "ldo6";
244 regulator-min-microvolt = <900000>;
245 regulator-max-microvolt = <1800000>;
251 regulator-name = "ldo7";
252 regulator-min-microvolt = <1800000>;
253 regulator-max-microvolt = <3300000>;
262 pinctrl-names = "default";
263 pinctrl-0 = <&pinctrl_fec1>;
264 phy-mode = "rgmii-id";
265 phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
266 phy-reset-duration = <10>;
267 phy-reset-post-delay = <50>;
268 phy-handle = <ðphy0>;
273 #address-cells = <1>;
275 ethphy0: ethernet-phy@0 {
276 compatible = "ethernet-phy-ieee802.3-c22";
283 pinctrl-names = "default";
284 pinctrl-0 = <&pinctrl_uart1>;
289 pinctrl-names = "default", "state_100mhz", "state_200mhz";
290 pinctrl-0 = <&pinctrl_usdhc1>;
291 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
292 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
299 pinctrl-names = "default", "state_100mhz", "state_200mhz";
300 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
301 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
302 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
304 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
305 vmmc-supply = <®_usdhc2_vmmc>;
328 pinctrl-names = "default";
329 pinctrl-0 = <&pinctrl_wdog>;
330 fsl,ext-reset-output;
335 pinctrl_fec1: fec1grp {
337 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
338 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
339 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
340 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
341 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
342 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
343 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
344 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
345 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
346 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
347 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
348 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
349 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
350 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
351 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
355 pinctrl_gpio_fan: gpiofangrp {
357 MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x16
361 pinctrl_i2c1: i2c1grp {
363 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
364 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
368 pinctrl_pmic: pmicirq {
370 MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
374 pinctrl_uart1: uart1grp {
376 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
377 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
381 pinctrl_usdhc1: usdhc1grp {
383 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
384 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
385 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
386 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
387 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
388 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
389 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
390 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
391 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
392 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
393 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
394 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
398 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
400 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
401 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
402 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
403 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
404 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
405 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
406 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
407 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
408 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
409 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
410 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
411 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
415 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
417 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
418 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
419 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
420 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
421 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
422 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
423 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
424 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
425 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
426 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
427 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
428 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
432 pinctrl_usdhc2_gpio: usdhc2grpgpio {
434 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
435 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
439 pinctrl_usdhc2: usdhc2grp {
441 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
442 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
443 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
444 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
445 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
446 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
447 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
451 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
453 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
454 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
455 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
456 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
457 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
458 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
459 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
463 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
465 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
466 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
467 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
468 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
469 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
470 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
471 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
475 pinctrl_wdog: wdoggrp {
477 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6