arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright 2017-2019 NXP
   4  */
   5
   6 /dts-v1/;
   7
   8 #include "imx8mq.dtsi"
   9
  10 / {
  11         model = "Google i.MX8MQ Phanbell";
  12         compatible = "google,imx8mq-phanbell", "fsl,imx8mq";
  13
  14         chosen {
  15                 stdout-path = &uart1;
  16         };
  17
  18         memory@40000000 {
  19                 device_type = "memory";
  20                 reg = <0x00000000 0x40000000 0 0x40000000>;
  21         };
  22
  23         pmic_osc: clock-pmic {
  24                 compatible = "fixed-clock";
  25                 #clock-cells = <0>;
  26                 clock-frequency = <32768>;
  27                 clock-output-names = "pmic_osc";
  28         };
  29
  30         reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
  31                 compatible = "regulator-fixed";
  32                 regulator-name = "VSD_3V3";
  33                 regulator-min-microvolt = <3300000>;
  34                 regulator-max-microvolt = <3300000>;
  35                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  36                 enable-active-high;
  37         };
  38
  39         fan: gpio-fan {
  40                 compatible = "gpio-fan";
  41                 gpio-fan,speed-map = <0 0 8600 1>;
  42                 gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>;
  43                 #cooling-cells = <2>;
  44                 pinctrl-names = "default";
  45                 pinctrl-0 = <&pinctrl_gpio_fan>;
  46                 status = "okay";
  47         };
  48 };
  49
  50 &A53_0 {
  51         cpu-supply = <&buck2>;
  52 };
  53
  54 &A53_1 {
  55         cpu-supply = <&buck2>;
  56 };
  57
  58 &A53_2 {
  59         cpu-supply = <&buck2>;
  60 };
  61
  62 &A53_3 {
  63         cpu-supply = <&buck2>;
  64 };
  65
  66 &cpu_thermal {
  67         trips {
  68                 cpu_alert0: trip0 {
  69                         temperature = <75000>;
  70                         hysteresis = <2000>;
  71                         type = "passive";
  72                 };
  73
  74                 cpu_alert1: trip1 {
  75                         temperature = <80000>;
  76                         hysteresis = <2000>;
  77                         type = "passive";
  78                 };
  79
  80                 cpu_crit0: trip3 {
  81                         temperature = <90000>;
  82                         hysteresis = <2000>;
  83                         type = "critical";
  84                 };
  85
  86                 fan_toggle0: trip4 {
  87                         temperature = <65000>;
  88                         hysteresis = <10000>;
  89                         type = "active";
  90                 };
  91         };
  92
  93         cooling-maps {
  94                 map0 {
  95                         trip = <&cpu_alert0>;
  96                         cooling-device =
  97                         <&A53_0 0 1>; /* Exclude highest OPP */
  98                 };
  99
 100                 map1 {
 101                         trip = <&cpu_alert1>;
 102                         cooling-device =
 103                         <&A53_0 0 2>; /* Exclude two highest OPPs */
 104                 };
 105
 106                 map4 {
 107                         trip = <&fan_toggle0>;
 108                         cooling-device = <&fan 0 1>;
 109                 };
 110         };
 111 };
 112
 113 &i2c1 {
 114         clock-frequency = <400000>;
 115         pinctrl-names = "default";
 116         pinctrl-0 = <&pinctrl_i2c1>;
 117         status = "okay";
 118
 119         pmic: pmic@4b {
 120                 compatible = "rohm,bd71837";
 121                 reg = <0x4b>;
 122                 pinctrl-names = "default";
 123                 pinctrl-0 = <&pinctrl_pmic>;
 124                 #clock-cells = <0>;
 125                 clocks = <&pmic_osc>;
 126                 clock-output-names = "pmic_clk";
 127                 interrupt-parent = <&gpio1>;
 128                 interrupts = <3 GPIO_ACTIVE_LOW>;
 129
 130                 regulators {
 131                         buck1: BUCK1 {
 132                                 regulator-name = "buck1";
 133                                 regulator-min-microvolt = <700000>;
 134                                 regulator-max-microvolt = <1300000>;
 135                                 regulator-boot-on;
 136                                 regulator-always-on;
 137                                 regulator-ramp-delay = <1250>;
 138                                 rohm,dvs-run-voltage = <900000>;
 139                                 rohm,dvs-idle-voltage = <900000>;
 140                                 rohm,dvs-suspend-voltage = <800000>;
 141                         };
 142
 143                         buck2: BUCK2 {
 144                                 regulator-name = "buck2";
 145                                 regulator-min-microvolt = <850000>;
 146                                 regulator-max-microvolt = <1000000>;
 147                                 regulator-boot-on;
 148                                 regulator-always-on;
 149                                 rohm,dvs-run-voltage = <1000000>;
 150                                 rohm,dvs-idle-voltage = <900000>;
 151                         };
 152
 153                         buck3: BUCK3 {
 154                                 regulator-name = "buck3";
 155                                 regulator-min-microvolt = <700000>;
 156                                 regulator-max-microvolt = <1300000>;
 157                                 regulator-boot-on;
 158                                 rohm,dvs-run-voltage = <900000>;
 159                         };
 160
 161                         buck4: BUCK4 {
 162                                 regulator-name = "buck4";
 163                                 regulator-min-microvolt = <700000>;
 164                                 regulator-max-microvolt = <1300000>;
 165                                 regulator-boot-on;
 166                                 regulator-always-on;
 167                                 rohm,dvs-run-voltage = <900000>;
 168                         };
 169
 170                         buck5: BUCK5 {
 171                                 regulator-name = "buck5";
 172                                 regulator-min-microvolt = <700000>;
 173                                 regulator-max-microvolt = <1350000>;
 174                                 regulator-boot-on;
 175                                 regulator-always-on;
 176                         };
 177
 178                         buck6: BUCK6 {
 179                                 regulator-name = "buck6";
 180                                 regulator-min-microvolt = <3000000>;
 181                                 regulator-max-microvolt = <3300000>;
 182                                 regulator-boot-on;
 183                                 regulator-always-on;
 184                         };
 185
 186                         buck7: BUCK7 {
 187                                 regulator-name = "buck7";
 188                                 regulator-min-microvolt = <1605000>;
 189                                 regulator-max-microvolt = <1995000>;
 190                                 regulator-boot-on;
 191                                 regulator-always-on;
 192                         };
 193
 194                         buck8: BUCK8 {
 195                                 regulator-name = "buck8";
 196                                 regulator-min-microvolt = <800000>;
 197                                 regulator-max-microvolt = <1400000>;
 198                                 regulator-boot-on;
 199                                 regulator-always-on;
 200                         };
 201
 202                         ldo1: LDO1 {
 203                                 regulator-name = "ldo1";
 204                                 regulator-min-microvolt = <3000000>;
 205                                 regulator-max-microvolt = <3300000>;
 206                                 regulator-boot-on;
 207                                 regulator-always-on;
 208                         };
 209
 210                         ldo2: LDO2 {
 211                                 regulator-name = "ldo2";
 212                                 regulator-min-microvolt = <900000>;
 213                                 regulator-max-microvolt = <900000>;
 214                                 regulator-boot-on;
 215                                 regulator-always-on;
 216                         };
 217
 218                         ldo3: LDO3 {
 219                                 regulator-name = "ldo3";
 220                                 regulator-min-microvolt = <1800000>;
 221                                 regulator-max-microvolt = <3300000>;
 222                                 regulator-boot-on;
 223                                 regulator-always-on;
 224                         };
 225
 226                         ldo4: LDO4 {
 227                                 regulator-name = "ldo4";
 228                                 regulator-min-microvolt = <900000>;
 229                                 regulator-max-microvolt = <1800000>;
 230                                 regulator-boot-on;
 231                                 regulator-always-on;
 232                         };
 233
 234                         ldo5: LDO5 {
 235                                 regulator-name = "ldo5";
 236                                 regulator-min-microvolt = <1800000>;
 237                                 regulator-max-microvolt = <3300000>;
 238                                 regulator-boot-on;
 239                                 regulator-always-on;
 240                         };
 241
 242                         ldo6: LDO6 {
 243                                 regulator-name = "ldo6";
 244                                 regulator-min-microvolt = <900000>;
 245                                 regulator-max-microvolt = <1800000>;
 246                                 regulator-boot-on;
 247                                 regulator-always-on;
 248                         };
 249
 250                         ldo7: LDO7 {
 251                                 regulator-name = "ldo7";
 252                                 regulator-min-microvolt = <1800000>;
 253                                 regulator-max-microvolt = <3300000>;
 254                                 regulator-boot-on;
 255                                 regulator-always-on;
 256                         };
 257                 };
 258         };
 259 };
 260
 261 &fec1 {
 262         pinctrl-names = "default";
 263         pinctrl-0 = <&pinctrl_fec1>;
 264         phy-mode = "rgmii-id";
 265         phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
 266         phy-reset-duration = <10>;
 267         phy-reset-post-delay = <50>;
 268         phy-handle = <&ethphy0>;
 269         fsl,magic-packet;
 270         status = "okay";
 271
 272         mdio {
 273                 #address-cells = <1>;
 274                 #size-cells = <0>;
 275                 ethphy0: ethernet-phy@0 {
 276                         compatible = "ethernet-phy-ieee802.3-c22";
 277                         reg = <0>;
 278                 };
 279         };
 280 };
 281
 282 &uart1 {
 283         pinctrl-names = "default";
 284         pinctrl-0 = <&pinctrl_uart1>;
 285         status = "okay";
 286 };
 287
 288 &usdhc1 {
 289         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 290         pinctrl-0 = <&pinctrl_usdhc1>;
 291         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 292         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 293         bus-width = <8>;
 294         non-removable;
 295         status = "okay";
 296 };
 297
 298 &usdhc2 {
 299         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 300         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 301         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 302         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 303         bus-width = <4>;
 304         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 305         vmmc-supply = <&reg_usdhc2_vmmc>;
 306         status = "okay";
 307 };
 308
 309 &usb3_phy0 {
 310         status = "okay";
 311 };
 312
 313 &usb_dwc3_0 {
 314         dr_mode = "otg";
 315         status = "okay";
 316 };
 317
 318 &usb3_phy1 {
 319         status = "okay";
 320 };
 321
 322 &usb_dwc3_1 {
 323         dr_mode = "host";
 324         status = "okay";
 325 };
 326
 327 &wdog1 {
 328         pinctrl-names = "default";
 329         pinctrl-0 = <&pinctrl_wdog>;
 330         fsl,ext-reset-output;
 331         status = "okay";
 332 };
 333
 334 &iomuxc {
 335         pinctrl_fec1: fec1grp {
 336                 fsl,pins = <
 337                         MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
 338                         MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO               0x23
 339                         MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3           0x1f
 340                         MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2           0x1f
 341                         MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x1f
 342                         MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x1f
 343                         MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3           0x91
 344                         MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2           0x91
 345                         MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91
 346                         MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91
 347                         MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC           0x1f
 348                         MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC           0x91
 349                         MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 350                         MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 351                         MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9               0x19
 352                 >;
 353         };
 354
 355         pinctrl_gpio_fan: gpiofangrp {
 356                 fsl,pins = <
 357                         MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5                 0x16
 358                 >;
 359         };
 360
 361         pinctrl_i2c1: i2c1grp {
 362                 fsl,pins = <
 363                         MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL                  0x4000007f
 364                         MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA                  0x4000007f
 365                 >;
 366         };
 367
 368         pinctrl_pmic: pmicirq {
 369                 fsl,pins = <
 370                         MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3       0x41
 371                 >;
 372         };
 373
 374         pinctrl_uart1: uart1grp {
 375                 fsl,pins = <
 376                         MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX             0x49
 377                         MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX             0x49
 378                 >;
 379         };
 380
 381         pinctrl_usdhc1: usdhc1grp {
 382                 fsl,pins = <
 383                         MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x83
 384                         MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xc3
 385                         MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xc3
 386                         MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xc3
 387                         MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xc3
 388                         MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xc3
 389                         MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xc3
 390                         MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xc3
 391                         MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xc3
 392                         MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xc3
 393                         MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x83
 394                         MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
 395                 >;
 396         };
 397
 398         pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
 399                 fsl,pins = <
 400                         MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x85
 401                         MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xc5
 402                         MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xc5
 403                         MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xc5
 404                         MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xc5
 405                         MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xc5
 406                         MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xc5
 407                         MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xc5
 408                         MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xc5
 409                         MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xc5
 410                         MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x85
 411                         MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
 412                 >;
 413         };
 414
 415         pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
 416                 fsl,pins = <
 417                         MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x87
 418                         MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xc7
 419                         MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xc7
 420                         MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xc7
 421                         MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xc7
 422                         MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xc7
 423                         MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xc7
 424                         MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xc7
 425                         MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xc7
 426                         MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xc7
 427                         MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x87
 428                         MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
 429                 >;
 430         };
 431
 432         pinctrl_usdhc2_gpio: usdhc2grpgpio {
 433                 fsl,pins = <
 434                         MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12        0x41
 435                         MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19     0x41
 436                 >;
 437         };
 438
 439         pinctrl_usdhc2: usdhc2grp {
 440                 fsl,pins = <
 441                         MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x83
 442                         MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc3
 443                         MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0             0xc3
 444                         MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1             0xc3
 445                         MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2             0xc3
 446                         MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3             0xc3
 447                         MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
 448                 >;
 449         };
 450
 451         pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
 452                 fsl,pins = <
 453                         MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x85
 454                         MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc5
 455                         MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0             0xc5
 456                         MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1             0xc5
 457                         MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2             0xc5
 458                         MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3             0xc5
 459                         MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
 460                 >;
 461         };
 462
 463         pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
 464                 fsl,pins = <
 465                         MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x87
 466                         MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc7
 467                         MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0             0xc7
 468                         MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1             0xc7
 469                         MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2             0xc7
 470                         MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3             0xc7
 471                         MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
 472                 >;
 473         };
 474
 475         pinctrl_wdog: wdoggrp {
 476                 fsl,pins = <
 477                         MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
 478                 >;
 479         };
 480 };