arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2018 Boundary Devices
   4  * Copyright 2021 Lucas Stach <dev@lynxeye.de>
   5  */
   6
   7 #include "imx8mq.dtsi"
   8
   9 / {
  10         model = "Boundary Devices i.MX8MQ Nitrogen8M";
  11         compatible = "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq";
  12
  13         chosen {
  14                 stdout-path = &uart1;
  15         };
  16
  17         reg_1p8v: regulator-fixed-1v8 {
  18                 compatible = "regulator-fixed";
  19                 regulator-name = "1P8V";
  20                 regulator-min-microvolt = <1800000>;
  21                 regulator-max-microvolt = <1800000>;
  22         };
  23
  24         reg_snvs: regulator-fixed-snvs {
  25                 compatible = "regulator-fixed";
  26                 regulator-name = "VDD_SNVS";
  27                 regulator-min-microvolt = <3300000>;
  28                 regulator-max-microvolt = <3300000>;
  29         };
  30 };
  31
  32 &{/opp-table/opp-800000000} {
  33         opp-microvolt = <1000000>;
  34 };
  35
  36 &{/opp-table/opp-1000000000} {
  37         opp-microvolt = <1000000>;
  38 };
  39
  40 &A53_0 {
  41         cpu-supply = <&reg_arm_dram>;
  42 };
  43
  44 &A53_1 {
  45         cpu-supply = <&reg_arm_dram>;
  46 };
  47
  48 &A53_2 {
  49         cpu-supply = <&reg_arm_dram>;
  50 };
  51
  52 &A53_3 {
  53         cpu-supply = <&reg_arm_dram>;
  54 };
  55
  56 &fec1 {
  57         pinctrl-names = "default";
  58         pinctrl-0 = <&pinctrl_fec1>;
  59         phy-mode = "rgmii-id";
  60         phy-handle = <&ethphy0>;
  61         fsl,magic-packet;
  62
  63         mdio {
  64                 #address-cells = <1>;
  65                 #size-cells = <0>;
  66
  67                 ethphy0: ethernet-phy@4 {
  68                         compatible = "ethernet-phy-ieee802.3-c22";
  69                         reg = <4>;
  70                         interrupt-parent = <&gpio1>;
  71                         interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
  72                         reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
  73                         reset-assert-us = <10000>;
  74                         reset-deassert-us = <300>;
  75                 };
  76         };
  77 };
  78
  79 &i2c1 {
  80         clock-frequency = <400000>;
  81         pinctrl-names = "default";
  82         pinctrl-0 = <&pinctrl_i2c1>;
  83         status = "okay";
  84
  85         i2c-mux@70 {
  86                 compatible = "nxp,pca9546";
  87                 pinctrl-names = "default";
  88                 pinctrl-0 = <&pinctrl_i2c1_pca9546>;
  89                 reg = <0x70>;
  90                 reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
  91                 #address-cells = <1>;
  92                 #size-cells = <0>;
  93
  94                 i2c1a: i2c@0 {
  95                         reg = <0>;
  96                         #address-cells = <1>;
  97                         #size-cells = <0>;
  98
  99                         reg_arm_dram: regulator@60 {
 100                                 compatible = "fcs,fan53555";
 101                                 reg = <0x60>;
 102                                 regulator-name = "VDD_ARM_DRAM_1V";
 103                                 regulator-min-microvolt = <1000000>;
 104                                 regulator-max-microvolt = <1000000>;
 105                                 regulator-always-on;
 106                         };
 107                 };
 108
 109                 i2c1b: i2c@1 {
 110                         reg = <1>;
 111                         #address-cells = <1>;
 112                         #size-cells = <0>;
 113
 114                         reg_dram_1p1v: regulator@60 {
 115                                 compatible = "fcs,fan53555";
 116                                 reg = <0x60>;
 117                                 regulator-name = "NVCC_DRAM_1P1V";
 118                                 regulator-min-microvolt = <1100000>;
 119                                 regulator-max-microvolt = <1100000>;
 120                                 regulator-always-on;
 121                         };
 122                 };
 123
 124                 i2c1c: i2c@2 {
 125                         reg = <2>;
 126                         #address-cells = <1>;
 127                         #size-cells = <0>;
 128
 129                         reg_soc_gpu_vpu: regulator@60 {
 130                                 compatible = "fcs,fan53555";
 131                                 reg = <0x60>;
 132                                 regulator-name = "VDD_SOC_GPU_VPU";
 133                                 regulator-min-microvolt = <900000>;
 134                                 regulator-max-microvolt = <900000>;
 135                                 regulator-always-on;
 136                         };
 137                 };
 138
 139                 i2c1d: i2c@3 {
 140                         reg = <3>;
 141                         #address-cells = <1>;
 142                         #size-cells = <0>;
 143                 };
 144         };
 145 };
 146
 147 &pgc_gpu {
 148         power-supply = <&reg_soc_gpu_vpu>;
 149 };
 150
 151 &pgc_vpu {
 152         power-supply = <&reg_soc_gpu_vpu>;
 153 };
 154
 155 &uart1 {
 156         pinctrl-names = "default";
 157         pinctrl-0 = <&pinctrl_uart1>;
 158         status = "okay";
 159 };
 160
 161 &usdhc1 {
 162         assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
 163         assigned-clock-rates = <400000000>;
 164         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 165         pinctrl-0 = <&pinctrl_usdhc1>;
 166         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 167         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 168         vqmmc-supply = <&reg_1p8v>;
 169         vmmc-supply = <&reg_snvs>;
 170         bus-width = <8>;
 171         non-removable;
 172         no-mmc-hs400;
 173         no-sdio;
 174         no-sd;
 175         status = "okay";
 176 };
 177
 178 &wdog1 {
 179         pinctrl-names = "default";
 180         pinctrl-0 = <&pinctrl_wdog>;
 181         fsl,ext-reset-output;
 182         status = "okay";
 183 };
 184
 185 &iomuxc {
 186         pinctrl_fec1: fec1grp {
 187                 fsl,pins = <
 188                         MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
 189                         MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO               0x23
 190                         MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 191                         MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC           0x1f
 192                         MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x1f
 193                         MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x1f
 194                         MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2           0x1f
 195                         MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3           0x1f
 196                         MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 197                         MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC           0xd1
 198                         MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91
 199                         MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91
 200                         MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2           0x91
 201                         MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3           0xd1
 202                         MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9               0x1
 203                         MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11              0x41
 204                 >;
 205         };
 206
 207         pinctrl_i2c1: i2c1grp {
 208                 fsl,pins = <
 209                         MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL                  0x40000022
 210                         MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA                  0x40000022
 211                 >;
 212         };
 213
 214         pinctrl_i2c1_pca9546: i2c1-pca9546grp {
 215                 fsl,pins = <
 216                         MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8               0x49
 217                 >;
 218         };
 219
 220         pinctrl_uart1: uart1grp {
 221                 fsl,pins = <
 222                         MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX             0x45
 223                         MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX             0x45
 224                 >;
 225         };
 226
 227         pinctrl_usdhc1: usdhc1grp {
 228                 fsl,pins = <
 229                         MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x83
 230                         MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xc3
 231                         MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xc3
 232                         MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xc3
 233                         MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xc3
 234                         MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xc3
 235                         MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xc3
 236                         MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xc3
 237                         MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xc3
 238                         MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xc3
 239                         MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
 240                 >;
 241         };
 242
 243         pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
 244                 fsl,pins = <
 245                         MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x8d
 246                         MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xcd
 247                         MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xcd
 248                         MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xcd
 249                         MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xcd
 250                         MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xcd
 251                         MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xcd
 252                         MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xcd
 253                         MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xcd
 254                         MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xcd
 255                 >;
 256         };
 257
 258         pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
 259                 fsl,pins = <
 260                         MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x9f
 261                         MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xdf
 262                         MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xdf
 263                         MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xdf
 264                         MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xdf
 265                         MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xdf
 266                         MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xdf
 267                         MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xdf
 268                         MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xdf
 269                         MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xdf
 270                 >;
 271         };
 272
 273         pinctrl_wdog: wdoggrp {
 274                 fsl,pins = <
 275                         MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B            0xc6
 276                 >;
 277         };
 278 };