1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright 2019-2021 MNT Research GmbH
5 * Copyright 2021 Lucas Stach <dev@lynxeye.de>
10 #include "imx8mq-nitrogen-som.dtsi"
13 model = "MNT Reform 2";
14 compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq";
16 pcie1_refclk: clock-pcie1-refclk {
17 compatible = "fixed-clock";
19 clock-frequency = <100000000>;
22 reg_main_5v: regulator-main-5v {
23 compatible = "regulator-fixed";
24 regulator-name = "5V";
25 regulator-min-microvolt = <5000000>;
26 regulator-max-microvolt = <5000000>;
29 reg_main_3v3: regulator-main-3v3 {
30 compatible = "regulator-fixed";
31 regulator-name = "3V3";
32 regulator-min-microvolt = <3300000>;
33 regulator-max-microvolt = <3300000>;
36 reg_main_usb: regulator-main-usb {
37 compatible = "regulator-fixed";
38 regulator-name = "USB_PWR";
39 regulator-min-microvolt = <5000000>;
40 regulator-max-microvolt = <5000000>;
41 vin-supply = <®_main_5v>;
45 compatible = "fsl,imx-audio-wm8960";
47 audio-codec = <&wm8960>;
49 "Headphone Jack", "HP_L",
50 "Headphone Jack", "HP_R",
55 "LINPUT1", "Mic Jack",
57 "LINPUT2", "Line In Jack",
58 "RINPUT2", "Line In Jack";
59 model = "wm8960-audio";
68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_i2c3>;
73 compatible = "wlf,wm8960";
75 clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
77 #sound-dai-cells = <0>;
81 compatible = "nxp,pcf8523";
87 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_pcie1>;
89 reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>;
90 clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
91 <&clk IMX8MQ_CLK_PCIE2_AUX>,
92 <&clk IMX8MQ_CLK_PCIE2_PHY>,
94 clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
99 vin-supply = <®_main_5v>;
103 vin-supply = <®_main_5v>;
107 vin-supply = <®_main_5v>;
111 vin-supply = <®_main_5v>;
115 vin-supply = <®_main_5v>;
119 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_sai2>;
121 assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
122 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
123 assigned-clock-rates = <25000000>;
124 fsl,sai-mclk-direction-output;
125 fsl,sai-asynchronous;
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_uart2>;
140 vbus-supply = <®_main_usb>;
145 vbus-supply = <®_main_usb>;
160 assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
161 assigned-clock-rates = <200000000>;
162 pinctrl-names = "default";
163 pinctrl-0 = <&pinctrl_usdhc2>;
164 vqmmc-supply = <®_main_3v3>;
165 vmmc-supply = <®_main_3v3>;
171 pinctrl_i2c3: i2c3grp {
173 MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
174 MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
178 pinctrl_pcie1: pcie1grp {
180 MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x16
184 pinctrl_sai2: sai2grp {
186 MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
187 MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0xd6
188 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
189 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
190 MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0xd6
191 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
192 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
196 pinctrl_uart2: uart2grp {
198 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45
199 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45
203 pinctrl_usdhc2: usdhc2grp {
205 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
206 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
207 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
208 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
209 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
210 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3