arch/arm64/boot/dts/freescale/imx8mq-evk.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright 2017 NXP
   4  * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
   5  */
   6
   7 /dts-v1/;
   8
   9 #include "imx8mq.dtsi"
  10
  11 / {
  12         model = "NXP i.MX8MQ EVK";
  13         compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
  14
  15         chosen {
  16                 stdout-path = &uart1;
  17         };
  18
  19         memory@40000000 {
  20                 device_type = "memory";
  21                 reg = <0x00000000 0x40000000 0 0xc0000000>;
  22         };
  23
  24         pcie0_refclk: pcie0-refclk {
  25                 compatible = "fixed-clock";
  26                 #clock-cells = <0>;
  27                 clock-frequency = <100000000>;
  28         };
  29
  30         reg_usdhc2_vmmc: regulator-vsd-3v3 {
  31                 pinctrl-names = "default";
  32                 pinctrl-0 = <&pinctrl_reg_usdhc2>;
  33                 compatible = "regulator-fixed";
  34                 regulator-name = "VSD_3V3";
  35                 regulator-min-microvolt = <3300000>;
  36                 regulator-max-microvolt = <3300000>;
  37                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  38                 enable-active-high;
  39         };
  40
  41         buck2_reg: regulator-buck2 {
  42                 pinctrl-names = "default";
  43                 pinctrl-0 = <&pinctrl_buck2>;
  44                 compatible = "regulator-gpio";
  45                 regulator-name = "vdd_arm";
  46                 regulator-min-microvolt = <900000>;
  47                 regulator-max-microvolt = <1000000>;
  48                 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
  49                 states = <1000000 0x0
  50                           900000 0x1>;
  51                 regulator-boot-on;
  52                 regulator-always-on;
  53         };
  54
  55         ir-receiver {
  56                 compatible = "gpio-ir-receiver";
  57                 gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
  58                 pinctrl-names = "default";
  59                 pinctrl-0 = <&pinctrl_ir>;
  60         };
  61
  62         wm8524: audio-codec {
  63                 #sound-dai-cells = <0>;
  64                 compatible = "wlf,wm8524";
  65                 wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
  66         };
  67
  68         sound-wm8524 {
  69                 compatible = "simple-audio-card";
  70                 simple-audio-card,name = "wm8524-audio";
  71                 simple-audio-card,format = "i2s";
  72                 simple-audio-card,frame-master = <&cpudai>;
  73                 simple-audio-card,bitclock-master = <&cpudai>;
  74                 simple-audio-card,widgets =
  75                         "Line", "Left Line Out Jack",
  76                         "Line", "Right Line Out Jack";
  77                 simple-audio-card,routing =
  78                         "Left Line Out Jack", "LINEVOUTL",
  79                         "Right Line Out Jack", "LINEVOUTR";
  80
  81                 cpudai: simple-audio-card,cpu {
  82                         sound-dai = <&sai2>;
  83                 };
  84
  85                 link_codec: simple-audio-card,codec {
  86                         sound-dai = <&wm8524>;
  87                         clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
  88                 };
  89         };
  90 };
  91
  92 &A53_0 {
  93         cpu-supply = <&buck2_reg>;
  94 };
  95
  96 &A53_1 {
  97         cpu-supply = <&buck2_reg>;
  98 };
  99
 100 &A53_2 {
 101         cpu-supply = <&buck2_reg>;
 102 };
 103
 104 &A53_3 {
 105         cpu-supply = <&buck2_reg>;
 106 };
 107
 108 &ddrc {
 109         operating-points-v2 = <&ddrc_opp_table>;
 110
 111         ddrc_opp_table: opp-table {
 112                 compatible = "operating-points-v2";
 113
 114                 opp-25M {
 115                         opp-hz = /bits/ 64 <25000000>;
 116                 };
 117
 118                 opp-100M {
 119                         opp-hz = /bits/ 64 <100000000>;
 120                 };
 121
 122                 /*
 123                  * On imx8mq B0 PLL can't be bypassed so low bus is 166M
 124                  */
 125                 opp-166M {
 126                         opp-hz = /bits/ 64 <166935483>;
 127                 };
 128
 129                 opp-800M {
 130                         opp-hz = /bits/ 64 <800000000>;
 131                 };
 132         };
 133 };
 134
 135 &dphy {
 136         status = "okay";
 137 };
 138
 139 &fec1 {
 140         pinctrl-names = "default";
 141         pinctrl-0 = <&pinctrl_fec1>;
 142         phy-mode = "rgmii-id";
 143         phy-handle = <&ethphy0>;
 144         fsl,magic-packet;
 145         status = "okay";
 146
 147         mdio {
 148                 #address-cells = <1>;
 149                 #size-cells = <0>;
 150
 151                 ethphy0: ethernet-phy@0 {
 152                         compatible = "ethernet-phy-ieee802.3-c22";
 153                         reg = <0>;
 154                         reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
 155                         reset-assert-us = <10000>;
 156                 };
 157         };
 158 };
 159
 160 &gpio5 {
 161         pinctrl-names = "default";
 162         pinctrl-0 = <&pinctrl_wifi_reset>;
 163
 164         wl-reg-on-hog {
 165                 gpio-hog;
 166                 gpios = <29 GPIO_ACTIVE_HIGH>;
 167                 output-high;
 168         };
 169 };
 170
 171 &i2c1 {
 172         clock-frequency = <100000>;
 173         pinctrl-names = "default";
 174         pinctrl-0 = <&pinctrl_i2c1>;
 175         status = "okay";
 176
 177         pmic@8 {
 178                 compatible = "fsl,pfuze100";
 179                 reg = <0x8>;
 180
 181                 regulators {
 182                         sw1a_reg: sw1ab {
 183                                 regulator-min-microvolt = <825000>;
 184                                 regulator-max-microvolt = <1100000>;
 185                         };
 186
 187                         sw1c_reg: sw1c {
 188                                 regulator-min-microvolt = <825000>;
 189                                 regulator-max-microvolt = <1100000>;
 190                         };
 191
 192                         sw2_reg: sw2 {
 193                                 regulator-min-microvolt = <1100000>;
 194                                 regulator-max-microvolt = <1100000>;
 195                                 regulator-always-on;
 196                         };
 197
 198                         sw3a_reg: sw3ab {
 199                                 regulator-min-microvolt = <825000>;
 200                                 regulator-max-microvolt = <1100000>;
 201                                 regulator-always-on;
 202                         };
 203
 204                         sw4_reg: sw4 {
 205                                 regulator-min-microvolt = <1800000>;
 206                                 regulator-max-microvolt = <1800000>;
 207                                 regulator-always-on;
 208                         };
 209
 210                         swbst_reg: swbst {
 211                                 regulator-min-microvolt = <5000000>;
 212                                 regulator-max-microvolt = <5150000>;
 213                         };
 214
 215                         snvs_reg: vsnvs {
 216                                 regulator-min-microvolt = <1000000>;
 217                                 regulator-max-microvolt = <3000000>;
 218                                 regulator-always-on;
 219                         };
 220
 221                         vref_reg: vrefddr {
 222                                 regulator-always-on;
 223                         };
 224
 225                         vgen1_reg: vgen1 {
 226                                 regulator-min-microvolt = <800000>;
 227                                 regulator-max-microvolt = <1550000>;
 228                         };
 229
 230                         vgen2_reg: vgen2 {
 231                                 regulator-min-microvolt = <850000>;
 232                                 regulator-max-microvolt = <975000>;
 233                                 regulator-always-on;
 234                         };
 235
 236                         vgen3_reg: vgen3 {
 237                                 regulator-min-microvolt = <1675000>;
 238                                 regulator-max-microvolt = <1975000>;
 239                                 regulator-always-on;
 240                         };
 241
 242                         vgen4_reg: vgen4 {
 243                                 regulator-min-microvolt = <1625000>;
 244                                 regulator-max-microvolt = <1875000>;
 245                                 regulator-always-on;
 246                         };
 247
 248                         vgen5_reg: vgen5 {
 249                                 regulator-min-microvolt = <3075000>;
 250                                 regulator-max-microvolt = <3625000>;
 251                                 regulator-always-on;
 252                         };
 253
 254                         vgen6_reg: vgen6 {
 255                                 regulator-min-microvolt = <1800000>;
 256                                 regulator-max-microvolt = <3300000>;
 257                         };
 258                 };
 259         };
 260 };
 261
 262 &lcdif {
 263         status = "okay";
 264 };
 265
 266 &mipi_dsi {
 267         #address-cells = <1>;
 268         #size-cells = <0>;
 269         status = "okay";
 270
 271         panel@0 {
 272                 pinctrl-0 = <&pinctrl_mipi_dsi>;
 273                 pinctrl-names = "default";
 274                 compatible = "raydium,rm67191";
 275                 reg = <0>;
 276                 reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
 277                 dsi-lanes = <4>;
 278
 279                 port {
 280                         panel_in: endpoint {
 281                                 remote-endpoint = <&mipi_dsi_out>;
 282                         };
 283                 };
 284         };
 285
 286         ports {
 287                 port@1 {
 288                         reg = <1>;
 289                         mipi_dsi_out: endpoint {
 290                                 remote-endpoint = <&panel_in>;
 291                         };
 292                 };
 293         };
 294 };
 295
 296 &pcie0 {
 297         pinctrl-names = "default";
 298         pinctrl-0 = <&pinctrl_pcie0>;
 299         reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
 300         clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
 301                  <&clk IMX8MQ_CLK_PCIE1_AUX>,
 302                  <&clk IMX8MQ_CLK_PCIE1_PHY>,
 303                  <&pcie0_refclk>;
 304         clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
 305         status = "okay";
 306 };
 307
 308 &pgc_gpu {
 309         power-supply = <&sw1a_reg>;
 310 };
 311
 312 &qspi0 {
 313         pinctrl-names = "default";
 314         pinctrl-0 = <&pinctrl_qspi>;
 315         status = "okay";
 316
 317         n25q256a: flash@0 {
 318                 reg = <0>;
 319                 #address-cells = <1>;
 320                 #size-cells = <1>;
 321                 compatible = "micron,n25q256a", "jedec,spi-nor";
 322                 spi-max-frequency = <29000000>;
 323         };
 324 };
 325
 326 &sai2 {
 327         pinctrl-names = "default";
 328         pinctrl-0 = <&pinctrl_sai2>;
 329         assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>;
 330         assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>;
 331         assigned-clock-rates = <0>, <24576000>;
 332         status = "okay";
 333 };
 334
 335 &snvs_pwrkey {
 336         status = "okay";
 337 };
 338
 339 &uart1 {
 340         pinctrl-names = "default";
 341         pinctrl-0 = <&pinctrl_uart1>;
 342         status = "okay";
 343 };
 344
 345 &usb3_phy1 {
 346         status = "okay";
 347 };
 348
 349 &usb_dwc3_1 {
 350         dr_mode = "host";
 351         status = "okay";
 352 };
 353
 354 &usdhc1 {
 355         assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
 356         assigned-clock-rates = <400000000>;
 357         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 358         pinctrl-0 = <&pinctrl_usdhc1>;
 359         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 360         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 361         vqmmc-supply = <&sw4_reg>;
 362         bus-width = <8>;
 363         non-removable;
 364         no-sd;
 365         no-sdio;
 366         status = "okay";
 367 };
 368
 369 &usdhc2 {
 370         assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
 371         assigned-clock-rates = <200000000>;
 372         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 373         pinctrl-0 = <&pinctrl_usdhc2>;
 374         pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
 375         pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
 376         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 377         vmmc-supply = <&reg_usdhc2_vmmc>;
 378         status = "okay";
 379 };
 380
 381 &wdog1 {
 382         pinctrl-names = "default";
 383         pinctrl-0 = <&pinctrl_wdog>;
 384         fsl,ext-reset-output;
 385         status = "okay";
 386 };
 387
 388 &iomuxc {
 389         pinctrl_buck2: vddarmgrp {
 390                 fsl,pins = <
 391                         MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13              0x19
 392                 >;
 393
 394         };
 395
 396         pinctrl_fec1: fec1grp {
 397                 fsl,pins = <
 398                         MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
 399                         MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO               0x23
 400                         MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3           0x1f
 401                         MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2           0x1f
 402                         MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x1f
 403                         MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x1f
 404                         MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3           0x91
 405                         MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2           0x91
 406                         MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91
 407                         MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91
 408                         MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC           0x1f
 409                         MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC           0x91
 410                         MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 411                         MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 412                         MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9               0x19
 413                 >;
 414         };
 415
 416         pinctrl_i2c1: i2c1grp {
 417                 fsl,pins = <
 418                         MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL                  0x4000007f
 419                         MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA                  0x4000007f
 420                 >;
 421         };
 422
 423         pinctrl_ir: irgrp {
 424                 fsl,pins = <
 425                         MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12              0x4f
 426                 >;
 427         };
 428
 429         pinctrl_mipi_dsi: mipidsigrp {
 430                 fsl,pins = <
 431                         MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6              0x16
 432                 >;
 433         };
 434
 435         pinctrl_pcie0: pcie0grp {
 436                 fsl,pins = <
 437                         MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B            0x76
 438                         MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28               0x16
 439                 >;
 440         };
 441
 442         pinctrl_qspi: qspigrp {
 443                 fsl,pins = <
 444                         MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK       0x82
 445                         MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B    0x82
 446                         MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0   0x82
 447                         MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1   0x82
 448                         MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2   0x82
 449                         MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3   0x82
 450
 451                 >;
 452         };
 453
 454         pinctrl_reg_usdhc2: regusdhc2gpiogrp {
 455                 fsl,pins = <
 456                         MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19             0x41
 457                 >;
 458         };
 459
 460         pinctrl_sai2: sai2grp {
 461                 fsl,pins = <
 462                         MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC     0xd6
 463                         MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK      0xd6
 464                         MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK        0xd6
 465                         MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0    0xd6
 466                         MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8       0xd6
 467                 >;
 468         };
 469
 470         pinctrl_uart1: uart1grp {
 471                 fsl,pins = <
 472                         MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX             0x49
 473                         MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX             0x49
 474                 >;
 475         };
 476
 477         pinctrl_usdhc1: usdhc1grp {
 478                 fsl,pins = <
 479                         MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x83
 480                         MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xc3
 481                         MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xc3
 482                         MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xc3
 483                         MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xc3
 484                         MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xc3
 485                         MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xc3
 486                         MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xc3
 487                         MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xc3
 488                         MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xc3
 489                         MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x83
 490                         MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
 491                 >;
 492         };
 493
 494         pinctrl_usdhc1_100mhz: usdhc1-100grp {
 495                 fsl,pins = <
 496                         MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x8d
 497                         MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xcd
 498                         MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xcd
 499                         MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xcd
 500                         MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xcd
 501                         MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xcd
 502                         MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xcd
 503                         MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xcd
 504                         MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xcd
 505                         MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xcd
 506                         MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x8d
 507                         MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
 508                 >;
 509         };
 510
 511         pinctrl_usdhc1_200mhz: usdhc1-200grp {
 512                 fsl,pins = <
 513                         MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x9f
 514                         MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xdf
 515                         MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xdf
 516                         MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xdf
 517                         MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xdf
 518                         MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xdf
 519                         MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xdf
 520                         MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xdf
 521                         MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xdf
 522                         MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xdf
 523                         MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x9f
 524                         MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
 525                 >;
 526         };
 527
 528         pinctrl_usdhc2: usdhc2grp {
 529                 fsl,pins = <
 530                         MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x83
 531                         MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc3
 532                         MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0             0xc3
 533                         MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1             0xc3
 534                         MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2             0xc3
 535                         MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3             0xc3
 536                         MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
 537                 >;
 538         };
 539
 540         pinctrl_usdhc2_100mhz: usdhc2-100grp {
 541                 fsl,pins = <
 542                         MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x85
 543                         MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc5
 544                         MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0             0xc5
 545                         MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1             0xc5
 546                         MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2             0xc5
 547                         MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3             0xc5
 548                         MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
 549                 >;
 550         };
 551
 552         pinctrl_usdhc2_200mhz: usdhc2-200grp {
 553                 fsl,pins = <
 554                         MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x87
 555                         MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc7
 556                         MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0             0xc7
 557                         MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1             0xc7
 558                         MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2             0xc7
 559                         MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3             0xc7
 560                         MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
 561                 >;
 562         };
 563
 564         pinctrl_wdog: wdog1grp {
 565                 fsl,pins = <
 566                         MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B            0xc6
 567                 >;
 568         };
 569
 570         pinctrl_wifi_reset: wifiresetgrp {
 571                 fsl,pins = <
 572                         MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29               0x16
 573                 >;
 574         };
 575 };