1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
12 model = "NXP i.MX8MQ EVK";
13 compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
20 device_type = "memory";
21 reg = <0x00000000 0x40000000 0 0xc0000000>;
24 pcie0_refclk: pcie0-refclk {
25 compatible = "fixed-clock";
27 clock-frequency = <100000000>;
30 reg_usdhc2_vmmc: regulator-vsd-3v3 {
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_reg_usdhc2>;
33 compatible = "regulator-fixed";
34 regulator-name = "VSD_3V3";
35 regulator-min-microvolt = <3300000>;
36 regulator-max-microvolt = <3300000>;
37 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
41 buck2_reg: regulator-buck2 {
42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_buck2>;
44 compatible = "regulator-gpio";
45 regulator-name = "vdd_arm";
46 regulator-min-microvolt = <900000>;
47 regulator-max-microvolt = <1000000>;
48 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
56 compatible = "gpio-ir-receiver";
57 gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
58 pinctrl-names = "default";
59 pinctrl-0 = <&pinctrl_ir>;
63 #sound-dai-cells = <0>;
64 compatible = "wlf,wm8524";
65 wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
69 compatible = "simple-audio-card";
70 simple-audio-card,name = "wm8524-audio";
71 simple-audio-card,format = "i2s";
72 simple-audio-card,frame-master = <&cpudai>;
73 simple-audio-card,bitclock-master = <&cpudai>;
74 simple-audio-card,widgets =
75 "Line", "Left Line Out Jack",
76 "Line", "Right Line Out Jack";
77 simple-audio-card,routing =
78 "Left Line Out Jack", "LINEVOUTL",
79 "Right Line Out Jack", "LINEVOUTR";
81 cpudai: simple-audio-card,cpu {
85 link_codec: simple-audio-card,codec {
86 sound-dai = <&wm8524>;
87 clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
93 cpu-supply = <&buck2_reg>;
97 cpu-supply = <&buck2_reg>;
101 cpu-supply = <&buck2_reg>;
105 cpu-supply = <&buck2_reg>;
109 operating-points-v2 = <&ddrc_opp_table>;
111 ddrc_opp_table: opp-table {
112 compatible = "operating-points-v2";
115 opp-hz = /bits/ 64 <25000000>;
119 opp-hz = /bits/ 64 <100000000>;
123 * On imx8mq B0 PLL can't be bypassed so low bus is 166M
126 opp-hz = /bits/ 64 <166935483>;
130 opp-hz = /bits/ 64 <800000000>;
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_fec1>;
142 phy-mode = "rgmii-id";
143 phy-handle = <ðphy0>;
148 #address-cells = <1>;
151 ethphy0: ethernet-phy@0 {
152 compatible = "ethernet-phy-ieee802.3-c22";
154 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
155 reset-assert-us = <10000>;
161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_wifi_reset>;
166 gpios = <29 GPIO_ACTIVE_HIGH>;
172 clock-frequency = <100000>;
173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_i2c1>;
178 compatible = "fsl,pfuze100";
183 regulator-min-microvolt = <825000>;
184 regulator-max-microvolt = <1100000>;
188 regulator-min-microvolt = <825000>;
189 regulator-max-microvolt = <1100000>;
193 regulator-min-microvolt = <1100000>;
194 regulator-max-microvolt = <1100000>;
199 regulator-min-microvolt = <825000>;
200 regulator-max-microvolt = <1100000>;
205 regulator-min-microvolt = <1800000>;
206 regulator-max-microvolt = <1800000>;
211 regulator-min-microvolt = <5000000>;
212 regulator-max-microvolt = <5150000>;
216 regulator-min-microvolt = <1000000>;
217 regulator-max-microvolt = <3000000>;
226 regulator-min-microvolt = <800000>;
227 regulator-max-microvolt = <1550000>;
231 regulator-min-microvolt = <850000>;
232 regulator-max-microvolt = <975000>;
237 regulator-min-microvolt = <1675000>;
238 regulator-max-microvolt = <1975000>;
243 regulator-min-microvolt = <1625000>;
244 regulator-max-microvolt = <1875000>;
249 regulator-min-microvolt = <3075000>;
250 regulator-max-microvolt = <3625000>;
255 regulator-min-microvolt = <1800000>;
256 regulator-max-microvolt = <3300000>;
267 #address-cells = <1>;
272 pinctrl-0 = <&pinctrl_mipi_dsi>;
273 pinctrl-names = "default";
274 compatible = "raydium,rm67191";
276 reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
281 remote-endpoint = <&mipi_dsi_out>;
289 mipi_dsi_out: endpoint {
290 remote-endpoint = <&panel_in>;
297 pinctrl-names = "default";
298 pinctrl-0 = <&pinctrl_pcie0>;
299 reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
300 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
301 <&clk IMX8MQ_CLK_PCIE1_AUX>,
302 <&clk IMX8MQ_CLK_PCIE1_PHY>,
304 clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
309 power-supply = <&sw1a_reg>;
313 pinctrl-names = "default";
314 pinctrl-0 = <&pinctrl_qspi>;
319 #address-cells = <1>;
321 compatible = "micron,n25q256a", "jedec,spi-nor";
322 spi-max-frequency = <29000000>;
327 pinctrl-names = "default";
328 pinctrl-0 = <&pinctrl_sai2>;
329 assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>;
330 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>;
331 assigned-clock-rates = <0>, <24576000>;
340 pinctrl-names = "default";
341 pinctrl-0 = <&pinctrl_uart1>;
355 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
356 assigned-clock-rates = <400000000>;
357 pinctrl-names = "default", "state_100mhz", "state_200mhz";
358 pinctrl-0 = <&pinctrl_usdhc1>;
359 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
360 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
361 vqmmc-supply = <&sw4_reg>;
370 assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
371 assigned-clock-rates = <200000000>;
372 pinctrl-names = "default", "state_100mhz", "state_200mhz";
373 pinctrl-0 = <&pinctrl_usdhc2>;
374 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
375 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
376 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
377 vmmc-supply = <®_usdhc2_vmmc>;
382 pinctrl-names = "default";
383 pinctrl-0 = <&pinctrl_wdog>;
384 fsl,ext-reset-output;
389 pinctrl_buck2: vddarmgrp {
391 MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
396 pinctrl_fec1: fec1grp {
398 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
399 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
400 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
401 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
402 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
403 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
404 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
405 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
406 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
407 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
408 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
409 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
410 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
411 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
412 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
416 pinctrl_i2c1: i2c1grp {
418 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
419 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
425 MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x4f
429 pinctrl_mipi_dsi: mipidsigrp {
431 MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16
435 pinctrl_pcie0: pcie0grp {
437 MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76
438 MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16
442 pinctrl_qspi: qspigrp {
444 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
445 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
446 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
447 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
448 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
449 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
454 pinctrl_reg_usdhc2: regusdhc2gpiogrp {
456 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
460 pinctrl_sai2: sai2grp {
462 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
463 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
464 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
465 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
466 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
470 pinctrl_uart1: uart1grp {
472 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
473 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
477 pinctrl_usdhc1: usdhc1grp {
479 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
480 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
481 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
482 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
483 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
484 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
485 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
486 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
487 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
488 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
489 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
490 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
494 pinctrl_usdhc1_100mhz: usdhc1-100grp {
496 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
497 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
498 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
499 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
500 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
501 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
502 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
503 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
504 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
505 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
506 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
507 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
511 pinctrl_usdhc1_200mhz: usdhc1-200grp {
513 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
514 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
515 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
516 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
517 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
518 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
519 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
520 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
521 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
522 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
523 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
524 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
528 pinctrl_usdhc2: usdhc2grp {
530 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
531 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
532 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
533 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
534 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
535 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
536 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
540 pinctrl_usdhc2_100mhz: usdhc2-100grp {
542 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
543 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
544 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
545 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
546 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
547 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
548 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
552 pinctrl_usdhc2_200mhz: usdhc2-200grp {
554 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
555 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
556 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
557 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
558 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
559 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
560 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
564 pinctrl_wdog: wdog1grp {
566 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
570 pinctrl_wifi_reset: wifiresetgrp {
572 MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16