arch/arm64/boot/dts/freescale/imx8mq-evk.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright 2017 NXP
   4  * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
   5  */
   6
   7 /dts-v1/;
   8
   9 #include "imx8mq.dtsi"
  10
  11 / {
  12         model = "NXP i.MX8MQ EVK";
  13         compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
  14
  15         chosen {
  16                 stdout-path = &uart1;
  17         };
  18
  19         memory@40000000 {
  20                 device_type = "memory";
  21                 reg = <0x00000000 0x40000000 0 0xc0000000>;
  22         };
  23
  24         pcie0_refclk: pcie0-refclk {
  25                 compatible = "fixed-clock";
  26                 #clock-cells = <0>;
  27                 clock-frequency = <100000000>;
  28         };
  29
  30         reg_usdhc2_vmmc: regulator-vsd-3v3 {
  31                 pinctrl-names = "default";
  32                 pinctrl-0 = <&pinctrl_reg_usdhc2>;
  33                 compatible = "regulator-fixed";
  34                 regulator-name = "VSD_3V3";
  35                 regulator-min-microvolt = <3300000>;
  36                 regulator-max-microvolt = <3300000>;
  37                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  38                 enable-active-high;
  39         };
  40
  41         buck2_reg: regulator-buck2 {
  42                 pinctrl-names = "default";
  43                 pinctrl-0 = <&pinctrl_buck2>;
  44                 compatible = "regulator-gpio";
  45                 regulator-name = "vdd_arm";
  46                 regulator-min-microvolt = <900000>;
  47                 regulator-max-microvolt = <1000000>;
  48                 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
  49                 states = <1000000 0x0
  50                           900000 0x1>;
  51                 regulator-boot-on;
  52                 regulator-always-on;
  53         };
  54
  55         ir-receiver {
  56                 compatible = "gpio-ir-receiver";
  57                 gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
  58                 pinctrl-names = "default";
  59                 pinctrl-0 = <&pinctrl_ir>;
  60         };
  61
  62         wm8524: audio-codec {
  63                 #sound-dai-cells = <0>;
  64                 compatible = "wlf,wm8524";
  65                 wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
  66         };
  67
  68         sound-wm8524 {
  69                 compatible = "simple-audio-card";
  70                 simple-audio-card,name = "wm8524-audio";
  71                 simple-audio-card,format = "i2s";
  72                 simple-audio-card,frame-master = <&cpudai>;
  73                 simple-audio-card,bitclock-master = <&cpudai>;
  74                 simple-audio-card,widgets =
  75                         "Line", "Left Line Out Jack",
  76                         "Line", "Right Line Out Jack";
  77                 simple-audio-card,routing =
  78                         "Left Line Out Jack", "LINEVOUTL",
  79                         "Right Line Out Jack", "LINEVOUTR";
  80
  81                 cpudai: simple-audio-card,cpu {
  82                         sound-dai = <&sai2>;
  83                 };
  84
  85                 link_codec: simple-audio-card,codec {
  86                         sound-dai = <&wm8524>;
  87                         clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
  88                 };
  89         };
  90 };
  91
  92 &A53_0 {
  93         cpu-supply = <&buck2_reg>;
  94 };
  95
  96 &A53_1 {
  97         cpu-supply = <&buck2_reg>;
  98 };
  99
 100 &A53_2 {
 101         cpu-supply = <&buck2_reg>;
 102 };
 103
 104 &A53_3 {
 105         cpu-supply = <&buck2_reg>;
 106 };
 107
 108 &ddrc {
 109         operating-points-v2 = <&ddrc_opp_table>;
 110
 111         ddrc_opp_table: opp-table {
 112                 compatible = "operating-points-v2";
 113
 114                 opp-25M {
 115                         opp-hz = /bits/ 64 <25000000>;
 116                 };
 117
 118                 opp-100M {
 119                         opp-hz = /bits/ 64 <100000000>;
 120                 };
 121
 122                 /*
 123                  * On imx8mq B0 PLL can't be bypassed so low bus is 166M
 124                  */
 125                 opp-166M {
 126                         opp-hz = /bits/ 64 <166935483>;
 127                 };
 128
 129                 opp-800M {
 130                         opp-hz = /bits/ 64 <800000000>;
 131                 };
 132         };
 133 };
 134
 135 &fec1 {
 136         pinctrl-names = "default";
 137         pinctrl-0 = <&pinctrl_fec1>;
 138         phy-mode = "rgmii-id";
 139         phy-handle = <&ethphy0>;
 140         phy-reset-gpios = <&gpio1 9  GPIO_ACTIVE_LOW>;
 141         phy-reset-duration = <10>;
 142         fsl,magic-packet;
 143         status = "okay";
 144
 145         mdio {
 146                 #address-cells = <1>;
 147                 #size-cells = <0>;
 148
 149                 ethphy0: ethernet-phy@0 {
 150                         compatible = "ethernet-phy-ieee802.3-c22";
 151                         reg = <0>;
 152                 };
 153         };
 154 };
 155
 156 &gpio5 {
 157         pinctrl-names = "default";
 158         pinctrl-0 = <&pinctrl_wifi_reset>;
 159
 160         wl-reg-on {
 161                 gpio-hog;
 162                 gpios = <29 GPIO_ACTIVE_HIGH>;
 163                 output-high;
 164         };
 165 };
 166
 167 &i2c1 {
 168         clock-frequency = <100000>;
 169         pinctrl-names = "default";
 170         pinctrl-0 = <&pinctrl_i2c1>;
 171         status = "okay";
 172
 173         pmic@8 {
 174                 compatible = "fsl,pfuze100";
 175                 reg = <0x8>;
 176
 177                 regulators {
 178                         sw1a_reg: sw1ab {
 179                                 regulator-min-microvolt = <825000>;
 180                                 regulator-max-microvolt = <1100000>;
 181                         };
 182
 183                         sw1c_reg: sw1c {
 184                                 regulator-min-microvolt = <825000>;
 185                                 regulator-max-microvolt = <1100000>;
 186                         };
 187
 188                         sw2_reg: sw2 {
 189                                 regulator-min-microvolt = <1100000>;
 190                                 regulator-max-microvolt = <1100000>;
 191                                 regulator-always-on;
 192                         };
 193
 194                         sw3a_reg: sw3ab {
 195                                 regulator-min-microvolt = <825000>;
 196                                 regulator-max-microvolt = <1100000>;
 197                                 regulator-always-on;
 198                         };
 199
 200                         sw4_reg: sw4 {
 201                                 regulator-min-microvolt = <1800000>;
 202                                 regulator-max-microvolt = <1800000>;
 203                                 regulator-always-on;
 204                         };
 205
 206                         swbst_reg: swbst {
 207                                 regulator-min-microvolt = <5000000>;
 208                                 regulator-max-microvolt = <5150000>;
 209                         };
 210
 211                         snvs_reg: vsnvs {
 212                                 regulator-min-microvolt = <1000000>;
 213                                 regulator-max-microvolt = <3000000>;
 214                                 regulator-always-on;
 215                         };
 216
 217                         vref_reg: vrefddr {
 218                                 regulator-always-on;
 219                         };
 220
 221                         vgen1_reg: vgen1 {
 222                                 regulator-min-microvolt = <800000>;
 223                                 regulator-max-microvolt = <1550000>;
 224                         };
 225
 226                         vgen2_reg: vgen2 {
 227                                 regulator-min-microvolt = <850000>;
 228                                 regulator-max-microvolt = <975000>;
 229                                 regulator-always-on;
 230                         };
 231
 232                         vgen3_reg: vgen3 {
 233                                 regulator-min-microvolt = <1675000>;
 234                                 regulator-max-microvolt = <1975000>;
 235                                 regulator-always-on;
 236                         };
 237
 238                         vgen4_reg: vgen4 {
 239                                 regulator-min-microvolt = <1625000>;
 240                                 regulator-max-microvolt = <1875000>;
 241                                 regulator-always-on;
 242                         };
 243
 244                         vgen5_reg: vgen5 {
 245                                 regulator-min-microvolt = <3075000>;
 246                                 regulator-max-microvolt = <3625000>;
 247                                 regulator-always-on;
 248                         };
 249
 250                         vgen6_reg: vgen6 {
 251                                 regulator-min-microvolt = <1800000>;
 252                                 regulator-max-microvolt = <3300000>;
 253                         };
 254                 };
 255         };
 256 };
 257
 258 &pcie0 {
 259         pinctrl-names = "default";
 260         pinctrl-0 = <&pinctrl_pcie0>;
 261         reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
 262         clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
 263                  <&clk IMX8MQ_CLK_PCIE1_AUX>,
 264                  <&clk IMX8MQ_CLK_PCIE1_PHY>,
 265                  <&pcie0_refclk>;
 266         clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
 267         status = "okay";
 268 };
 269
 270 &pgc_gpu {
 271         power-supply = <&sw1a_reg>;
 272 };
 273
 274 &qspi0 {
 275         pinctrl-names = "default";
 276         pinctrl-0 = <&pinctrl_qspi>;
 277         status = "okay";
 278
 279         n25q256a: flash@0 {
 280                 reg = <0>;
 281                 #address-cells = <1>;
 282                 #size-cells = <1>;
 283                 compatible = "micron,n25q256a", "jedec,spi-nor";
 284                 spi-max-frequency = <29000000>;
 285         };
 286 };
 287
 288 &sai2 {
 289         pinctrl-names = "default";
 290         pinctrl-0 = <&pinctrl_sai2>;
 291         assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>;
 292         assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>;
 293         assigned-clock-rates = <0>, <24576000>;
 294         status = "okay";
 295 };
 296
 297 &snvs_pwrkey {
 298         status = "okay";
 299 };
 300
 301 &uart1 {
 302         pinctrl-names = "default";
 303         pinctrl-0 = <&pinctrl_uart1>;
 304         status = "okay";
 305 };
 306
 307 &usb3_phy1 {
 308         status = "okay";
 309 };
 310
 311 &usb_dwc3_1 {
 312         dr_mode = "host";
 313         status = "okay";
 314 };
 315
 316 &usdhc1 {
 317         assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
 318         assigned-clock-rates = <400000000>;
 319         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 320         pinctrl-0 = <&pinctrl_usdhc1>;
 321         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 322         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 323         vqmmc-supply = <&sw4_reg>;
 324         bus-width = <8>;
 325         non-removable;
 326         no-sd;
 327         no-sdio;
 328         status = "okay";
 329 };
 330
 331 &usdhc2 {
 332         assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
 333         assigned-clock-rates = <200000000>;
 334         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 335         pinctrl-0 = <&pinctrl_usdhc2>;
 336         pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
 337         pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
 338         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 339         vmmc-supply = <&reg_usdhc2_vmmc>;
 340         status = "okay";
 341 };
 342
 343 &wdog1 {
 344         pinctrl-names = "default";
 345         pinctrl-0 = <&pinctrl_wdog>;
 346         fsl,ext-reset-output;
 347         status = "okay";
 348 };
 349
 350 &iomuxc {
 351         pinctrl_buck2: vddarmgrp {
 352                 fsl,pins = <
 353                         MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13              0x19
 354                 >;
 355
 356         };
 357
 358         pinctrl_fec1: fec1grp {
 359                 fsl,pins = <
 360                         MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
 361                         MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO               0x23
 362                         MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3           0x1f
 363                         MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2           0x1f
 364                         MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x1f
 365                         MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x1f
 366                         MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3           0x91
 367                         MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2           0x91
 368                         MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91
 369                         MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91
 370                         MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC           0x1f
 371                         MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC           0x91
 372                         MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 373                         MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 374                         MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9               0x19
 375                 >;
 376         };
 377
 378         pinctrl_i2c1: i2c1grp {
 379                 fsl,pins = <
 380                         MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL                  0x4000007f
 381                         MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA                  0x4000007f
 382                 >;
 383         };
 384
 385         pinctrl_ir: irgrp {
 386                 fsl,pins = <
 387                         MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12              0x4f
 388                 >;
 389         };
 390
 391         pinctrl_pcie0: pcie0grp {
 392                 fsl,pins = <
 393                         MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B            0x76
 394                         MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28               0x16
 395                 >;
 396         };
 397
 398         pinctrl_qspi: qspigrp {
 399                 fsl,pins = <
 400                         MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK       0x82
 401                         MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B    0x82
 402                         MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0   0x82
 403                         MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1   0x82
 404                         MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2   0x82
 405                         MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3   0x82
 406
 407                 >;
 408         };
 409
 410         pinctrl_reg_usdhc2: regusdhc2grpgpio {
 411                 fsl,pins = <
 412                         MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19             0x41
 413                 >;
 414         };
 415
 416         pinctrl_sai2: sai2grp {
 417                 fsl,pins = <
 418                         MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC     0xd6
 419                         MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK      0xd6
 420                         MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK        0xd6
 421                         MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0    0xd6
 422                         MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8       0xd6
 423                 >;
 424         };
 425
 426         pinctrl_uart1: uart1grp {
 427                 fsl,pins = <
 428                         MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX             0x49
 429                         MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX             0x49
 430                 >;
 431         };
 432
 433         pinctrl_usdhc1: usdhc1grp {
 434                 fsl,pins = <
 435                         MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x83
 436                         MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xc3
 437                         MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xc3
 438                         MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xc3
 439                         MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xc3
 440                         MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xc3
 441                         MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xc3
 442                         MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xc3
 443                         MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xc3
 444                         MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xc3
 445                         MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x83
 446                         MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
 447                 >;
 448         };
 449
 450         pinctrl_usdhc1_100mhz: usdhc1-100grp {
 451                 fsl,pins = <
 452                         MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x8d
 453                         MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xcd
 454                         MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xcd
 455                         MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xcd
 456                         MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xcd
 457                         MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xcd
 458                         MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xcd
 459                         MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xcd
 460                         MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xcd
 461                         MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xcd
 462                         MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x8d
 463                         MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
 464                 >;
 465         };
 466
 467         pinctrl_usdhc1_200mhz: usdhc1-200grp {
 468                 fsl,pins = <
 469                         MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x9f
 470                         MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xdf
 471                         MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xdf
 472                         MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xdf
 473                         MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xdf
 474                         MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xdf
 475                         MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xdf
 476                         MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xdf
 477                         MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xdf
 478                         MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xdf
 479                         MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x9f
 480                         MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
 481                 >;
 482         };
 483
 484         pinctrl_usdhc2: usdhc2grp {
 485                 fsl,pins = <
 486                         MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x83
 487                         MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc3
 488                         MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0             0xc3
 489                         MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1             0xc3
 490                         MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2             0xc3
 491                         MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3             0xc3
 492                         MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
 493                 >;
 494         };
 495
 496         pinctrl_usdhc2_100mhz: usdhc2-100grp {
 497                 fsl,pins = <
 498                         MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x85
 499                         MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc5
 500                         MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0             0xc5
 501                         MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1             0xc5
 502                         MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2             0xc5
 503                         MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3             0xc5
 504                         MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
 505                 >;
 506         };
 507
 508         pinctrl_usdhc2_200mhz: usdhc2-200grp {
 509                 fsl,pins = <
 510                         MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x87
 511                         MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc7
 512                         MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0             0xc7
 513                         MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1             0xc7
 514                         MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2             0xc7
 515                         MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3             0xc7
 516                         MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
 517                 >;
 518         };
 519
 520         pinctrl_wdog: wdog1grp {
 521                 fsl,pins = <
 522                         MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B            0xc6
 523                 >;
 524         };
 525
 526         pinctrl_wifi_reset: wifiresetgrp {
 527                 fsl,pins = <
 528                         MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29               0x16
 529                 >;
 530         };
 531 };