arch/arm64/boot/dts/freescale/imx8mp.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <dt-bindings/clock/imx8mp-clock.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/input/input.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/thermal/thermal.h>
  11
  12 #include "imx8mp-pinfunc.h"
  13
  14 / {
  15         interrupt-parent = <&gic>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 ethernet0 = &fec;
  21                 ethernet1 = &eqos;
  22                 gpio0 = &gpio1;
  23                 gpio1 = &gpio2;
  24                 gpio2 = &gpio3;
  25                 gpio3 = &gpio4;
  26                 gpio4 = &gpio5;
  27                 i2c0 = &i2c1;
  28                 i2c1 = &i2c2;
  29                 i2c2 = &i2c3;
  30                 i2c3 = &i2c4;
  31                 i2c4 = &i2c5;
  32                 i2c5 = &i2c6;
  33                 mmc0 = &usdhc1;
  34                 mmc1 = &usdhc2;
  35                 mmc2 = &usdhc3;
  36                 serial0 = &uart1;
  37                 serial1 = &uart2;
  38                 serial2 = &uart3;
  39                 serial3 = &uart4;
  40         };
  41
  42         cpus {
  43                 #address-cells = <1>;
  44                 #size-cells = <0>;
  45
  46                 A53_0: cpu@0 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a53";
  49                         reg = <0x0>;
  50                         clock-latency = <61036>;
  51                         clocks = <&clk IMX8MP_CLK_ARM>;
  52                         enable-method = "psci";
  53                         next-level-cache = <&A53_L2>;
  54                         #cooling-cells = <2>;
  55                 };
  56
  57                 A53_1: cpu@1 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a53";
  60                         reg = <0x1>;
  61                         clock-latency = <61036>;
  62                         clocks = <&clk IMX8MP_CLK_ARM>;
  63                         enable-method = "psci";
  64                         next-level-cache = <&A53_L2>;
  65                         #cooling-cells = <2>;
  66                 };
  67
  68                 A53_2: cpu@2 {
  69                         device_type = "cpu";
  70                         compatible = "arm,cortex-a53";
  71                         reg = <0x2>;
  72                         clock-latency = <61036>;
  73                         clocks = <&clk IMX8MP_CLK_ARM>;
  74                         enable-method = "psci";
  75                         next-level-cache = <&A53_L2>;
  76                         #cooling-cells = <2>;
  77                 };
  78
  79                 A53_3: cpu@3 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a53";
  82                         reg = <0x3>;
  83                         clock-latency = <61036>;
  84                         clocks = <&clk IMX8MP_CLK_ARM>;
  85                         enable-method = "psci";
  86                         next-level-cache = <&A53_L2>;
  87                         #cooling-cells = <2>;
  88                 };
  89
  90                 A53_L2: l2-cache0 {
  91                         compatible = "cache";
  92                 };
  93         };
  94
  95         osc_32k: clock-osc-32k {
  96                 compatible = "fixed-clock";
  97                 #clock-cells = <0>;
  98                 clock-frequency = <32768>;
  99                 clock-output-names = "osc_32k";
 100         };
 101
 102         osc_24m: clock-osc-24m {
 103                 compatible = "fixed-clock";
 104                 #clock-cells = <0>;
 105                 clock-frequency = <24000000>;
 106                 clock-output-names = "osc_24m";
 107         };
 108
 109         clk_ext1: clock-ext1 {
 110                 compatible = "fixed-clock";
 111                 #clock-cells = <0>;
 112                 clock-frequency = <133000000>;
 113                 clock-output-names = "clk_ext1";
 114         };
 115
 116         clk_ext2: clock-ext2 {
 117                 compatible = "fixed-clock";
 118                 #clock-cells = <0>;
 119                 clock-frequency = <133000000>;
 120                 clock-output-names = "clk_ext2";
 121         };
 122
 123         clk_ext3: clock-ext3 {
 124                 compatible = "fixed-clock";
 125                 #clock-cells = <0>;
 126                 clock-frequency = <133000000>;
 127                 clock-output-names = "clk_ext3";
 128         };
 129
 130         clk_ext4: clock-ext4 {
 131                 compatible = "fixed-clock";
 132                 #clock-cells = <0>;
 133                 clock-frequency= <133000000>;
 134                 clock-output-names = "clk_ext4";
 135         };
 136
 137         pmu {
 138                 compatible = "arm,cortex-a53-pmu";
 139                 interrupts = <GIC_PPI 7
 140                              (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 141                 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
 142         };
 143
 144         psci {
 145                 compatible = "arm,psci-1.0";
 146                 method = "smc";
 147         };
 148
 149         thermal-zones {
 150                 cpu-thermal {
 151                         polling-delay-passive = <250>;
 152                         polling-delay = <2000>;
 153                         thermal-sensors = <&tmu 0>;
 154                         trips {
 155                                 cpu_alert0: trip0 {
 156                                         temperature = <85000>;
 157                                         hysteresis = <2000>;
 158                                         type = "passive";
 159                                 };
 160
 161                                 cpu_crit0: trip1 {
 162                                         temperature = <95000>;
 163                                         hysteresis = <2000>;
 164                                         type = "critical";
 165                                 };
 166                         };
 167
 168                         cooling-maps {
 169                                 map0 {
 170                                         trip = <&cpu_alert0>;
 171                                         cooling-device =
 172                                                 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 173                                                 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 174                                                 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 175                                                 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 176                                 };
 177                         };
 178                 };
 179
 180                 soc-thermal {
 181                         polling-delay-passive = <250>;
 182                         polling-delay = <2000>;
 183                         thermal-sensors = <&tmu 1>;
 184                         trips {
 185                                 soc_alert0: trip0 {
 186                                         temperature = <85000>;
 187                                         hysteresis = <2000>;
 188                                         type = "passive";
 189                                 };
 190
 191                                 soc_crit0: trip1 {
 192                                         temperature = <95000>;
 193                                         hysteresis = <2000>;
 194                                         type = "critical";
 195                                 };
 196                         };
 197
 198                         cooling-maps {
 199                                 map0 {
 200                                         trip = <&soc_alert0>;
 201                                         cooling-device =
 202                                                 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 203                                                 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 204                                                 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 205                                                 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 206                                 };
 207                         };
 208                 };
 209         };
 210
 211         timer {
 212                 compatible = "arm,armv8-timer";
 213                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 214                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 215                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 216                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 217                 clock-frequency = <8000000>;
 218                 arm,no-tick-in-suspend;
 219         };
 220
 221         soc@0 {
 222                 compatible = "fsl,imx8mp-soc", "simple-bus";
 223                 #address-cells = <1>;
 224                 #size-cells = <1>;
 225                 ranges = <0x0 0x0 0x0 0x3e000000>;
 226                 nvmem-cells = <&imx8mp_uid>;
 227                 nvmem-cell-names = "soc_unique_id";
 228
 229                 aips1: bus@30000000 {
 230                         compatible = "fsl,aips-bus", "simple-bus";
 231                         reg = <0x30000000 0x400000>;
 232                         #address-cells = <1>;
 233                         #size-cells = <1>;
 234                         ranges;
 235
 236                         gpio1: gpio@30200000 {
 237                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 238                                 reg = <0x30200000 0x10000>;
 239                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 240                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 241                                 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
 242                                 gpio-controller;
 243                                 #gpio-cells = <2>;
 244                                 interrupt-controller;
 245                                 #interrupt-cells = <2>;
 246                                 gpio-ranges = <&iomuxc 0 5 30>;
 247                         };
 248
 249                         gpio2: gpio@30210000 {
 250                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 251                                 reg = <0x30210000 0x10000>;
 252                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 253                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 254                                 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
 255                                 gpio-controller;
 256                                 #gpio-cells = <2>;
 257                                 interrupt-controller;
 258                                 #interrupt-cells = <2>;
 259                                 gpio-ranges = <&iomuxc 0 35 21>;
 260                         };
 261
 262                         gpio3: gpio@30220000 {
 263                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 264                                 reg = <0x30220000 0x10000>;
 265                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 266                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 267                                 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
 268                                 gpio-controller;
 269                                 #gpio-cells = <2>;
 270                                 interrupt-controller;
 271                                 #interrupt-cells = <2>;
 272                                 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
 273                         };
 274
 275                         gpio4: gpio@30230000 {
 276                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 277                                 reg = <0x30230000 0x10000>;
 278                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 279                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 280                                 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
 281                                 gpio-controller;
 282                                 #gpio-cells = <2>;
 283                                 interrupt-controller;
 284                                 #interrupt-cells = <2>;
 285                                 gpio-ranges = <&iomuxc 0 82 32>;
 286                         };
 287
 288                         gpio5: gpio@30240000 {
 289                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 290                                 reg = <0x30240000 0x10000>;
 291                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 292                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 293                                 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
 294                                 gpio-controller;
 295                                 #gpio-cells = <2>;
 296                                 interrupt-controller;
 297                                 #interrupt-cells = <2>;
 298                                 gpio-ranges = <&iomuxc 0 114 30>;
 299                         };
 300
 301                         tmu: tmu@30260000 {
 302                                 compatible = "fsl,imx8mp-tmu";
 303                                 reg = <0x30260000 0x10000>;
 304                                 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
 305                                 #thermal-sensor-cells = <1>;
 306                         };
 307
 308                         wdog1: watchdog@30280000 {
 309                                 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
 310                                 reg = <0x30280000 0x10000>;
 311                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 312                                 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
 313                                 status = "disabled";
 314                         };
 315
 316                         wdog2: watchdog@30290000 {
 317                                 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
 318                                 reg = <0x30290000 0x10000>;
 319                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 320                                 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>;
 321                                 status = "disabled";
 322                         };
 323
 324                         wdog3: watchdog@302a0000 {
 325                                 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
 326                                 reg = <0x302a0000 0x10000>;
 327                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 328                                 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>;
 329                                 status = "disabled";
 330                         };
 331
 332                         iomuxc: pinctrl@30330000 {
 333                                 compatible = "fsl,imx8mp-iomuxc";
 334                                 reg = <0x30330000 0x10000>;
 335                         };
 336
 337                         gpr: iomuxc-gpr@30340000 {
 338                                 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
 339                                 reg = <0x30340000 0x10000>;
 340                         };
 341
 342                         ocotp: efuse@30350000 {
 343                                 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
 344                                 reg = <0x30350000 0x10000>;
 345                                 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
 346                                 /* For nvmem subnodes */
 347                                 #address-cells = <1>;
 348                                 #size-cells = <1>;
 349
 350                                 imx8mp_uid: unique-id@420 {
 351                                         reg = <0x8 0x8>;
 352                                 };
 353
 354                                 cpu_speed_grade: speed-grade@10 {
 355                                         reg = <0x10 4>;
 356                                 };
 357
 358                                 eth_mac1: mac-address@90 {
 359                                         reg = <0x90 6>;
 360                                 };
 361                         };
 362
 363                         anatop: anatop@30360000 {
 364                                 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
 365                                              "syscon";
 366                                 reg = <0x30360000 0x10000>;
 367                         };
 368
 369                         snvs: snvs@30370000 {
 370                                 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
 371                                 reg = <0x30370000 0x10000>;
 372
 373                                 snvs_rtc: snvs-rtc-lp {
 374                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 375                                         regmap =<&snvs>;
 376                                         offset = <0x34>;
 377                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 378                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 379                                         clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
 380                                         clock-names = "snvs-rtc";
 381                                 };
 382
 383                                 snvs_pwrkey: snvs-powerkey {
 384                                         compatible = "fsl,sec-v4.0-pwrkey";
 385                                         regmap = <&snvs>;
 386                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 387                                         clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
 388                                         clock-names = "snvs-pwrkey";
 389                                         linux,keycode = <KEY_POWER>;
 390                                         wakeup-source;
 391                                         status = "disabled";
 392                                 };
 393                         };
 394
 395                         clk: clock-controller@30380000 {
 396                                 compatible = "fsl,imx8mp-ccm";
 397                                 reg = <0x30380000 0x10000>;
 398                                 #clock-cells = <1>;
 399                                 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
 400                                          <&clk_ext3>, <&clk_ext4>;
 401                                 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
 402                                               "clk_ext3", "clk_ext4";
 403                                 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
 404                                                   <&clk IMX8MP_CLK_A53_CORE>,
 405                                                   <&clk IMX8MP_CLK_NOC>,
 406                                                   <&clk IMX8MP_CLK_NOC_IO>,
 407                                                   <&clk IMX8MP_CLK_GIC>,
 408                                                   <&clk IMX8MP_CLK_AUDIO_AHB>,
 409                                                   <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
 410                                                   <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>,
 411                                                   <&clk IMX8MP_AUDIO_PLL1>,
 412                                                   <&clk IMX8MP_AUDIO_PLL2>;
 413                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
 414                                                          <&clk IMX8MP_ARM_PLL_OUT>,
 415                                                          <&clk IMX8MP_SYS_PLL2_1000M>,
 416                                                          <&clk IMX8MP_SYS_PLL1_800M>,
 417                                                          <&clk IMX8MP_SYS_PLL2_500M>,
 418                                                          <&clk IMX8MP_SYS_PLL1_800M>,
 419                                                          <&clk IMX8MP_SYS_PLL1_800M>;
 420                                 assigned-clock-rates = <0>, <0>,
 421                                                        <1000000000>,
 422                                                        <800000000>,
 423                                                        <500000000>,
 424                                                        <400000000>,
 425                                                        <800000000>,
 426                                                        <400000000>,
 427                                                        <393216000>,
 428                                                        <361267200>;
 429                         };
 430
 431                         src: reset-controller@30390000 {
 432                                 compatible = "fsl,imx8mp-src", "syscon";
 433                                 reg = <0x30390000 0x10000>;
 434                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 435                                 #reset-cells = <1>;
 436                         };
 437                 };
 438
 439                 aips2: bus@30400000 {
 440                         compatible = "fsl,aips-bus", "simple-bus";
 441                         reg = <0x30400000 0x400000>;
 442                         #address-cells = <1>;
 443                         #size-cells = <1>;
 444                         ranges;
 445
 446                         pwm1: pwm@30660000 {
 447                                 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
 448                                 reg = <0x30660000 0x10000>;
 449                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 450                                 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
 451                                          <&clk IMX8MP_CLK_PWM1_ROOT>;
 452                                 clock-names = "ipg", "per";
 453                                 #pwm-cells = <2>;
 454                                 status = "disabled";
 455                         };
 456
 457                         pwm2: pwm@30670000 {
 458                                 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
 459                                 reg = <0x30670000 0x10000>;
 460                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 461                                 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
 462                                          <&clk IMX8MP_CLK_PWM2_ROOT>;
 463                                 clock-names = "ipg", "per";
 464                                 #pwm-cells = <2>;
 465                                 status = "disabled";
 466                         };
 467
 468                         pwm3: pwm@30680000 {
 469                                 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
 470                                 reg = <0x30680000 0x10000>;
 471                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 472                                 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
 473                                          <&clk IMX8MP_CLK_PWM3_ROOT>;
 474                                 clock-names = "ipg", "per";
 475                                 #pwm-cells = <2>;
 476                                 status = "disabled";
 477                         };
 478
 479                         pwm4: pwm@30690000 {
 480                                 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
 481                                 reg = <0x30690000 0x10000>;
 482                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 483                                 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
 484                                          <&clk IMX8MP_CLK_PWM4_ROOT>;
 485                                 clock-names = "ipg", "per";
 486                                 #pwm-cells = <2>;
 487                                 status = "disabled";
 488                         };
 489
 490                         system_counter: timer@306a0000 {
 491                                 compatible = "nxp,sysctr-timer";
 492                                 reg = <0x306a0000 0x20000>;
 493                                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 494                                 clocks = <&osc_24m>;
 495                                 clock-names = "per";
 496                         };
 497                 };
 498
 499                 aips3: bus@30800000 {
 500                         compatible = "fsl,aips-bus", "simple-bus";
 501                         reg = <0x30800000 0x400000>;
 502                         #address-cells = <1>;
 503                         #size-cells = <1>;
 504                         ranges;
 505
 506                         ecspi1: spi@30820000 {
 507                                 #address-cells = <1>;
 508                                 #size-cells = <0>;
 509                                 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
 510                                 reg = <0x30820000 0x10000>;
 511                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 512                                 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
 513                                          <&clk IMX8MP_CLK_ECSPI1_ROOT>;
 514                                 clock-names = "ipg", "per";
 515                                 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
 516                                 dma-names = "rx", "tx";
 517                                 status = "disabled";
 518                         };
 519
 520                         ecspi2: spi@30830000 {
 521                                 #address-cells = <1>;
 522                                 #size-cells = <0>;
 523                                 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
 524                                 reg = <0x30830000 0x10000>;
 525                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 526                                 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
 527                                          <&clk IMX8MP_CLK_ECSPI2_ROOT>;
 528                                 clock-names = "ipg", "per";
 529                                 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
 530                                 dma-names = "rx", "tx";
 531                                 status = "disabled";
 532                         };
 533
 534                         ecspi3: spi@30840000 {
 535                                 #address-cells = <1>;
 536                                 #size-cells = <0>;
 537                                 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
 538                                 reg = <0x30840000 0x10000>;
 539                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 540                                 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
 541                                          <&clk IMX8MP_CLK_ECSPI3_ROOT>;
 542                                 clock-names = "ipg", "per";
 543                                 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
 544                                 dma-names = "rx", "tx";
 545                                 status = "disabled";
 546                         };
 547
 548                         uart1: serial@30860000 {
 549                                 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
 550                                 reg = <0x30860000 0x10000>;
 551                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 552                                 clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
 553                                          <&clk IMX8MP_CLK_UART1_ROOT>;
 554                                 clock-names = "ipg", "per";
 555                                 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
 556                                 dma-names = "rx", "tx";
 557                                 status = "disabled";
 558                         };
 559
 560                         uart3: serial@30880000 {
 561                                 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
 562                                 reg = <0x30880000 0x10000>;
 563                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 564                                 clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
 565                                          <&clk IMX8MP_CLK_UART3_ROOT>;
 566                                 clock-names = "ipg", "per";
 567                                 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
 568                                 dma-names = "rx", "tx";
 569                                 status = "disabled";
 570                         };
 571
 572                         uart2: serial@30890000 {
 573                                 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
 574                                 reg = <0x30890000 0x10000>;
 575                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 576                                 clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
 577                                          <&clk IMX8MP_CLK_UART2_ROOT>;
 578                                 clock-names = "ipg", "per";
 579                                 status = "disabled";
 580                         };
 581
 582                         flexcan1: can@308c0000 {
 583                                 compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan";
 584                                 reg = <0x308c0000 0x10000>;
 585                                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 586                                 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
 587                                          <&clk IMX8MP_CLK_CAN1_ROOT>;
 588                                 clock-names = "ipg", "per";
 589                                 assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
 590                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
 591                                 assigned-clock-rates = <40000000>;
 592                                 fsl,clk-source = /bits/ 8 <0>;
 593                                 fsl,stop-mode = <&gpr 0x10 4>;
 594                                 status = "disabled";
 595                         };
 596
 597                         flexcan2: can@308d0000 {
 598                                 compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan";
 599                                 reg = <0x308d0000 0x10000>;
 600                                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 601                                 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
 602                                          <&clk IMX8MP_CLK_CAN2_ROOT>;
 603                                 clock-names = "ipg", "per";
 604                                 assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
 605                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
 606                                 assigned-clock-rates = <40000000>;
 607                                 fsl,clk-source = /bits/ 8 <0>;
 608                                 fsl,stop-mode = <&gpr 0x10 5>;
 609                                 status = "disabled";
 610                         };
 611
 612                         crypto: crypto@30900000 {
 613                                 compatible = "fsl,sec-v4.0";
 614                                 #address-cells = <1>;
 615                                 #size-cells = <1>;
 616                                 reg = <0x30900000 0x40000>;
 617                                 ranges = <0 0x30900000 0x40000>;
 618                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 619                                 clocks = <&clk IMX8MP_CLK_AHB>,
 620                                          <&clk IMX8MP_CLK_IPG_ROOT>;
 621                                 clock-names = "aclk", "ipg";
 622
 623                                 sec_jr0: jr@1000 {
 624                                         compatible = "fsl,sec-v4.0-job-ring";
 625                                         reg = <0x1000 0x1000>;
 626                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 627                                 };
 628
 629                                 sec_jr1: jr@2000 {
 630                                         compatible = "fsl,sec-v4.0-job-ring";
 631                                         reg = <0x2000 0x1000>;
 632                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 633                                 };
 634
 635                                 sec_jr2: jr@3000 {
 636                                         compatible = "fsl,sec-v4.0-job-ring";
 637                                         reg = <0x3000 0x1000>;
 638                                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 639                                 };
 640                         };
 641
 642                         i2c1: i2c@30a20000 {
 643                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
 644                                 #address-cells = <1>;
 645                                 #size-cells = <0>;
 646                                 reg = <0x30a20000 0x10000>;
 647                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 648                                 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>;
 649                                 status = "disabled";
 650                         };
 651
 652                         i2c2: i2c@30a30000 {
 653                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
 654                                 #address-cells = <1>;
 655                                 #size-cells = <0>;
 656                                 reg = <0x30a30000 0x10000>;
 657                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 658                                 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>;
 659                                 status = "disabled";
 660                         };
 661
 662                         i2c3: i2c@30a40000 {
 663                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
 664                                 #address-cells = <1>;
 665                                 #size-cells = <0>;
 666                                 reg = <0x30a40000 0x10000>;
 667                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 668                                 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
 669                                 status = "disabled";
 670                         };
 671
 672                         i2c4: i2c@30a50000 {
 673                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
 674                                 #address-cells = <1>;
 675                                 #size-cells = <0>;
 676                                 reg = <0x30a50000 0x10000>;
 677                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 678                                 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>;
 679                                 status = "disabled";
 680                         };
 681
 682                         uart4: serial@30a60000 {
 683                                 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
 684                                 reg = <0x30a60000 0x10000>;
 685                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 686                                 clocks = <&clk IMX8MP_CLK_UART4_ROOT>,
 687                                          <&clk IMX8MP_CLK_UART4_ROOT>;
 688                                 clock-names = "ipg", "per";
 689                                 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
 690                                 dma-names = "rx", "tx";
 691                                 status = "disabled";
 692                         };
 693
 694                         mu: mailbox@30aa0000 {
 695                                 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
 696                                 reg = <0x30aa0000 0x10000>;
 697                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 698                                 clocks = <&clk IMX8MP_CLK_MU_ROOT>;
 699                                 #mbox-cells = <2>;
 700                         };
 701
 702                         i2c5: i2c@30ad0000 {
 703                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
 704                                 #address-cells = <1>;
 705                                 #size-cells = <0>;
 706                                 reg = <0x30ad0000 0x10000>;
 707                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 708                                 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>;
 709                                 status = "disabled";
 710                         };
 711
 712                         i2c6: i2c@30ae0000 {
 713                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
 714                                 #address-cells = <1>;
 715                                 #size-cells = <0>;
 716                                 reg = <0x30ae0000 0x10000>;
 717                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 718                                 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>;
 719                                 status = "disabled";
 720                         };
 721
 722                         usdhc1: mmc@30b40000 {
 723                                 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
 724                                 reg = <0x30b40000 0x10000>;
 725                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 726                                 clocks = <&clk IMX8MP_CLK_DUMMY>,
 727                                          <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
 728                                          <&clk IMX8MP_CLK_USDHC1_ROOT>;
 729                                 clock-names = "ipg", "ahb", "per";
 730                                 fsl,tuning-start-tap = <20>;
 731                                 fsl,tuning-step= <2>;
 732                                 bus-width = <4>;
 733                                 status = "disabled";
 734                         };
 735
 736                         usdhc2: mmc@30b50000 {
 737                                 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
 738                                 reg = <0x30b50000 0x10000>;
 739                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 740                                 clocks = <&clk IMX8MP_CLK_DUMMY>,
 741                                          <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
 742                                          <&clk IMX8MP_CLK_USDHC2_ROOT>;
 743                                 clock-names = "ipg", "ahb", "per";
 744                                 fsl,tuning-start-tap = <20>;
 745                                 fsl,tuning-step= <2>;
 746                                 bus-width = <4>;
 747                                 status = "disabled";
 748                         };
 749
 750                         usdhc3: mmc@30b60000 {
 751                                 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
 752                                 reg = <0x30b60000 0x10000>;
 753                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 754                                 clocks = <&clk IMX8MP_CLK_DUMMY>,
 755                                          <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
 756                                          <&clk IMX8MP_CLK_USDHC3_ROOT>;
 757                                 clock-names = "ipg", "ahb", "per";
 758                                 fsl,tuning-start-tap = <20>;
 759                                 fsl,tuning-step= <2>;
 760                                 bus-width = <4>;
 761                                 status = "disabled";
 762                         };
 763
 764                         sdma1: dma-controller@30bd0000 {
 765                                 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
 766                                 reg = <0x30bd0000 0x10000>;
 767                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 768                                 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
 769                                          <&clk IMX8MP_CLK_AHB>;
 770                                 clock-names = "ipg", "ahb";
 771                                 #dma-cells = <3>;
 772                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
 773                         };
 774
 775                         fec: ethernet@30be0000 {
 776                                 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
 777                                 reg = <0x30be0000 0x10000>;
 778                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 779                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 780                                              <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 781                                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 782                                 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
 783                                          <&clk IMX8MP_CLK_SIM_ENET_ROOT>,
 784                                          <&clk IMX8MP_CLK_ENET_TIMER>,
 785                                          <&clk IMX8MP_CLK_ENET_REF>,
 786                                          <&clk IMX8MP_CLK_ENET_PHY_REF>;
 787                                 clock-names = "ipg", "ahb", "ptp",
 788                                               "enet_clk_ref", "enet_out";
 789                                 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
 790                                                   <&clk IMX8MP_CLK_ENET_TIMER>,
 791                                                   <&clk IMX8MP_CLK_ENET_REF>,
 792                                                   <&clk IMX8MP_CLK_ENET_PHY_REF>;
 793                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
 794                                                          <&clk IMX8MP_SYS_PLL2_100M>,
 795                                                          <&clk IMX8MP_SYS_PLL2_125M>,
 796                                                          <&clk IMX8MP_SYS_PLL2_50M>;
 797                                 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
 798                                 fsl,num-tx-queues = <3>;
 799                                 fsl,num-rx-queues = <3>;
 800                                 nvmem-cells = <&eth_mac1>;
 801                                 nvmem-cell-names = "mac-address";
 802                                 fsl,stop-mode = <&gpr 0x10 3>;
 803                                 nvmem_macaddr_swap;
 804                                 status = "disabled";
 805                         };
 806
 807                         eqos: ethernet@30bf0000 {
 808                                 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
 809                                 reg = <0x30bf0000 0x10000>;
 810                                 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 811                                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
 812                                 interrupt-names = "eth_wake_irq", "macirq";
 813                                 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
 814                                          <&clk IMX8MP_CLK_QOS_ENET_ROOT>,
 815                                          <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
 816                                          <&clk IMX8MP_CLK_ENET_QOS>;
 817                                 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
 818                                 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
 819                                                   <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
 820                                                   <&clk IMX8MP_CLK_ENET_QOS>;
 821                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
 822                                                          <&clk IMX8MP_SYS_PLL2_100M>,
 823                                                          <&clk IMX8MP_SYS_PLL2_125M>;
 824                                 assigned-clock-rates = <0>, <100000000>, <125000000>;
 825                                 intf_mode = <&gpr 0x4>;
 826                                 status = "disabled";
 827                         };
 828                 };
 829
 830                 gic: interrupt-controller@38800000 {
 831                         compatible = "arm,gic-v3";
 832                         reg = <0x38800000 0x10000>,
 833                               <0x38880000 0xc0000>;
 834                         #interrupt-cells = <3>;
 835                         interrupt-controller;
 836                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 837                         interrupt-parent = <&gic>;
 838                 };
 839
 840                 ddr-pmu@3d800000 {
 841                         compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
 842                         reg = <0x3d800000 0x400000>;
 843                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 844                 };
 845
 846                 usb3_phy0: usb-phy@381f0040 {
 847                         compatible = "fsl,imx8mp-usb-phy";
 848                         reg = <0x381f0040 0x40>;
 849                         clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
 850                         clock-names = "phy";
 851                         assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
 852                         assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
 853                         #phy-cells = <0>;
 854                         status = "disabled";
 855                 };
 856
 857                 usb3_0: usb@32f10100 {
 858                         compatible = "fsl,imx8mp-dwc3";
 859                         reg = <0x32f10100 0x8>;
 860                         clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
 861                                  <&clk IMX8MP_CLK_USB_ROOT>;
 862                         clock-names = "hsio", "suspend";
 863                         interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 864                         #address-cells = <1>;
 865                         #size-cells = <1>;
 866                         dma-ranges = <0x40000000 0x40000000 0xc0000000>;
 867                         ranges;
 868                         status = "disabled";
 869
 870                         usb_dwc3_0: usb@38100000 {
 871                                 compatible = "snps,dwc3";
 872                                 reg = <0x38100000 0x10000>;
 873                                 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
 874                                          <&clk IMX8MP_CLK_USB_CORE_REF>,
 875                                          <&clk IMX8MP_CLK_USB_ROOT>;
 876                                 clock-names = "bus_early", "ref", "suspend";
 877                                 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
 878                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
 879                                 assigned-clock-rates = <500000000>;
 880                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 881                                 phys = <&usb3_phy0>, <&usb3_phy0>;
 882                                 phy-names = "usb2-phy", "usb3-phy";
 883                                 snps,dis-u2-freeclk-exists-quirk;
 884                         };
 885
 886                 };
 887
 888                 usb3_phy1: usb-phy@382f0040 {
 889                         compatible = "fsl,imx8mp-usb-phy";
 890                         reg = <0x382f0040 0x40>;
 891                         clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
 892                         clock-names = "phy";
 893                         assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
 894                         assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
 895                         #phy-cells = <0>;
 896                 };
 897
 898                 usb3_1: usb@32f10108 {
 899                         compatible = "fsl,imx8mp-dwc3";
 900                         reg = <0x32f10108 0x8>;
 901                         clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
 902                                  <&clk IMX8MP_CLK_USB_ROOT>;
 903                         clock-names = "hsio", "suspend";
 904                         interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 905                         #address-cells = <1>;
 906                         #size-cells = <1>;
 907                         dma-ranges = <0x40000000 0x40000000 0xc0000000>;
 908                         ranges;
 909                         status = "disabled";
 910
 911                         usb_dwc3_1: usb@38200000 {
 912                                 compatible = "snps,dwc3";
 913                                 reg = <0x38200000 0x10000>;
 914                                 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
 915                                          <&clk IMX8MP_CLK_USB_CORE_REF>,
 916                                          <&clk IMX8MP_CLK_USB_ROOT>;
 917                                 clock-names = "bus_early", "ref", "suspend";
 918                                 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
 919                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
 920                                 assigned-clock-rates = <500000000>;
 921                                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 922                                 phys = <&usb3_phy1>, <&usb3_phy1>;
 923                                 phy-names = "usb2-phy", "usb3-phy";
 924                                 snps,dis-u2-freeclk-exists-quirk;
 925                         };
 926                 };
 927         };
 928 };