1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx8mp-pinfunc.h"
15 interrupt-parent = <&gic>;
48 compatible = "arm,cortex-a53";
50 clock-latency = <61036>;
51 clocks = <&clk IMX8MP_CLK_ARM>;
52 enable-method = "psci";
53 next-level-cache = <&A53_L2>;
59 compatible = "arm,cortex-a53";
61 clock-latency = <61036>;
62 clocks = <&clk IMX8MP_CLK_ARM>;
63 enable-method = "psci";
64 next-level-cache = <&A53_L2>;
70 compatible = "arm,cortex-a53";
72 clock-latency = <61036>;
73 clocks = <&clk IMX8MP_CLK_ARM>;
74 enable-method = "psci";
75 next-level-cache = <&A53_L2>;
81 compatible = "arm,cortex-a53";
83 clock-latency = <61036>;
84 clocks = <&clk IMX8MP_CLK_ARM>;
85 enable-method = "psci";
86 next-level-cache = <&A53_L2>;
95 osc_32k: clock-osc-32k {
96 compatible = "fixed-clock";
98 clock-frequency = <32768>;
99 clock-output-names = "osc_32k";
102 osc_24m: clock-osc-24m {
103 compatible = "fixed-clock";
105 clock-frequency = <24000000>;
106 clock-output-names = "osc_24m";
109 clk_ext1: clock-ext1 {
110 compatible = "fixed-clock";
112 clock-frequency = <133000000>;
113 clock-output-names = "clk_ext1";
116 clk_ext2: clock-ext2 {
117 compatible = "fixed-clock";
119 clock-frequency = <133000000>;
120 clock-output-names = "clk_ext2";
123 clk_ext3: clock-ext3 {
124 compatible = "fixed-clock";
126 clock-frequency = <133000000>;
127 clock-output-names = "clk_ext3";
130 clk_ext4: clock-ext4 {
131 compatible = "fixed-clock";
133 clock-frequency= <133000000>;
134 clock-output-names = "clk_ext4";
138 compatible = "arm,cortex-a53-pmu";
139 interrupts = <GIC_PPI 7
140 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
141 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
145 compatible = "arm,psci-1.0";
151 polling-delay-passive = <250>;
152 polling-delay = <2000>;
153 thermal-sensors = <&tmu 0>;
156 temperature = <85000>;
162 temperature = <95000>;
170 trip = <&cpu_alert0>;
172 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
173 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
174 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
175 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
181 polling-delay-passive = <250>;
182 polling-delay = <2000>;
183 thermal-sensors = <&tmu 1>;
186 temperature = <85000>;
192 temperature = <95000>;
200 trip = <&soc_alert0>;
202 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
203 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
204 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
205 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
212 compatible = "arm,armv8-timer";
213 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
214 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
215 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
216 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
217 clock-frequency = <8000000>;
218 arm,no-tick-in-suspend;
222 compatible = "fsl,imx8mp-soc", "simple-bus";
223 #address-cells = <1>;
225 ranges = <0x0 0x0 0x0 0x3e000000>;
226 nvmem-cells = <&imx8mp_uid>;
227 nvmem-cell-names = "soc_unique_id";
229 aips1: bus@30000000 {
230 compatible = "fsl,aips-bus", "simple-bus";
231 reg = <0x30000000 0x400000>;
232 #address-cells = <1>;
236 gpio1: gpio@30200000 {
237 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
238 reg = <0x30200000 0x10000>;
239 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
244 interrupt-controller;
245 #interrupt-cells = <2>;
246 gpio-ranges = <&iomuxc 0 5 30>;
249 gpio2: gpio@30210000 {
250 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
251 reg = <0x30210000 0x10000>;
252 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
257 interrupt-controller;
258 #interrupt-cells = <2>;
259 gpio-ranges = <&iomuxc 0 35 21>;
262 gpio3: gpio@30220000 {
263 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
264 reg = <0x30220000 0x10000>;
265 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
270 interrupt-controller;
271 #interrupt-cells = <2>;
272 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
275 gpio4: gpio@30230000 {
276 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
277 reg = <0x30230000 0x10000>;
278 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
283 interrupt-controller;
284 #interrupt-cells = <2>;
285 gpio-ranges = <&iomuxc 0 82 32>;
288 gpio5: gpio@30240000 {
289 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
290 reg = <0x30240000 0x10000>;
291 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
296 interrupt-controller;
297 #interrupt-cells = <2>;
298 gpio-ranges = <&iomuxc 0 114 30>;
302 compatible = "fsl,imx8mp-tmu";
303 reg = <0x30260000 0x10000>;
304 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
305 #thermal-sensor-cells = <1>;
308 wdog1: watchdog@30280000 {
309 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
310 reg = <0x30280000 0x10000>;
311 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
312 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
316 wdog2: watchdog@30290000 {
317 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
318 reg = <0x30290000 0x10000>;
319 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
320 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>;
324 wdog3: watchdog@302a0000 {
325 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
326 reg = <0x302a0000 0x10000>;
327 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>;
332 iomuxc: pinctrl@30330000 {
333 compatible = "fsl,imx8mp-iomuxc";
334 reg = <0x30330000 0x10000>;
337 gpr: iomuxc-gpr@30340000 {
338 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
339 reg = <0x30340000 0x10000>;
342 ocotp: efuse@30350000 {
343 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
344 reg = <0x30350000 0x10000>;
345 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
346 /* For nvmem subnodes */
347 #address-cells = <1>;
350 imx8mp_uid: unique-id@420 {
354 cpu_speed_grade: speed-grade@10 {
358 eth_mac1: mac-address@90 {
363 anatop: anatop@30360000 {
364 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
366 reg = <0x30360000 0x10000>;
369 snvs: snvs@30370000 {
370 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
371 reg = <0x30370000 0x10000>;
373 snvs_rtc: snvs-rtc-lp {
374 compatible = "fsl,sec-v4.0-mon-rtc-lp";
377 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
378 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
380 clock-names = "snvs-rtc";
383 snvs_pwrkey: snvs-powerkey {
384 compatible = "fsl,sec-v4.0-pwrkey";
386 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
388 clock-names = "snvs-pwrkey";
389 linux,keycode = <KEY_POWER>;
395 clk: clock-controller@30380000 {
396 compatible = "fsl,imx8mp-ccm";
397 reg = <0x30380000 0x10000>;
399 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
400 <&clk_ext3>, <&clk_ext4>;
401 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
402 "clk_ext3", "clk_ext4";
403 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
404 <&clk IMX8MP_CLK_A53_CORE>,
405 <&clk IMX8MP_CLK_NOC>,
406 <&clk IMX8MP_CLK_NOC_IO>,
407 <&clk IMX8MP_CLK_GIC>,
408 <&clk IMX8MP_CLK_AUDIO_AHB>,
409 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
410 <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>,
411 <&clk IMX8MP_AUDIO_PLL1>,
412 <&clk IMX8MP_AUDIO_PLL2>;
413 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
414 <&clk IMX8MP_ARM_PLL_OUT>,
415 <&clk IMX8MP_SYS_PLL2_1000M>,
416 <&clk IMX8MP_SYS_PLL1_800M>,
417 <&clk IMX8MP_SYS_PLL2_500M>,
418 <&clk IMX8MP_SYS_PLL1_800M>,
419 <&clk IMX8MP_SYS_PLL1_800M>;
420 assigned-clock-rates = <0>, <0>,
431 src: reset-controller@30390000 {
432 compatible = "fsl,imx8mp-src", "syscon";
433 reg = <0x30390000 0x10000>;
434 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
439 aips2: bus@30400000 {
440 compatible = "fsl,aips-bus", "simple-bus";
441 reg = <0x30400000 0x400000>;
442 #address-cells = <1>;
447 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
448 reg = <0x30660000 0x10000>;
449 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
450 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
451 <&clk IMX8MP_CLK_PWM1_ROOT>;
452 clock-names = "ipg", "per";
458 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
459 reg = <0x30670000 0x10000>;
460 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
461 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
462 <&clk IMX8MP_CLK_PWM2_ROOT>;
463 clock-names = "ipg", "per";
469 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
470 reg = <0x30680000 0x10000>;
471 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
473 <&clk IMX8MP_CLK_PWM3_ROOT>;
474 clock-names = "ipg", "per";
480 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
481 reg = <0x30690000 0x10000>;
482 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
483 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
484 <&clk IMX8MP_CLK_PWM4_ROOT>;
485 clock-names = "ipg", "per";
490 system_counter: timer@306a0000 {
491 compatible = "nxp,sysctr-timer";
492 reg = <0x306a0000 0x20000>;
493 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
499 aips3: bus@30800000 {
500 compatible = "fsl,aips-bus", "simple-bus";
501 reg = <0x30800000 0x400000>;
502 #address-cells = <1>;
506 ecspi1: spi@30820000 {
507 #address-cells = <1>;
509 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
510 reg = <0x30820000 0x10000>;
511 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
513 <&clk IMX8MP_CLK_ECSPI1_ROOT>;
514 clock-names = "ipg", "per";
515 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
516 dma-names = "rx", "tx";
520 ecspi2: spi@30830000 {
521 #address-cells = <1>;
523 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
524 reg = <0x30830000 0x10000>;
525 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
526 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
527 <&clk IMX8MP_CLK_ECSPI2_ROOT>;
528 clock-names = "ipg", "per";
529 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
530 dma-names = "rx", "tx";
534 ecspi3: spi@30840000 {
535 #address-cells = <1>;
537 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
538 reg = <0x30840000 0x10000>;
539 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
541 <&clk IMX8MP_CLK_ECSPI3_ROOT>;
542 clock-names = "ipg", "per";
543 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
544 dma-names = "rx", "tx";
548 uart1: serial@30860000 {
549 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
550 reg = <0x30860000 0x10000>;
551 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
552 clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
553 <&clk IMX8MP_CLK_UART1_ROOT>;
554 clock-names = "ipg", "per";
555 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
556 dma-names = "rx", "tx";
560 uart3: serial@30880000 {
561 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
562 reg = <0x30880000 0x10000>;
563 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
565 <&clk IMX8MP_CLK_UART3_ROOT>;
566 clock-names = "ipg", "per";
567 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
568 dma-names = "rx", "tx";
572 uart2: serial@30890000 {
573 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
574 reg = <0x30890000 0x10000>;
575 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
577 <&clk IMX8MP_CLK_UART2_ROOT>;
578 clock-names = "ipg", "per";
582 flexcan1: can@308c0000 {
583 compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan";
584 reg = <0x308c0000 0x10000>;
585 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
586 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
587 <&clk IMX8MP_CLK_CAN1_ROOT>;
588 clock-names = "ipg", "per";
589 assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
590 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
591 assigned-clock-rates = <40000000>;
592 fsl,clk-source = /bits/ 8 <0>;
593 fsl,stop-mode = <&gpr 0x10 4>;
597 flexcan2: can@308d0000 {
598 compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan";
599 reg = <0x308d0000 0x10000>;
600 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
601 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
602 <&clk IMX8MP_CLK_CAN2_ROOT>;
603 clock-names = "ipg", "per";
604 assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
605 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
606 assigned-clock-rates = <40000000>;
607 fsl,clk-source = /bits/ 8 <0>;
608 fsl,stop-mode = <&gpr 0x10 5>;
612 crypto: crypto@30900000 {
613 compatible = "fsl,sec-v4.0";
614 #address-cells = <1>;
616 reg = <0x30900000 0x40000>;
617 ranges = <0 0x30900000 0x40000>;
618 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&clk IMX8MP_CLK_AHB>,
620 <&clk IMX8MP_CLK_IPG_ROOT>;
621 clock-names = "aclk", "ipg";
624 compatible = "fsl,sec-v4.0-job-ring";
625 reg = <0x1000 0x1000>;
626 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
630 compatible = "fsl,sec-v4.0-job-ring";
631 reg = <0x2000 0x1000>;
632 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
636 compatible = "fsl,sec-v4.0-job-ring";
637 reg = <0x3000 0x1000>;
638 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
643 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
644 #address-cells = <1>;
646 reg = <0x30a20000 0x10000>;
647 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>;
653 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
654 #address-cells = <1>;
656 reg = <0x30a30000 0x10000>;
657 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
658 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>;
663 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
664 #address-cells = <1>;
666 reg = <0x30a40000 0x10000>;
667 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
668 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
673 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
674 #address-cells = <1>;
676 reg = <0x30a50000 0x10000>;
677 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
678 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>;
682 uart4: serial@30a60000 {
683 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
684 reg = <0x30a60000 0x10000>;
685 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
686 clocks = <&clk IMX8MP_CLK_UART4_ROOT>,
687 <&clk IMX8MP_CLK_UART4_ROOT>;
688 clock-names = "ipg", "per";
689 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
690 dma-names = "rx", "tx";
694 mu: mailbox@30aa0000 {
695 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
696 reg = <0x30aa0000 0x10000>;
697 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&clk IMX8MP_CLK_MU_ROOT>;
703 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
704 #address-cells = <1>;
706 reg = <0x30ad0000 0x10000>;
707 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
708 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>;
713 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
714 #address-cells = <1>;
716 reg = <0x30ae0000 0x10000>;
717 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
718 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>;
722 usdhc1: mmc@30b40000 {
723 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
724 reg = <0x30b40000 0x10000>;
725 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&clk IMX8MP_CLK_DUMMY>,
727 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
728 <&clk IMX8MP_CLK_USDHC1_ROOT>;
729 clock-names = "ipg", "ahb", "per";
730 fsl,tuning-start-tap = <20>;
731 fsl,tuning-step= <2>;
736 usdhc2: mmc@30b50000 {
737 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
738 reg = <0x30b50000 0x10000>;
739 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
740 clocks = <&clk IMX8MP_CLK_DUMMY>,
741 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
742 <&clk IMX8MP_CLK_USDHC2_ROOT>;
743 clock-names = "ipg", "ahb", "per";
744 fsl,tuning-start-tap = <20>;
745 fsl,tuning-step= <2>;
750 usdhc3: mmc@30b60000 {
751 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
752 reg = <0x30b60000 0x10000>;
753 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
754 clocks = <&clk IMX8MP_CLK_DUMMY>,
755 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
756 <&clk IMX8MP_CLK_USDHC3_ROOT>;
757 clock-names = "ipg", "ahb", "per";
758 fsl,tuning-start-tap = <20>;
759 fsl,tuning-step= <2>;
764 sdma1: dma-controller@30bd0000 {
765 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
766 reg = <0x30bd0000 0x10000>;
767 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
768 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
769 <&clk IMX8MP_CLK_AHB>;
770 clock-names = "ipg", "ahb";
772 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
775 fec: ethernet@30be0000 {
776 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
777 reg = <0x30be0000 0x10000>;
778 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
782 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
783 <&clk IMX8MP_CLK_SIM_ENET_ROOT>,
784 <&clk IMX8MP_CLK_ENET_TIMER>,
785 <&clk IMX8MP_CLK_ENET_REF>,
786 <&clk IMX8MP_CLK_ENET_PHY_REF>;
787 clock-names = "ipg", "ahb", "ptp",
788 "enet_clk_ref", "enet_out";
789 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
790 <&clk IMX8MP_CLK_ENET_TIMER>,
791 <&clk IMX8MP_CLK_ENET_REF>,
792 <&clk IMX8MP_CLK_ENET_PHY_REF>;
793 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
794 <&clk IMX8MP_SYS_PLL2_100M>,
795 <&clk IMX8MP_SYS_PLL2_125M>,
796 <&clk IMX8MP_SYS_PLL2_50M>;
797 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
798 fsl,num-tx-queues = <3>;
799 fsl,num-rx-queues = <3>;
800 nvmem-cells = <ð_mac1>;
801 nvmem-cell-names = "mac-address";
802 fsl,stop-mode = <&gpr 0x10 3>;
807 eqos: ethernet@30bf0000 {
808 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
809 reg = <0x30bf0000 0x10000>;
810 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
811 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
812 interrupt-names = "eth_wake_irq", "macirq";
813 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
814 <&clk IMX8MP_CLK_QOS_ENET_ROOT>,
815 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
816 <&clk IMX8MP_CLK_ENET_QOS>;
817 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
818 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
819 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
820 <&clk IMX8MP_CLK_ENET_QOS>;
821 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
822 <&clk IMX8MP_SYS_PLL2_100M>,
823 <&clk IMX8MP_SYS_PLL2_125M>;
824 assigned-clock-rates = <0>, <100000000>, <125000000>;
825 intf_mode = <&gpr 0x4>;
830 gic: interrupt-controller@38800000 {
831 compatible = "arm,gic-v3";
832 reg = <0x38800000 0x10000>,
833 <0x38880000 0xc0000>;
834 #interrupt-cells = <3>;
835 interrupt-controller;
836 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
837 interrupt-parent = <&gic>;
841 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
842 reg = <0x3d800000 0x400000>;
843 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
846 usb3_phy0: usb-phy@381f0040 {
847 compatible = "fsl,imx8mp-usb-phy";
848 reg = <0x381f0040 0x40>;
849 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
851 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
852 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
857 usb3_0: usb@32f10100 {
858 compatible = "fsl,imx8mp-dwc3";
859 reg = <0x32f10100 0x8>;
860 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
861 <&clk IMX8MP_CLK_USB_ROOT>;
862 clock-names = "hsio", "suspend";
863 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
864 #address-cells = <1>;
866 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
870 usb_dwc3_0: usb@38100000 {
871 compatible = "snps,dwc3";
872 reg = <0x38100000 0x10000>;
873 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
874 <&clk IMX8MP_CLK_USB_CORE_REF>,
875 <&clk IMX8MP_CLK_USB_ROOT>;
876 clock-names = "bus_early", "ref", "suspend";
877 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
878 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
879 assigned-clock-rates = <500000000>;
880 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
881 phys = <&usb3_phy0>, <&usb3_phy0>;
882 phy-names = "usb2-phy", "usb3-phy";
883 snps,dis-u2-freeclk-exists-quirk;
888 usb3_phy1: usb-phy@382f0040 {
889 compatible = "fsl,imx8mp-usb-phy";
890 reg = <0x382f0040 0x40>;
891 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
893 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
894 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
898 usb3_1: usb@32f10108 {
899 compatible = "fsl,imx8mp-dwc3";
900 reg = <0x32f10108 0x8>;
901 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
902 <&clk IMX8MP_CLK_USB_ROOT>;
903 clock-names = "hsio", "suspend";
904 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
905 #address-cells = <1>;
907 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
911 usb_dwc3_1: usb@38200000 {
912 compatible = "snps,dwc3";
913 reg = <0x38200000 0x10000>;
914 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
915 <&clk IMX8MP_CLK_USB_CORE_REF>,
916 <&clk IMX8MP_CLK_USB_ROOT>;
917 clock-names = "bus_early", "ref", "suspend";
918 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
919 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
920 assigned-clock-rates = <500000000>;
921 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
922 phys = <&usb3_phy1>, <&usb3_phy1>;
923 phy-names = "usb2-phy", "usb3-phy";
924 snps,dis-u2-freeclk-exists-quirk;