1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/power/imx8mp-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
13 #include "imx8mp-pinfunc.h"
16 interrupt-parent = <&gic>;
50 compatible = "arm,cortex-a53";
52 clock-latency = <61036>;
53 clocks = <&clk IMX8MP_CLK_ARM>;
54 enable-method = "psci";
55 i-cache-size = <0x8000>;
56 i-cache-line-size = <64>;
58 d-cache-size = <0x8000>;
59 d-cache-line-size = <64>;
61 next-level-cache = <&A53_L2>;
62 nvmem-cells = <&cpu_speed_grade>;
63 nvmem-cell-names = "speed_grade";
64 operating-points-v2 = <&a53_opp_table>;
70 compatible = "arm,cortex-a53";
72 clock-latency = <61036>;
73 clocks = <&clk IMX8MP_CLK_ARM>;
74 enable-method = "psci";
75 i-cache-size = <0x8000>;
76 i-cache-line-size = <64>;
78 d-cache-size = <0x8000>;
79 d-cache-line-size = <64>;
81 next-level-cache = <&A53_L2>;
82 operating-points-v2 = <&a53_opp_table>;
88 compatible = "arm,cortex-a53";
90 clock-latency = <61036>;
91 clocks = <&clk IMX8MP_CLK_ARM>;
92 enable-method = "psci";
93 i-cache-size = <0x8000>;
94 i-cache-line-size = <64>;
96 d-cache-size = <0x8000>;
97 d-cache-line-size = <64>;
99 next-level-cache = <&A53_L2>;
100 operating-points-v2 = <&a53_opp_table>;
101 #cooling-cells = <2>;
106 compatible = "arm,cortex-a53";
108 clock-latency = <61036>;
109 clocks = <&clk IMX8MP_CLK_ARM>;
110 enable-method = "psci";
111 i-cache-size = <0x8000>;
112 i-cache-line-size = <64>;
113 i-cache-sets = <256>;
114 d-cache-size = <0x8000>;
115 d-cache-line-size = <64>;
116 d-cache-sets = <128>;
117 next-level-cache = <&A53_L2>;
118 operating-points-v2 = <&a53_opp_table>;
119 #cooling-cells = <2>;
123 compatible = "cache";
125 cache-size = <0x80000>;
126 cache-line-size = <64>;
131 a53_opp_table: opp-table {
132 compatible = "operating-points-v2";
136 opp-hz = /bits/ 64 <1200000000>;
137 opp-microvolt = <850000>;
138 opp-supported-hw = <0x8a0>, <0x7>;
139 clock-latency-ns = <150000>;
144 opp-hz = /bits/ 64 <1600000000>;
145 opp-microvolt = <950000>;
146 opp-supported-hw = <0xa0>, <0x7>;
147 clock-latency-ns = <150000>;
152 opp-hz = /bits/ 64 <1800000000>;
153 opp-microvolt = <1000000>;
154 opp-supported-hw = <0x20>, <0x3>;
155 clock-latency-ns = <150000>;
160 osc_32k: clock-osc-32k {
161 compatible = "fixed-clock";
163 clock-frequency = <32768>;
164 clock-output-names = "osc_32k";
167 osc_24m: clock-osc-24m {
168 compatible = "fixed-clock";
170 clock-frequency = <24000000>;
171 clock-output-names = "osc_24m";
174 clk_ext1: clock-ext1 {
175 compatible = "fixed-clock";
177 clock-frequency = <133000000>;
178 clock-output-names = "clk_ext1";
181 clk_ext2: clock-ext2 {
182 compatible = "fixed-clock";
184 clock-frequency = <133000000>;
185 clock-output-names = "clk_ext2";
188 clk_ext3: clock-ext3 {
189 compatible = "fixed-clock";
191 clock-frequency = <133000000>;
192 clock-output-names = "clk_ext3";
195 clk_ext4: clock-ext4 {
196 compatible = "fixed-clock";
198 clock-frequency= <133000000>;
199 clock-output-names = "clk_ext4";
203 #address-cells = <2>;
207 dsp_reserved: dsp@92400000 {
208 reg = <0 0x92400000 0 0x2000000>;
214 compatible = "arm,cortex-a53-pmu";
215 interrupts = <GIC_PPI 7
216 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
220 compatible = "arm,psci-1.0";
226 polling-delay-passive = <250>;
227 polling-delay = <2000>;
228 thermal-sensors = <&tmu 0>;
231 temperature = <85000>;
237 temperature = <95000>;
245 trip = <&cpu_alert0>;
247 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
248 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
249 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
250 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
256 polling-delay-passive = <250>;
257 polling-delay = <2000>;
258 thermal-sensors = <&tmu 1>;
261 temperature = <85000>;
267 temperature = <95000>;
275 trip = <&soc_alert0>;
277 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
278 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
279 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
280 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
287 compatible = "arm,armv8-timer";
288 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
289 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
290 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
291 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
292 clock-frequency = <8000000>;
293 arm,no-tick-in-suspend;
297 compatible = "fsl,imx8mp-soc", "simple-bus";
298 #address-cells = <1>;
300 ranges = <0x0 0x0 0x0 0x3e000000>;
301 nvmem-cells = <&imx8mp_uid>;
302 nvmem-cell-names = "soc_unique_id";
304 aips1: bus@30000000 {
305 compatible = "fsl,aips-bus", "simple-bus";
306 reg = <0x30000000 0x400000>;
307 #address-cells = <1>;
311 gpio1: gpio@30200000 {
312 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
313 reg = <0x30200000 0x10000>;
314 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
315 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
319 interrupt-controller;
320 #interrupt-cells = <2>;
321 gpio-ranges = <&iomuxc 0 5 30>;
324 gpio2: gpio@30210000 {
325 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
326 reg = <0x30210000 0x10000>;
327 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
332 interrupt-controller;
333 #interrupt-cells = <2>;
334 gpio-ranges = <&iomuxc 0 35 21>;
337 gpio3: gpio@30220000 {
338 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
339 reg = <0x30220000 0x10000>;
340 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
345 interrupt-controller;
346 #interrupt-cells = <2>;
347 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
350 gpio4: gpio@30230000 {
351 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
352 reg = <0x30230000 0x10000>;
353 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
354 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
358 interrupt-controller;
359 #interrupt-cells = <2>;
360 gpio-ranges = <&iomuxc 0 82 32>;
363 gpio5: gpio@30240000 {
364 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
365 reg = <0x30240000 0x10000>;
366 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
367 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
371 interrupt-controller;
372 #interrupt-cells = <2>;
373 gpio-ranges = <&iomuxc 0 114 30>;
377 compatible = "fsl,imx8mp-tmu";
378 reg = <0x30260000 0x10000>;
379 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
380 #thermal-sensor-cells = <1>;
383 wdog1: watchdog@30280000 {
384 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
385 reg = <0x30280000 0x10000>;
386 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
391 wdog2: watchdog@30290000 {
392 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
393 reg = <0x30290000 0x10000>;
394 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>;
399 wdog3: watchdog@302a0000 {
400 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
401 reg = <0x302a0000 0x10000>;
402 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
403 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>;
407 iomuxc: pinctrl@30330000 {
408 compatible = "fsl,imx8mp-iomuxc";
409 reg = <0x30330000 0x10000>;
412 gpr: iomuxc-gpr@30340000 {
413 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
414 reg = <0x30340000 0x10000>;
417 ocotp: efuse@30350000 {
418 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
419 reg = <0x30350000 0x10000>;
420 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
421 /* For nvmem subnodes */
422 #address-cells = <1>;
425 imx8mp_uid: unique-id@420 {
429 cpu_speed_grade: speed-grade@10 {
433 eth_mac1: mac-address@90 {
437 eth_mac2: mac-address@96 {
442 anatop: anatop@30360000 {
443 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
445 reg = <0x30360000 0x10000>;
448 snvs: snvs@30370000 {
449 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
450 reg = <0x30370000 0x10000>;
452 snvs_rtc: snvs-rtc-lp {
453 compatible = "fsl,sec-v4.0-mon-rtc-lp";
456 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
459 clock-names = "snvs-rtc";
462 snvs_pwrkey: snvs-powerkey {
463 compatible = "fsl,sec-v4.0-pwrkey";
465 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
467 clock-names = "snvs-pwrkey";
468 linux,keycode = <KEY_POWER>;
474 clk: clock-controller@30380000 {
475 compatible = "fsl,imx8mp-ccm";
476 reg = <0x30380000 0x10000>;
478 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
479 <&clk_ext3>, <&clk_ext4>;
480 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
481 "clk_ext3", "clk_ext4";
482 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
483 <&clk IMX8MP_CLK_A53_CORE>,
484 <&clk IMX8MP_CLK_NOC>,
485 <&clk IMX8MP_CLK_NOC_IO>,
486 <&clk IMX8MP_CLK_GIC>,
487 <&clk IMX8MP_CLK_AUDIO_AHB>,
488 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
489 <&clk IMX8MP_AUDIO_PLL1>,
490 <&clk IMX8MP_AUDIO_PLL2>;
491 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
492 <&clk IMX8MP_ARM_PLL_OUT>,
493 <&clk IMX8MP_SYS_PLL2_1000M>,
494 <&clk IMX8MP_SYS_PLL1_800M>,
495 <&clk IMX8MP_SYS_PLL2_500M>,
496 <&clk IMX8MP_SYS_PLL1_800M>,
497 <&clk IMX8MP_SYS_PLL1_800M>;
498 assigned-clock-rates = <0>, <0>,
508 src: reset-controller@30390000 {
509 compatible = "fsl,imx8mp-src", "syscon";
510 reg = <0x30390000 0x10000>;
511 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
516 compatible = "fsl,imx8mp-gpc";
517 reg = <0x303a0000 0x1000>;
518 interrupt-parent = <&gic>;
519 interrupt-controller;
520 #interrupt-cells = <3>;
523 #address-cells = <1>;
526 pgc_gpu2d: power-domain@6 {
527 #power-domain-cells = <0>;
528 reg = <IMX8MP_POWER_DOMAIN_GPU2D>;
529 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>;
530 power-domains = <&pgc_gpumix>;
533 pgc_gpumix: power-domain@7 {
534 #power-domain-cells = <0>;
535 reg = <IMX8MP_POWER_DOMAIN_GPUMIX>;
536 clocks = <&clk IMX8MP_CLK_GPU_ROOT>,
537 <&clk IMX8MP_CLK_GPU_AHB>;
538 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
539 <&clk IMX8MP_CLK_GPU_AHB>;
540 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
541 <&clk IMX8MP_SYS_PLL1_800M>;
542 assigned-clock-rates = <800000000>, <400000000>;
545 pgc_gpu3d: power-domain@9 {
546 #power-domain-cells = <0>;
547 reg = <IMX8MP_POWER_DOMAIN_GPU3D>;
548 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
549 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
550 power-domains = <&pgc_gpumix>;
556 aips2: bus@30400000 {
557 compatible = "fsl,aips-bus", "simple-bus";
558 reg = <0x30400000 0x400000>;
559 #address-cells = <1>;
564 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
565 reg = <0x30660000 0x10000>;
566 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
567 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
568 <&clk IMX8MP_CLK_PWM1_ROOT>;
569 clock-names = "ipg", "per";
575 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
576 reg = <0x30670000 0x10000>;
577 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
579 <&clk IMX8MP_CLK_PWM2_ROOT>;
580 clock-names = "ipg", "per";
586 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
587 reg = <0x30680000 0x10000>;
588 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
589 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
590 <&clk IMX8MP_CLK_PWM3_ROOT>;
591 clock-names = "ipg", "per";
597 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
598 reg = <0x30690000 0x10000>;
599 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
601 <&clk IMX8MP_CLK_PWM4_ROOT>;
602 clock-names = "ipg", "per";
607 system_counter: timer@306a0000 {
608 compatible = "nxp,sysctr-timer";
609 reg = <0x306a0000 0x20000>;
610 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
616 aips3: bus@30800000 {
617 compatible = "fsl,aips-bus", "simple-bus";
618 reg = <0x30800000 0x400000>;
619 #address-cells = <1>;
623 ecspi1: spi@30820000 {
624 #address-cells = <1>;
626 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
627 reg = <0x30820000 0x10000>;
628 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
630 <&clk IMX8MP_CLK_ECSPI1_ROOT>;
631 clock-names = "ipg", "per";
632 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
633 dma-names = "rx", "tx";
637 ecspi2: spi@30830000 {
638 #address-cells = <1>;
640 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
641 reg = <0x30830000 0x10000>;
642 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
643 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
644 <&clk IMX8MP_CLK_ECSPI2_ROOT>;
645 clock-names = "ipg", "per";
646 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
647 dma-names = "rx", "tx";
651 ecspi3: spi@30840000 {
652 #address-cells = <1>;
654 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
655 reg = <0x30840000 0x10000>;
656 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
657 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
658 <&clk IMX8MP_CLK_ECSPI3_ROOT>;
659 clock-names = "ipg", "per";
660 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
661 dma-names = "rx", "tx";
665 uart1: serial@30860000 {
666 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
667 reg = <0x30860000 0x10000>;
668 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
669 clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
670 <&clk IMX8MP_CLK_UART1_ROOT>;
671 clock-names = "ipg", "per";
672 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
673 dma-names = "rx", "tx";
677 uart3: serial@30880000 {
678 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
679 reg = <0x30880000 0x10000>;
680 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
682 <&clk IMX8MP_CLK_UART3_ROOT>;
683 clock-names = "ipg", "per";
684 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
685 dma-names = "rx", "tx";
689 uart2: serial@30890000 {
690 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
691 reg = <0x30890000 0x10000>;
692 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
693 clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
694 <&clk IMX8MP_CLK_UART2_ROOT>;
695 clock-names = "ipg", "per";
699 flexcan1: can@308c0000 {
700 compatible = "fsl,imx8mp-flexcan";
701 reg = <0x308c0000 0x10000>;
702 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
703 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
704 <&clk IMX8MP_CLK_CAN1_ROOT>;
705 clock-names = "ipg", "per";
706 assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
707 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
708 assigned-clock-rates = <40000000>;
709 fsl,clk-source = /bits/ 8 <0>;
710 fsl,stop-mode = <&gpr 0x10 4>;
714 flexcan2: can@308d0000 {
715 compatible = "fsl,imx8mp-flexcan";
716 reg = <0x308d0000 0x10000>;
717 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
718 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
719 <&clk IMX8MP_CLK_CAN2_ROOT>;
720 clock-names = "ipg", "per";
721 assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
722 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
723 assigned-clock-rates = <40000000>;
724 fsl,clk-source = /bits/ 8 <0>;
725 fsl,stop-mode = <&gpr 0x10 5>;
729 crypto: crypto@30900000 {
730 compatible = "fsl,sec-v4.0";
731 #address-cells = <1>;
733 reg = <0x30900000 0x40000>;
734 ranges = <0 0x30900000 0x40000>;
735 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
736 clocks = <&clk IMX8MP_CLK_AHB>,
737 <&clk IMX8MP_CLK_IPG_ROOT>;
738 clock-names = "aclk", "ipg";
741 compatible = "fsl,sec-v4.0-job-ring";
742 reg = <0x1000 0x1000>;
743 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
747 compatible = "fsl,sec-v4.0-job-ring";
748 reg = <0x2000 0x1000>;
749 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
753 compatible = "fsl,sec-v4.0-job-ring";
754 reg = <0x3000 0x1000>;
755 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
760 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
761 #address-cells = <1>;
763 reg = <0x30a20000 0x10000>;
764 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
765 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>;
770 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
771 #address-cells = <1>;
773 reg = <0x30a30000 0x10000>;
774 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
775 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>;
780 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
781 #address-cells = <1>;
783 reg = <0x30a40000 0x10000>;
784 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
785 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
790 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
791 #address-cells = <1>;
793 reg = <0x30a50000 0x10000>;
794 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
795 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>;
799 uart4: serial@30a60000 {
800 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
801 reg = <0x30a60000 0x10000>;
802 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
803 clocks = <&clk IMX8MP_CLK_UART4_ROOT>,
804 <&clk IMX8MP_CLK_UART4_ROOT>;
805 clock-names = "ipg", "per";
806 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
807 dma-names = "rx", "tx";
811 mu: mailbox@30aa0000 {
812 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
813 reg = <0x30aa0000 0x10000>;
814 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
815 clocks = <&clk IMX8MP_CLK_MU_ROOT>;
819 mu2: mailbox@30e60000 {
820 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
821 reg = <0x30e60000 0x10000>;
822 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
828 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
829 #address-cells = <1>;
831 reg = <0x30ad0000 0x10000>;
832 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
833 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>;
838 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
839 #address-cells = <1>;
841 reg = <0x30ae0000 0x10000>;
842 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
843 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>;
847 usdhc1: mmc@30b40000 {
848 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
849 reg = <0x30b40000 0x10000>;
850 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
851 clocks = <&clk IMX8MP_CLK_DUMMY>,
852 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
853 <&clk IMX8MP_CLK_USDHC1_ROOT>;
854 clock-names = "ipg", "ahb", "per";
855 fsl,tuning-start-tap = <20>;
856 fsl,tuning-step= <2>;
861 usdhc2: mmc@30b50000 {
862 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
863 reg = <0x30b50000 0x10000>;
864 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
865 clocks = <&clk IMX8MP_CLK_DUMMY>,
866 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
867 <&clk IMX8MP_CLK_USDHC2_ROOT>;
868 clock-names = "ipg", "ahb", "per";
869 fsl,tuning-start-tap = <20>;
870 fsl,tuning-step= <2>;
875 usdhc3: mmc@30b60000 {
876 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
877 reg = <0x30b60000 0x10000>;
878 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
879 clocks = <&clk IMX8MP_CLK_DUMMY>,
880 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
881 <&clk IMX8MP_CLK_USDHC3_ROOT>;
882 clock-names = "ipg", "ahb", "per";
883 fsl,tuning-start-tap = <20>;
884 fsl,tuning-step= <2>;
889 flexspi: spi@30bb0000 {
890 compatible = "nxp,imx8mp-fspi";
891 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
892 reg-names = "fspi_base", "fspi_mmap";
893 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
894 clocks = <&clk IMX8MP_CLK_QSPI_ROOT>,
895 <&clk IMX8MP_CLK_QSPI_ROOT>;
896 clock-names = "fspi_en", "fspi";
897 assigned-clock-rates = <80000000>;
898 assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
899 #address-cells = <1>;
904 sdma1: dma-controller@30bd0000 {
905 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
906 reg = <0x30bd0000 0x10000>;
907 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
908 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
909 <&clk IMX8MP_CLK_AHB>;
910 clock-names = "ipg", "ahb";
912 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
915 fec: ethernet@30be0000 {
916 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
917 reg = <0x30be0000 0x10000>;
918 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
919 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
920 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
921 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
922 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
923 <&clk IMX8MP_CLK_SIM_ENET_ROOT>,
924 <&clk IMX8MP_CLK_ENET_TIMER>,
925 <&clk IMX8MP_CLK_ENET_REF>,
926 <&clk IMX8MP_CLK_ENET_PHY_REF>;
927 clock-names = "ipg", "ahb", "ptp",
928 "enet_clk_ref", "enet_out";
929 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
930 <&clk IMX8MP_CLK_ENET_TIMER>,
931 <&clk IMX8MP_CLK_ENET_REF>,
932 <&clk IMX8MP_CLK_ENET_PHY_REF>;
933 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
934 <&clk IMX8MP_SYS_PLL2_100M>,
935 <&clk IMX8MP_SYS_PLL2_125M>,
936 <&clk IMX8MP_SYS_PLL2_50M>;
937 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
938 fsl,num-tx-queues = <3>;
939 fsl,num-rx-queues = <3>;
940 nvmem-cells = <ð_mac1>;
941 nvmem-cell-names = "mac-address";
942 fsl,stop-mode = <&gpr 0x10 3>;
946 eqos: ethernet@30bf0000 {
947 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
948 reg = <0x30bf0000 0x10000>;
949 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
950 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
951 interrupt-names = "macirq", "eth_wake_irq";
952 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
953 <&clk IMX8MP_CLK_QOS_ENET_ROOT>,
954 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
955 <&clk IMX8MP_CLK_ENET_QOS>;
956 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
957 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
958 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
959 <&clk IMX8MP_CLK_ENET_QOS>;
960 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
961 <&clk IMX8MP_SYS_PLL2_100M>,
962 <&clk IMX8MP_SYS_PLL2_125M>;
963 assigned-clock-rates = <0>, <100000000>, <125000000>;
964 nvmem-cells = <ð_mac2>;
965 nvmem-cell-names = "mac-address";
966 intf_mode = <&gpr 0x4>;
971 gpu3d: gpu@38000000 {
972 compatible = "vivante,gc";
973 reg = <0x38000000 0x8000>;
974 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
975 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
976 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>,
977 <&clk IMX8MP_CLK_GPU_ROOT>,
978 <&clk IMX8MP_CLK_GPU_AHB>;
979 clock-names = "core", "shader", "bus", "reg";
980 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
981 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
982 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
983 <&clk IMX8MP_SYS_PLL1_800M>;
984 assigned-clock-rates = <800000000>, <800000000>;
985 power-domains = <&pgc_gpu3d>;
988 gpu2d: gpu@38008000 {
989 compatible = "vivante,gc";
990 reg = <0x38008000 0x8000>;
991 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
992 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>,
993 <&clk IMX8MP_CLK_GPU_ROOT>,
994 <&clk IMX8MP_CLK_GPU_AHB>;
995 clock-names = "core", "bus", "reg";
996 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
997 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
998 assigned-clock-rates = <800000000>;
999 power-domains = <&pgc_gpu2d>;
1002 gic: interrupt-controller@38800000 {
1003 compatible = "arm,gic-v3";
1004 reg = <0x38800000 0x10000>,
1005 <0x38880000 0xc0000>;
1006 #interrupt-cells = <3>;
1007 interrupt-controller;
1008 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1009 interrupt-parent = <&gic>;
1013 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
1014 reg = <0x3d800000 0x400000>;
1015 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1018 usb3_phy0: usb-phy@381f0040 {
1019 compatible = "fsl,imx8mp-usb-phy";
1020 reg = <0x381f0040 0x40>;
1021 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
1022 clock-names = "phy";
1023 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
1024 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
1026 status = "disabled";
1029 usb3_0: usb@32f10100 {
1030 compatible = "fsl,imx8mp-dwc3";
1031 reg = <0x32f10100 0x8>,
1033 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
1034 <&clk IMX8MP_CLK_USB_ROOT>;
1035 clock-names = "hsio", "suspend";
1036 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1037 #address-cells = <1>;
1039 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
1041 status = "disabled";
1043 usb_dwc3_0: usb@38100000 {
1044 compatible = "snps,dwc3";
1045 reg = <0x38100000 0x10000>;
1046 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
1047 <&clk IMX8MP_CLK_USB_CORE_REF>,
1048 <&clk IMX8MP_CLK_USB_ROOT>;
1049 clock-names = "bus_early", "ref", "suspend";
1050 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
1051 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
1052 assigned-clock-rates = <500000000>;
1053 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1054 phys = <&usb3_phy0>, <&usb3_phy0>;
1055 phy-names = "usb2-phy", "usb3-phy";
1056 snps,dis-u2-freeclk-exists-quirk;
1061 usb3_phy1: usb-phy@382f0040 {
1062 compatible = "fsl,imx8mp-usb-phy";
1063 reg = <0x382f0040 0x40>;
1064 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
1065 clock-names = "phy";
1066 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
1067 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
1069 status = "disabled";
1072 usb3_1: usb@32f10108 {
1073 compatible = "fsl,imx8mp-dwc3";
1074 reg = <0x32f10108 0x8>,
1076 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
1077 <&clk IMX8MP_CLK_USB_ROOT>;
1078 clock-names = "hsio", "suspend";
1079 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
1080 #address-cells = <1>;
1082 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
1084 status = "disabled";
1086 usb_dwc3_1: usb@38200000 {
1087 compatible = "snps,dwc3";
1088 reg = <0x38200000 0x10000>;
1089 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
1090 <&clk IMX8MP_CLK_USB_CORE_REF>,
1091 <&clk IMX8MP_CLK_USB_ROOT>;
1092 clock-names = "bus_early", "ref", "suspend";
1093 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
1094 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
1095 assigned-clock-rates = <500000000>;
1096 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1097 phys = <&usb3_phy1>, <&usb3_phy1>;
1098 phy-names = "usb2-phy", "usb3-phy";
1099 snps,dis-u2-freeclk-exists-quirk;
1104 compatible = "fsl,imx8mp-dsp";
1105 reg = <0x3b6e8000 0x88000>;
1106 mbox-names = "txdb0", "txdb1",
1108 mboxes = <&mu2 2 0>, <&mu2 2 1>,
1109 <&mu2 3 0>, <&mu2 3 1>;
1110 memory-region = <&dsp_reserved>;
1111 status = "disabled";