arch/arm64/boot/dts/freescale/imx8mp.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <dt-bindings/clock/imx8mp-clock.h>
   7 #include <dt-bindings/power/imx8mp-power.h>
   8 #include <dt-bindings/reset/imx8mp-reset.h>
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/input/input.h>
  11 #include <dt-bindings/interconnect/fsl,imx8mp.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14
  15 #include "imx8mp-pinfunc.h"
  16
  17 / {
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 ethernet0 = &fec;
  24                 ethernet1 = &eqos;
  25                 gpio0 = &gpio1;
  26                 gpio1 = &gpio2;
  27                 gpio2 = &gpio3;
  28                 gpio3 = &gpio4;
  29                 gpio4 = &gpio5;
  30                 i2c0 = &i2c1;
  31                 i2c1 = &i2c2;
  32                 i2c2 = &i2c3;
  33                 i2c3 = &i2c4;
  34                 i2c4 = &i2c5;
  35                 i2c5 = &i2c6;
  36                 mmc0 = &usdhc1;
  37                 mmc1 = &usdhc2;
  38                 mmc2 = &usdhc3;
  39                 serial0 = &uart1;
  40                 serial1 = &uart2;
  41                 serial2 = &uart3;
  42                 serial3 = &uart4;
  43                 spi0 = &flexspi;
  44         };
  45
  46         cpus {
  47                 #address-cells = <1>;
  48                 #size-cells = <0>;
  49
  50                 A53_0: cpu@0 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a53";
  53                         reg = <0x0>;
  54                         clock-latency = <61036>;
  55                         clocks = <&clk IMX8MP_CLK_ARM>;
  56                         enable-method = "psci";
  57                         i-cache-size = <0x8000>;
  58                         i-cache-line-size = <64>;
  59                         i-cache-sets = <256>;
  60                         d-cache-size = <0x8000>;
  61                         d-cache-line-size = <64>;
  62                         d-cache-sets = <128>;
  63                         next-level-cache = <&A53_L2>;
  64                         nvmem-cells = <&cpu_speed_grade>;
  65                         nvmem-cell-names = "speed_grade";
  66                         operating-points-v2 = <&a53_opp_table>;
  67                         #cooling-cells = <2>;
  68                 };
  69
  70                 A53_1: cpu@1 {
  71                         device_type = "cpu";
  72                         compatible = "arm,cortex-a53";
  73                         reg = <0x1>;
  74                         clock-latency = <61036>;
  75                         clocks = <&clk IMX8MP_CLK_ARM>;
  76                         enable-method = "psci";
  77                         i-cache-size = <0x8000>;
  78                         i-cache-line-size = <64>;
  79                         i-cache-sets = <256>;
  80                         d-cache-size = <0x8000>;
  81                         d-cache-line-size = <64>;
  82                         d-cache-sets = <128>;
  83                         next-level-cache = <&A53_L2>;
  84                         operating-points-v2 = <&a53_opp_table>;
  85                         #cooling-cells = <2>;
  86                 };
  87
  88                 A53_2: cpu@2 {
  89                         device_type = "cpu";
  90                         compatible = "arm,cortex-a53";
  91                         reg = <0x2>;
  92                         clock-latency = <61036>;
  93                         clocks = <&clk IMX8MP_CLK_ARM>;
  94                         enable-method = "psci";
  95                         i-cache-size = <0x8000>;
  96                         i-cache-line-size = <64>;
  97                         i-cache-sets = <256>;
  98                         d-cache-size = <0x8000>;
  99                         d-cache-line-size = <64>;
 100                         d-cache-sets = <128>;
 101                         next-level-cache = <&A53_L2>;
 102                         operating-points-v2 = <&a53_opp_table>;
 103                         #cooling-cells = <2>;
 104                 };
 105
 106                 A53_3: cpu@3 {
 107                         device_type = "cpu";
 108                         compatible = "arm,cortex-a53";
 109                         reg = <0x3>;
 110                         clock-latency = <61036>;
 111                         clocks = <&clk IMX8MP_CLK_ARM>;
 112                         enable-method = "psci";
 113                         i-cache-size = <0x8000>;
 114                         i-cache-line-size = <64>;
 115                         i-cache-sets = <256>;
 116                         d-cache-size = <0x8000>;
 117                         d-cache-line-size = <64>;
 118                         d-cache-sets = <128>;
 119                         next-level-cache = <&A53_L2>;
 120                         operating-points-v2 = <&a53_opp_table>;
 121                         #cooling-cells = <2>;
 122                 };
 123
 124                 A53_L2: l2-cache0 {
 125                         compatible = "cache";
 126                         cache-unified;
 127                         cache-level = <2>;
 128                         cache-size = <0x80000>;
 129                         cache-line-size = <64>;
 130                         cache-sets = <512>;
 131                 };
 132         };
 133
 134         a53_opp_table: opp-table {
 135                 compatible = "operating-points-v2";
 136                 opp-shared;
 137
 138                 opp-1200000000 {
 139                         opp-hz = /bits/ 64 <1200000000>;
 140                         opp-microvolt = <850000>;
 141                         opp-supported-hw = <0x8a0>, <0x7>;
 142                         clock-latency-ns = <150000>;
 143                         opp-suspend;
 144                 };
 145
 146                 opp-1600000000 {
 147                         opp-hz = /bits/ 64 <1600000000>;
 148                         opp-microvolt = <950000>;
 149                         opp-supported-hw = <0xa0>, <0x7>;
 150                         clock-latency-ns = <150000>;
 151                         opp-suspend;
 152                 };
 153
 154                 opp-1800000000 {
 155                         opp-hz = /bits/ 64 <1800000000>;
 156                         opp-microvolt = <1000000>;
 157                         opp-supported-hw = <0x20>, <0x3>;
 158                         clock-latency-ns = <150000>;
 159                         opp-suspend;
 160                 };
 161         };
 162
 163         osc_32k: clock-osc-32k {
 164                 compatible = "fixed-clock";
 165                 #clock-cells = <0>;
 166                 clock-frequency = <32768>;
 167                 clock-output-names = "osc_32k";
 168         };
 169
 170         osc_24m: clock-osc-24m {
 171                 compatible = "fixed-clock";
 172                 #clock-cells = <0>;
 173                 clock-frequency = <24000000>;
 174                 clock-output-names = "osc_24m";
 175         };
 176
 177         clk_ext1: clock-ext1 {
 178                 compatible = "fixed-clock";
 179                 #clock-cells = <0>;
 180                 clock-frequency = <133000000>;
 181                 clock-output-names = "clk_ext1";
 182         };
 183
 184         clk_ext2: clock-ext2 {
 185                 compatible = "fixed-clock";
 186                 #clock-cells = <0>;
 187                 clock-frequency = <133000000>;
 188                 clock-output-names = "clk_ext2";
 189         };
 190
 191         clk_ext3: clock-ext3 {
 192                 compatible = "fixed-clock";
 193                 #clock-cells = <0>;
 194                 clock-frequency = <133000000>;
 195                 clock-output-names = "clk_ext3";
 196         };
 197
 198         clk_ext4: clock-ext4 {
 199                 compatible = "fixed-clock";
 200                 #clock-cells = <0>;
 201                 clock-frequency = <133000000>;
 202                 clock-output-names = "clk_ext4";
 203         };
 204
 205         funnel {
 206                 /*
 207                  * non-configurable funnel don't show up on the AMBA
 208                  * bus.  As such no need to add "arm,primecell".
 209                  */
 210                 compatible = "arm,coresight-static-funnel";
 211
 212                 in-ports {
 213                         #address-cells = <1>;
 214                         #size-cells = <0>;
 215
 216                         port@0 {
 217                                 reg = <0>;
 218
 219                                 ca_funnel_in_port0: endpoint {
 220                                         remote-endpoint = <&etm0_out_port>;
 221                                 };
 222                         };
 223
 224                         port@1 {
 225                                 reg = <1>;
 226
 227                                 ca_funnel_in_port1: endpoint {
 228                                         remote-endpoint = <&etm1_out_port>;
 229                                 };
 230                         };
 231
 232                         port@2 {
 233                                 reg = <2>;
 234
 235                                 ca_funnel_in_port2: endpoint {
 236                                         remote-endpoint = <&etm2_out_port>;
 237                                 };
 238                         };
 239
 240                         port@3 {
 241                                 reg = <3>;
 242
 243                                         ca_funnel_in_port3: endpoint {
 244                                         remote-endpoint = <&etm3_out_port>;
 245                                 };
 246                         };
 247                 };
 248
 249                 out-ports {
 250                         port {
 251
 252                                 ca_funnel_out_port0: endpoint {
 253                                         remote-endpoint = <&hugo_funnel_in_port0>;
 254                                 };
 255                         };
 256                 };
 257         };
 258
 259         reserved-memory {
 260                 #address-cells = <2>;
 261                 #size-cells = <2>;
 262                 ranges;
 263
 264                 dsp_reserved: dsp@92400000 {
 265                         reg = <0 0x92400000 0 0x2000000>;
 266                         no-map;
 267                 };
 268         };
 269
 270         pmu {
 271                 compatible = "arm,cortex-a53-pmu";
 272                 interrupts = <GIC_PPI 7
 273                              (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 274         };
 275
 276         psci {
 277                 compatible = "arm,psci-1.0";
 278                 method = "smc";
 279         };
 280
 281         thermal-zones {
 282                 cpu-thermal {
 283                         polling-delay-passive = <250>;
 284                         polling-delay = <2000>;
 285                         thermal-sensors = <&tmu 0>;
 286                         trips {
 287                                 cpu_alert0: trip0 {
 288                                         temperature = <85000>;
 289                                         hysteresis = <2000>;
 290                                         type = "passive";
 291                                 };
 292
 293                                 cpu_crit0: trip1 {
 294                                         temperature = <95000>;
 295                                         hysteresis = <2000>;
 296                                         type = "critical";
 297                                 };
 298                         };
 299
 300                         cooling-maps {
 301                                 map0 {
 302                                         trip = <&cpu_alert0>;
 303                                         cooling-device =
 304                                                 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 305                                                 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 306                                                 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 307                                                 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 308                                 };
 309                         };
 310                 };
 311
 312                 soc-thermal {
 313                         polling-delay-passive = <250>;
 314                         polling-delay = <2000>;
 315                         thermal-sensors = <&tmu 1>;
 316                         trips {
 317                                 soc_alert0: trip0 {
 318                                         temperature = <85000>;
 319                                         hysteresis = <2000>;
 320                                         type = "passive";
 321                                 };
 322
 323                                 soc_crit0: trip1 {
 324                                         temperature = <95000>;
 325                                         hysteresis = <2000>;
 326                                         type = "critical";
 327                                 };
 328                         };
 329
 330                         cooling-maps {
 331                                 map0 {
 332                                         trip = <&soc_alert0>;
 333                                         cooling-device =
 334                                                 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 335                                                 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 336                                                 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 337                                                 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 338                                 };
 339                         };
 340                 };
 341         };
 342
 343         timer {
 344                 compatible = "arm,armv8-timer";
 345                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 346                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 347                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 348                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 349                 clock-frequency = <8000000>;
 350                 arm,no-tick-in-suspend;
 351         };
 352
 353         soc: soc@0 {
 354                 compatible = "fsl,imx8mp-soc", "simple-bus";
 355                 #address-cells = <1>;
 356                 #size-cells = <1>;
 357                 ranges = <0x0 0x0 0x0 0x3e000000>;
 358                 nvmem-cells = <&imx8mp_uid>;
 359                 nvmem-cell-names = "soc_unique_id";
 360
 361                 etm0: etm@28440000 {
 362                         compatible = "arm,coresight-etm4x", "arm,primecell";
 363                         reg = <0x28440000 0x1000>;
 364                         cpu = <&A53_0>;
 365                         clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
 366                         clock-names = "apb_pclk";
 367
 368                         out-ports {
 369                                 port {
 370                                         etm0_out_port: endpoint {
 371                                                 remote-endpoint = <&ca_funnel_in_port0>;
 372                                         };
 373                                 };
 374                         };
 375                 };
 376
 377                 etm1: etm@28540000 {
 378                         compatible = "arm,coresight-etm4x", "arm,primecell";
 379                         reg = <0x28540000 0x1000>;
 380                         cpu = <&A53_1>;
 381                         clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
 382                         clock-names = "apb_pclk";
 383
 384                         out-ports {
 385                                 port {
 386                                         etm1_out_port: endpoint {
 387                                                 remote-endpoint = <&ca_funnel_in_port1>;
 388                                         };
 389                                 };
 390                         };
 391                 };
 392
 393                 etm2: etm@28640000 {
 394                         compatible = "arm,coresight-etm4x", "arm,primecell";
 395                         reg = <0x28640000 0x1000>;
 396                         cpu = <&A53_2>;
 397                         clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
 398                         clock-names = "apb_pclk";
 399
 400                         out-ports {
 401                                 port {
 402                                         etm2_out_port: endpoint {
 403                                                 remote-endpoint = <&ca_funnel_in_port2>;
 404                                         };
 405                                 };
 406                         };
 407                 };
 408
 409                 etm3: etm@28740000 {
 410                         compatible = "arm,coresight-etm4x", "arm,primecell";
 411                         reg = <0x28740000 0x1000>;
 412                         cpu = <&A53_3>;
 413                         clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
 414                         clock-names = "apb_pclk";
 415
 416                         out-ports {
 417                                 port {
 418                                         etm3_out_port: endpoint {
 419                                                 remote-endpoint = <&ca_funnel_in_port3>;
 420                                         };
 421                                 };
 422                         };
 423                 };
 424
 425                 funnel@28c03000 {
 426                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 427                         reg = <0x28c03000 0x1000>;
 428                         clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
 429                         clock-names = "apb_pclk";
 430
 431                         in-ports {
 432                                 #address-cells = <1>;
 433                                 #size-cells = <0>;
 434
 435                                 port@0 {
 436                                         reg = <0>;
 437
 438                                         hugo_funnel_in_port0: endpoint {
 439                                                 remote-endpoint = <&ca_funnel_out_port0>;
 440                                         };
 441                                 };
 442
 443                                 port@1 {
 444                                         reg = <1>;
 445
 446                                         hugo_funnel_in_port1: endpoint {
 447                                         /* M7 input */
 448                                         };
 449                                 };
 450
 451                                 port@2 {
 452                                         reg = <2>;
 453
 454                                         hugo_funnel_in_port2: endpoint {
 455                                         /* DSP input */
 456                                         };
 457                                 };
 458                                 /* the other input ports are not connect to anything */
 459                         };
 460
 461                         out-ports {
 462                                 port {
 463                                         hugo_funnel_out_port0: endpoint {
 464                                                 remote-endpoint = <&etf_in_port>;
 465                                         };
 466                                 };
 467                         };
 468                 };
 469
 470                 etf@28c04000 {
 471                         compatible = "arm,coresight-tmc", "arm,primecell";
 472                         reg = <0x28c04000 0x1000>;
 473                         clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
 474                         clock-names = "apb_pclk";
 475
 476                         in-ports {
 477                                 port {
 478                                         etf_in_port: endpoint {
 479                                                 remote-endpoint = <&hugo_funnel_out_port0>;
 480                                         };
 481                                 };
 482                         };
 483
 484                         out-ports {
 485                                 port {
 486                                         etf_out_port: endpoint {
 487                                                 remote-endpoint = <&etr_in_port>;
 488                                         };
 489                                 };
 490                         };
 491                 };
 492
 493                 etr@28c06000 {
 494                         compatible = "arm,coresight-tmc", "arm,primecell";
 495                         reg = <0x28c06000 0x1000>;
 496                         clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
 497                         clock-names = "apb_pclk";
 498
 499                         in-ports {
 500                                 port {
 501                                         etr_in_port: endpoint {
 502                                                 remote-endpoint = <&etf_out_port>;
 503                                         };
 504                                 };
 505                         };
 506                 };
 507
 508                 aips1: bus@30000000 {
 509                         compatible = "fsl,aips-bus", "simple-bus";
 510                         reg = <0x30000000 0x400000>;
 511                         #address-cells = <1>;
 512                         #size-cells = <1>;
 513                         ranges;
 514
 515                         gpio1: gpio@30200000 {
 516                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 517                                 reg = <0x30200000 0x10000>;
 518                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 519                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 520                                 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
 521                                 gpio-controller;
 522                                 #gpio-cells = <2>;
 523                                 interrupt-controller;
 524                                 #interrupt-cells = <2>;
 525                                 gpio-ranges = <&iomuxc 0 5 30>;
 526                         };
 527
 528                         gpio2: gpio@30210000 {
 529                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 530                                 reg = <0x30210000 0x10000>;
 531                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 532                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 533                                 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
 534                                 gpio-controller;
 535                                 #gpio-cells = <2>;
 536                                 interrupt-controller;
 537                                 #interrupt-cells = <2>;
 538                                 gpio-ranges = <&iomuxc 0 35 21>;
 539                         };
 540
 541                         gpio3: gpio@30220000 {
 542                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 543                                 reg = <0x30220000 0x10000>;
 544                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 545                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 546                                 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
 547                                 gpio-controller;
 548                                 #gpio-cells = <2>;
 549                                 interrupt-controller;
 550                                 #interrupt-cells = <2>;
 551                                 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
 552                         };
 553
 554                         gpio4: gpio@30230000 {
 555                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 556                                 reg = <0x30230000 0x10000>;
 557                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 558                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 559                                 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
 560                                 gpio-controller;
 561                                 #gpio-cells = <2>;
 562                                 interrupt-controller;
 563                                 #interrupt-cells = <2>;
 564                                 gpio-ranges = <&iomuxc 0 82 32>;
 565                         };
 566
 567                         gpio5: gpio@30240000 {
 568                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 569                                 reg = <0x30240000 0x10000>;
 570                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 571                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 572                                 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
 573                                 gpio-controller;
 574                                 #gpio-cells = <2>;
 575                                 interrupt-controller;
 576                                 #interrupt-cells = <2>;
 577                                 gpio-ranges = <&iomuxc 0 114 30>;
 578                         };
 579
 580                         tmu: tmu@30260000 {
 581                                 compatible = "fsl,imx8mp-tmu";
 582                                 reg = <0x30260000 0x10000>;
 583                                 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
 584                                 nvmem-cells = <&tmu_calib>;
 585                                 nvmem-cell-names = "calib";
 586                                 #thermal-sensor-cells = <1>;
 587                         };
 588
 589                         wdog1: watchdog@30280000 {
 590                                 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
 591                                 reg = <0x30280000 0x10000>;
 592                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 593                                 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
 594                                 status = "disabled";
 595                         };
 596
 597                         wdog2: watchdog@30290000 {
 598                                 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
 599                                 reg = <0x30290000 0x10000>;
 600                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 601                                 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>;
 602                                 status = "disabled";
 603                         };
 604
 605                         wdog3: watchdog@302a0000 {
 606                                 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
 607                                 reg = <0x302a0000 0x10000>;
 608                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 609                                 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>;
 610                                 status = "disabled";
 611                         };
 612
 613                         gpt1: timer@302d0000 {
 614                                 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
 615                                 reg = <0x302d0000 0x10000>;
 616                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 617                                 clocks = <&clk IMX8MP_CLK_GPT1_ROOT>, <&clk IMX8MP_CLK_GPT1>;
 618                                 clock-names = "ipg", "per";
 619                         };
 620
 621                         gpt2: timer@302e0000 {
 622                                 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
 623                                 reg = <0x302e0000 0x10000>;
 624                                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 625                                 clocks = <&clk IMX8MP_CLK_GPT2_ROOT>, <&clk IMX8MP_CLK_GPT2>;
 626                                 clock-names = "ipg", "per";
 627                         };
 628
 629                         gpt3: timer@302f0000 {
 630                                 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
 631                                 reg = <0x302f0000 0x10000>;
 632                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 633                                 clocks = <&clk IMX8MP_CLK_GPT3_ROOT>, <&clk IMX8MP_CLK_GPT3>;
 634                                 clock-names = "ipg", "per";
 635                         };
 636
 637                         iomuxc: pinctrl@30330000 {
 638                                 compatible = "fsl,imx8mp-iomuxc";
 639                                 reg = <0x30330000 0x10000>;
 640                         };
 641
 642                         gpr: syscon@30340000 {
 643                                 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
 644                                 reg = <0x30340000 0x10000>;
 645                         };
 646
 647                         ocotp: efuse@30350000 {
 648                                 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
 649                                 reg = <0x30350000 0x10000>;
 650                                 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
 651                                 /* For nvmem subnodes */
 652                                 #address-cells = <1>;
 653                                 #size-cells = <1>;
 654
 655                                 /*
 656                                  * The register address below maps to the MX8M
 657                                  * Fusemap Description Table entries this way.
 658                                  * Assuming
 659                                  *   reg = <ADDR SIZE>;
 660                                  * then
 661                                  *   Fuse Address = (ADDR * 4) + 0x400
 662                                  * Note that if SIZE is greater than 4, then
 663                                  * each subsequent fuse is located at offset
 664                                  * +0x10 in Fusemap Description Table (e.g.
 665                                  * reg = <0x8 0x8> describes fuses 0x420 and
 666                                  * 0x430).
 667                                  */
 668                                 imx8mp_uid: unique-id@8 { /* 0x420-0x430 */
 669                                         reg = <0x8 0x8>;
 670                                 };
 671
 672                                 cpu_speed_grade: speed-grade@10 { /* 0x440 */
 673                                         reg = <0x10 4>;
 674                                 };
 675
 676                                 eth_mac1: mac-address@90 { /* 0x640 */
 677                                         reg = <0x90 6>;
 678                                 };
 679
 680                                 eth_mac2: mac-address@96 { /* 0x658 */
 681                                         reg = <0x96 6>;
 682                                 };
 683
 684                                 tmu_calib: calib@264 { /* 0xd90-0xdc0 */
 685                                         reg = <0x264 0x10>;
 686                                 };
 687                         };
 688
 689                         anatop: clock-controller@30360000 {
 690                                 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop";
 691                                 reg = <0x30360000 0x10000>;
 692                                 #clock-cells = <1>;
 693                         };
 694
 695                         snvs: snvs@30370000 {
 696                                 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
 697                                 reg = <0x30370000 0x10000>;
 698
 699                                 snvs_rtc: snvs-rtc-lp {
 700                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 701                                         regmap = <&snvs>;
 702                                         offset = <0x34>;
 703                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 704                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 705                                         clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
 706                                         clock-names = "snvs-rtc";
 707                                 };
 708
 709                                 snvs_pwrkey: snvs-powerkey {
 710                                         compatible = "fsl,sec-v4.0-pwrkey";
 711                                         regmap = <&snvs>;
 712                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 713                                         clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
 714                                         clock-names = "snvs-pwrkey";
 715                                         linux,keycode = <KEY_POWER>;
 716                                         wakeup-source;
 717                                         status = "disabled";
 718                                 };
 719
 720                                 snvs_lpgpr: snvs-lpgpr {
 721                                         compatible = "fsl,imx8mp-snvs-lpgpr",
 722                                                      "fsl,imx7d-snvs-lpgpr";
 723                                 };
 724                         };
 725
 726                         clk: clock-controller@30380000 {
 727                                 compatible = "fsl,imx8mp-ccm";
 728                                 reg = <0x30380000 0x10000>;
 729                                 #clock-cells = <1>;
 730                                 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
 731                                          <&clk_ext3>, <&clk_ext4>;
 732                                 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
 733                                               "clk_ext3", "clk_ext4";
 734                                 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
 735                                                   <&clk IMX8MP_CLK_A53_CORE>,
 736                                                   <&clk IMX8MP_CLK_NOC>,
 737                                                   <&clk IMX8MP_CLK_NOC_IO>,
 738                                                   <&clk IMX8MP_CLK_GIC>;
 739                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
 740                                                          <&clk IMX8MP_ARM_PLL_OUT>,
 741                                                          <&clk IMX8MP_SYS_PLL2_1000M>,
 742                                                          <&clk IMX8MP_SYS_PLL1_800M>,
 743                                                          <&clk IMX8MP_SYS_PLL2_500M>;
 744                                 assigned-clock-rates = <0>, <0>,
 745                                                        <1000000000>,
 746                                                        <800000000>,
 747                                                        <500000000>;
 748                         };
 749
 750                         src: reset-controller@30390000 {
 751                                 compatible = "fsl,imx8mp-src", "syscon";
 752                                 reg = <0x30390000 0x10000>;
 753                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 754                                 #reset-cells = <1>;
 755                         };
 756
 757                         gpc: gpc@303a0000 {
 758                                 compatible = "fsl,imx8mp-gpc";
 759                                 reg = <0x303a0000 0x1000>;
 760                                 interrupt-parent = <&gic>;
 761                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 762                                 interrupt-controller;
 763                                 #interrupt-cells = <3>;
 764
 765                                 pgc {
 766                                         #address-cells = <1>;
 767                                         #size-cells = <0>;
 768
 769                                         pgc_mipi_phy1: power-domain@0 {
 770                                                 #power-domain-cells = <0>;
 771                                                 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>;
 772                                         };
 773
 774                                         pgc_pcie_phy: power-domain@1 {
 775                                                 #power-domain-cells = <0>;
 776                                                 reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
 777                                         };
 778
 779                                         pgc_usb1_phy: power-domain@2 {
 780                                                 #power-domain-cells = <0>;
 781                                                 reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>;
 782                                         };
 783
 784                                         pgc_usb2_phy: power-domain@3 {
 785                                                 #power-domain-cells = <0>;
 786                                                 reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
 787                                         };
 788
 789                                         pgc_audio: power-domain@5 {
 790                                                 #power-domain-cells = <0>;
 791                                                 reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>;
 792                                                 clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
 793                                                          <&clk IMX8MP_CLK_AUDIO_AXI>;
 794                                                 assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>,
 795                                                                   <&clk IMX8MP_CLK_AUDIO_AXI_SRC>;
 796                                                 assigned-clock-parents =  <&clk IMX8MP_SYS_PLL1_800M>,
 797                                                                           <&clk IMX8MP_SYS_PLL1_800M>;
 798                                                 assigned-clock-rates = <400000000>,
 799                                                                        <600000000>;
 800                                         };
 801
 802                                         pgc_gpu2d: power-domain@6 {
 803                                                 #power-domain-cells = <0>;
 804                                                 reg = <IMX8MP_POWER_DOMAIN_GPU2D>;
 805                                                 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>;
 806                                                 power-domains = <&pgc_gpumix>;
 807                                         };
 808
 809                                         pgc_gpumix: power-domain@7 {
 810                                                 #power-domain-cells = <0>;
 811                                                 reg = <IMX8MP_POWER_DOMAIN_GPUMIX>;
 812                                                 clocks = <&clk IMX8MP_CLK_GPU_ROOT>,
 813                                                          <&clk IMX8MP_CLK_GPU_AHB>;
 814                                                 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
 815                                                                   <&clk IMX8MP_CLK_GPU_AHB>;
 816                                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
 817                                                                          <&clk IMX8MP_SYS_PLL1_800M>;
 818                                                 assigned-clock-rates = <800000000>, <400000000>;
 819                                         };
 820
 821                                         pgc_gpu3d: power-domain@9 {
 822                                                 #power-domain-cells = <0>;
 823                                                 reg = <IMX8MP_POWER_DOMAIN_GPU3D>;
 824                                                 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
 825                                                          <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
 826                                                 power-domains = <&pgc_gpumix>;
 827                                         };
 828
 829                                         pgc_mediamix: power-domain@10 {
 830                                                 #power-domain-cells = <0>;
 831                                                 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>;
 832                                                 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
 833                                                          <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
 834                                         };
 835
 836                                         pgc_mipi_phy2: power-domain@16 {
 837                                                 #power-domain-cells = <0>;
 838                                                 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
 839                                         };
 840
 841                                         pgc_hsiomix: power-domain@17 {
 842                                                 #power-domain-cells = <0>;
 843                                                 reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
 844                                                 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
 845                                                          <&clk IMX8MP_CLK_HSIO_ROOT>;
 846                                                 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
 847                                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
 848                                                 assigned-clock-rates = <500000000>;
 849                                         };
 850
 851                                         pgc_ispdwp: power-domain@18 {
 852                                                 #power-domain-cells = <0>;
 853                                                 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
 854                                                 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>;
 855                                         };
 856
 857                                         pgc_vpumix: power-domain@19 {
 858                                                 #power-domain-cells = <0>;
 859                                                 reg = <IMX8MP_POWER_DOMAIN_VPUMIX>;
 860                                                 clocks = <&clk IMX8MP_CLK_VPU_ROOT>;
 861                                         };
 862
 863                                         pgc_vpu_g1: power-domain@20 {
 864                                                 #power-domain-cells = <0>;
 865                                                 power-domains = <&pgc_vpumix>;
 866                                                 reg = <IMX8MP_POWER_DOMAIN_VPU_G1>;
 867                                                 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
 868                                         };
 869
 870                                         pgc_vpu_g2: power-domain@21 {
 871                                                 #power-domain-cells = <0>;
 872                                                 power-domains = <&pgc_vpumix>;
 873                                                 reg = <IMX8MP_POWER_DOMAIN_VPU_G2>;
 874                                                 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
 875                                         };
 876
 877                                         pgc_vpu_vc8000e: power-domain@22 {
 878                                                 #power-domain-cells = <0>;
 879                                                 power-domains = <&pgc_vpumix>;
 880                                                 reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;
 881                                                 clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
 882                                         };
 883
 884                                         pgc_mlmix: power-domain@24 {
 885                                                 #power-domain-cells = <0>;
 886                                                 reg = <IMX8MP_POWER_DOMAIN_MLMIX>;
 887                                                 clocks = <&clk IMX8MP_CLK_ML_AXI>,
 888                                                          <&clk IMX8MP_CLK_ML_AHB>,
 889                                                          <&clk IMX8MP_CLK_NPU_ROOT>;
 890                                         };
 891                                 };
 892                         };
 893                 };
 894
 895                 aips2: bus@30400000 {
 896                         compatible = "fsl,aips-bus", "simple-bus";
 897                         reg = <0x30400000 0x400000>;
 898                         #address-cells = <1>;
 899                         #size-cells = <1>;
 900                         ranges;
 901
 902                         pwm1: pwm@30660000 {
 903                                 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
 904                                 reg = <0x30660000 0x10000>;
 905                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 906                                 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
 907                                          <&clk IMX8MP_CLK_PWM1_ROOT>;
 908                                 clock-names = "ipg", "per";
 909                                 #pwm-cells = <3>;
 910                                 status = "disabled";
 911                         };
 912
 913                         pwm2: pwm@30670000 {
 914                                 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
 915                                 reg = <0x30670000 0x10000>;
 916                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 917                                 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
 918                                          <&clk IMX8MP_CLK_PWM2_ROOT>;
 919                                 clock-names = "ipg", "per";
 920                                 #pwm-cells = <3>;
 921                                 status = "disabled";
 922                         };
 923
 924                         pwm3: pwm@30680000 {
 925                                 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
 926                                 reg = <0x30680000 0x10000>;
 927                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 928                                 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
 929                                          <&clk IMX8MP_CLK_PWM3_ROOT>;
 930                                 clock-names = "ipg", "per";
 931                                 #pwm-cells = <3>;
 932                                 status = "disabled";
 933                         };
 934
 935                         pwm4: pwm@30690000 {
 936                                 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
 937                                 reg = <0x30690000 0x10000>;
 938                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 939                                 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
 940                                          <&clk IMX8MP_CLK_PWM4_ROOT>;
 941                                 clock-names = "ipg", "per";
 942                                 #pwm-cells = <3>;
 943                                 status = "disabled";
 944                         };
 945
 946                         system_counter: timer@306a0000 {
 947                                 compatible = "nxp,sysctr-timer";
 948                                 reg = <0x306a0000 0x20000>;
 949                                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 950                                 clocks = <&osc_24m>;
 951                                 clock-names = "per";
 952                         };
 953
 954                         gpt6: timer@306e0000 {
 955                                 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
 956                                 reg = <0x306e0000 0x10000>;
 957                                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 958                                 clocks = <&clk IMX8MP_CLK_GPT6_ROOT>, <&clk IMX8MP_CLK_GPT6>;
 959                                 clock-names = "ipg", "per";
 960                         };
 961
 962                         gpt5: timer@306f0000 {
 963                                 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
 964                                 reg = <0x306f0000 0x10000>;
 965                                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 966                                 clocks = <&clk IMX8MP_CLK_GPT5_ROOT>, <&clk IMX8MP_CLK_GPT5>;
 967                                 clock-names = "ipg", "per";
 968                         };
 969
 970                         gpt4: timer@30700000 {
 971                                 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
 972                                 reg = <0x30700000 0x10000>;
 973                                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 974                                 clocks = <&clk IMX8MP_CLK_GPT4_ROOT>, <&clk IMX8MP_CLK_GPT4>;
 975                                 clock-names = "ipg", "per";
 976                         };
 977                 };
 978
 979                 aips3: bus@30800000 {
 980                         compatible = "fsl,aips-bus", "simple-bus";
 981                         reg = <0x30800000 0x400000>;
 982                         #address-cells = <1>;
 983                         #size-cells = <1>;
 984                         ranges;
 985
 986                         spba-bus@30800000 {
 987                                 compatible = "fsl,spba-bus", "simple-bus";
 988                                 reg = <0x30800000 0x100000>;
 989                                 #address-cells = <1>;
 990                                 #size-cells = <1>;
 991                                 ranges;
 992
 993                                 ecspi1: spi@30820000 {
 994                                         #address-cells = <1>;
 995                                         #size-cells = <0>;
 996                                         compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
 997                                         reg = <0x30820000 0x10000>;
 998                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 999                                         clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
1000                                                  <&clk IMX8MP_CLK_ECSPI1_ROOT>;
1001                                         clock-names = "ipg", "per";
1002                                         assigned-clock-rates = <80000000>;
1003                                         assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;
1004                                         assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1005                                         dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
1006                                         dma-names = "rx", "tx";
1007                                         status = "disabled";
1008                                 };
1009
1010                                 ecspi2: spi@30830000 {
1011                                         #address-cells = <1>;
1012                                         #size-cells = <0>;
1013                                         compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
1014                                         reg = <0x30830000 0x10000>;
1015                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1016                                         clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
1017                                                  <&clk IMX8MP_CLK_ECSPI2_ROOT>;
1018                                         clock-names = "ipg", "per";
1019                                         assigned-clock-rates = <80000000>;
1020                                         assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;
1021                                         assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1022                                         dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
1023                                         dma-names = "rx", "tx";
1024                                         status = "disabled";
1025                                 };
1026
1027                                 ecspi3: spi@30840000 {
1028                                         #address-cells = <1>;
1029                                         #size-cells = <0>;
1030                                         compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
1031                                         reg = <0x30840000 0x10000>;
1032                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1033                                         clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
1034                                                  <&clk IMX8MP_CLK_ECSPI3_ROOT>;
1035                                         clock-names = "ipg", "per";
1036                                         assigned-clock-rates = <80000000>;
1037                                         assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;
1038                                         assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1039                                         dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
1040                                         dma-names = "rx", "tx";
1041                                         status = "disabled";
1042                                 };
1043
1044                                 uart1: serial@30860000 {
1045                                         compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1046                                         reg = <0x30860000 0x10000>;
1047                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1048                                         clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
1049                                                  <&clk IMX8MP_CLK_UART1_ROOT>;
1050                                         clock-names = "ipg", "per";
1051                                         dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
1052                                         dma-names = "rx", "tx";
1053                                         status = "disabled";
1054                                 };
1055
1056                                 uart3: serial@30880000 {
1057                                         compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1058                                         reg = <0x30880000 0x10000>;
1059                                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1060                                         clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
1061                                                  <&clk IMX8MP_CLK_UART3_ROOT>;
1062                                         clock-names = "ipg", "per";
1063                                         dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
1064                                         dma-names = "rx", "tx";
1065                                         status = "disabled";
1066                                 };
1067
1068                                 uart2: serial@30890000 {
1069                                         compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1070                                         reg = <0x30890000 0x10000>;
1071                                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1072                                         clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
1073                                                  <&clk IMX8MP_CLK_UART2_ROOT>;
1074                                         clock-names = "ipg", "per";
1075                                         dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
1076                                         dma-names = "rx", "tx";
1077                                         status = "disabled";
1078                                 };
1079
1080                                 flexcan1: can@308c0000 {
1081                                         compatible = "fsl,imx8mp-flexcan";
1082                                         reg = <0x308c0000 0x10000>;
1083                                         interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
1084                                         clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
1085                                                  <&clk IMX8MP_CLK_CAN1_ROOT>;
1086                                         clock-names = "ipg", "per";
1087                                         assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
1088                                         assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
1089                                         assigned-clock-rates = <40000000>;
1090                                         fsl,clk-source = /bits/ 8 <0>;
1091                                         fsl,stop-mode = <&gpr 0x10 4>;
1092                                         status = "disabled";
1093                                 };
1094
1095                                 flexcan2: can@308d0000 {
1096                                         compatible = "fsl,imx8mp-flexcan";
1097                                         reg = <0x308d0000 0x10000>;
1098                                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
1099                                         clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
1100                                                  <&clk IMX8MP_CLK_CAN2_ROOT>;
1101                                         clock-names = "ipg", "per";
1102                                         assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
1103                                         assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
1104                                         assigned-clock-rates = <40000000>;
1105                                         fsl,clk-source = /bits/ 8 <0>;
1106                                         fsl,stop-mode = <&gpr 0x10 5>;
1107                                         status = "disabled";
1108                                 };
1109                         };
1110
1111                         crypto: crypto@30900000 {
1112                                 compatible = "fsl,sec-v4.0";
1113                                 #address-cells = <1>;
1114                                 #size-cells = <1>;
1115                                 reg = <0x30900000 0x40000>;
1116                                 ranges = <0 0x30900000 0x40000>;
1117                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1118                                 clocks = <&clk IMX8MP_CLK_AHB>,
1119                                          <&clk IMX8MP_CLK_IPG_ROOT>;
1120                                 clock-names = "aclk", "ipg";
1121
1122                                 sec_jr0: jr@1000 {
1123                                         compatible = "fsl,sec-v4.0-job-ring";
1124                                         reg = <0x1000 0x1000>;
1125                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1126                                         status = "disabled";
1127                                 };
1128
1129                                 sec_jr1: jr@2000 {
1130                                         compatible = "fsl,sec-v4.0-job-ring";
1131                                         reg = <0x2000 0x1000>;
1132                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1133                                 };
1134
1135                                 sec_jr2: jr@3000 {
1136                                         compatible = "fsl,sec-v4.0-job-ring";
1137                                         reg = <0x3000 0x1000>;
1138                                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1139                                 };
1140                         };
1141
1142                         i2c1: i2c@30a20000 {
1143                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1144                                 #address-cells = <1>;
1145                                 #size-cells = <0>;
1146                                 reg = <0x30a20000 0x10000>;
1147                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1148                                 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>;
1149                                 status = "disabled";
1150                         };
1151
1152                         i2c2: i2c@30a30000 {
1153                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1154                                 #address-cells = <1>;
1155                                 #size-cells = <0>;
1156                                 reg = <0x30a30000 0x10000>;
1157                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1158                                 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>;
1159                                 status = "disabled";
1160                         };
1161
1162                         i2c3: i2c@30a40000 {
1163                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1164                                 #address-cells = <1>;
1165                                 #size-cells = <0>;
1166                                 reg = <0x30a40000 0x10000>;
1167                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1168                                 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
1169                                 status = "disabled";
1170                         };
1171
1172                         i2c4: i2c@30a50000 {
1173                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1174                                 #address-cells = <1>;
1175                                 #size-cells = <0>;
1176                                 reg = <0x30a50000 0x10000>;
1177                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1178                                 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>;
1179                                 status = "disabled";
1180                         };
1181
1182                         uart4: serial@30a60000 {
1183                                 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1184                                 reg = <0x30a60000 0x10000>;
1185                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1186                                 clocks = <&clk IMX8MP_CLK_UART4_ROOT>,
1187                                          <&clk IMX8MP_CLK_UART4_ROOT>;
1188                                 clock-names = "ipg", "per";
1189                                 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
1190                                 dma-names = "rx", "tx";
1191                                 status = "disabled";
1192                         };
1193
1194                         mu: mailbox@30aa0000 {
1195                                 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
1196                                 reg = <0x30aa0000 0x10000>;
1197                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1198                                 clocks = <&clk IMX8MP_CLK_MU_ROOT>;
1199                                 #mbox-cells = <2>;
1200                         };
1201
1202                         mu2: mailbox@30e60000 {
1203                                 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
1204                                 reg = <0x30e60000 0x10000>;
1205                                 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1206                                 #mbox-cells = <2>;
1207                                 status = "disabled";
1208                         };
1209
1210                         i2c5: i2c@30ad0000 {
1211                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1212                                 #address-cells = <1>;
1213                                 #size-cells = <0>;
1214                                 reg = <0x30ad0000 0x10000>;
1215                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
1216                                 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>;
1217                                 status = "disabled";
1218                         };
1219
1220                         i2c6: i2c@30ae0000 {
1221                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1222                                 #address-cells = <1>;
1223                                 #size-cells = <0>;
1224                                 reg = <0x30ae0000 0x10000>;
1225                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1226                                 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>;
1227                                 status = "disabled";
1228                         };
1229
1230                         usdhc1: mmc@30b40000 {
1231                                 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1232                                 reg = <0x30b40000 0x10000>;
1233                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1234                                 clocks = <&clk IMX8MP_CLK_DUMMY>,
1235                                          <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
1236                                          <&clk IMX8MP_CLK_USDHC1_ROOT>;
1237                                 clock-names = "ipg", "ahb", "per";
1238                                 fsl,tuning-start-tap = <20>;
1239                                 fsl,tuning-step = <2>;
1240                                 bus-width = <4>;
1241                                 status = "disabled";
1242                         };
1243
1244                         usdhc2: mmc@30b50000 {
1245                                 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1246                                 reg = <0x30b50000 0x10000>;
1247                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1248                                 clocks = <&clk IMX8MP_CLK_DUMMY>,
1249                                          <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
1250                                          <&clk IMX8MP_CLK_USDHC2_ROOT>;
1251                                 clock-names = "ipg", "ahb", "per";
1252                                 fsl,tuning-start-tap = <20>;
1253                                 fsl,tuning-step = <2>;
1254                                 bus-width = <4>;
1255                                 status = "disabled";
1256                         };
1257
1258                         usdhc3: mmc@30b60000 {
1259                                 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1260                                 reg = <0x30b60000 0x10000>;
1261                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1262                                 clocks = <&clk IMX8MP_CLK_DUMMY>,
1263                                          <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
1264                                          <&clk IMX8MP_CLK_USDHC3_ROOT>;
1265                                 clock-names = "ipg", "ahb", "per";
1266                                 fsl,tuning-start-tap = <20>;
1267                                 fsl,tuning-step = <2>;
1268                                 bus-width = <4>;
1269                                 status = "disabled";
1270                         };
1271
1272                         flexspi: spi@30bb0000 {
1273                                 compatible = "nxp,imx8mp-fspi";
1274                                 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
1275                                 reg-names = "fspi_base", "fspi_mmap";
1276                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1277                                 clocks = <&clk IMX8MP_CLK_QSPI_ROOT>,
1278                                          <&clk IMX8MP_CLK_QSPI_ROOT>;
1279                                 clock-names = "fspi_en", "fspi";
1280                                 assigned-clock-rates = <80000000>;
1281                                 assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
1282                                 #address-cells = <1>;
1283                                 #size-cells = <0>;
1284                                 status = "disabled";
1285                         };
1286
1287                         sdma1: dma-controller@30bd0000 {
1288                                 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1289                                 reg = <0x30bd0000 0x10000>;
1290                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1291                                 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
1292                                          <&clk IMX8MP_CLK_AHB>;
1293                                 clock-names = "ipg", "ahb";
1294                                 #dma-cells = <3>;
1295                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1296                         };
1297
1298                         fec: ethernet@30be0000 {
1299                                 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1300                                 reg = <0x30be0000 0x10000>;
1301                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1302                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1303                                              <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1304                                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1305                                 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
1306                                          <&clk IMX8MP_CLK_SIM_ENET_ROOT>,
1307                                          <&clk IMX8MP_CLK_ENET_TIMER>,
1308                                          <&clk IMX8MP_CLK_ENET_REF>,
1309                                          <&clk IMX8MP_CLK_ENET_PHY_REF>;
1310                                 clock-names = "ipg", "ahb", "ptp",
1311                                               "enet_clk_ref", "enet_out";
1312                                 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1313                                                   <&clk IMX8MP_CLK_ENET_TIMER>,
1314                                                   <&clk IMX8MP_CLK_ENET_REF>,
1315                                                   <&clk IMX8MP_CLK_ENET_PHY_REF>;
1316                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1317                                                          <&clk IMX8MP_SYS_PLL2_100M>,
1318                                                          <&clk IMX8MP_SYS_PLL2_125M>,
1319                                                          <&clk IMX8MP_SYS_PLL2_50M>;
1320                                 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1321                                 fsl,num-tx-queues = <3>;
1322                                 fsl,num-rx-queues = <3>;
1323                                 nvmem-cells = <&eth_mac1>;
1324                                 nvmem-cell-names = "mac-address";
1325                                 fsl,stop-mode = <&gpr 0x10 3>;
1326                                 status = "disabled";
1327                         };
1328
1329                         eqos: ethernet@30bf0000 {
1330                                 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
1331                                 reg = <0x30bf0000 0x10000>;
1332                                 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1333                                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
1334                                 interrupt-names = "macirq", "eth_wake_irq";
1335                                 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
1336                                          <&clk IMX8MP_CLK_QOS_ENET_ROOT>,
1337                                          <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
1338                                          <&clk IMX8MP_CLK_ENET_QOS>;
1339                                 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
1340                                 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1341                                                   <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
1342                                                   <&clk IMX8MP_CLK_ENET_QOS>;
1343                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1344                                                          <&clk IMX8MP_SYS_PLL2_100M>,
1345                                                          <&clk IMX8MP_SYS_PLL2_125M>;
1346                                 assigned-clock-rates = <0>, <100000000>, <125000000>;
1347                                 nvmem-cells = <&eth_mac2>;
1348                                 nvmem-cell-names = "mac-address";
1349                                 intf_mode = <&gpr 0x4>;
1350                                 status = "disabled";
1351                         };
1352                 };
1353
1354                 aips5: bus@30c00000 {
1355                         compatible = "fsl,aips-bus", "simple-bus";
1356                         reg = <0x30c00000 0x400000>;
1357                         #address-cells = <1>;
1358                         #size-cells = <1>;
1359                         ranges;
1360
1361                         spba-bus@30c00000 {
1362                                 compatible = "fsl,spba-bus", "simple-bus";
1363                                 reg = <0x30c00000 0x100000>;
1364                                 #address-cells = <1>;
1365                                 #size-cells = <1>;
1366                                 ranges;
1367
1368                                 sai1: sai@30c10000 {
1369                                         compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1370                                         reg = <0x30c10000 0x10000>;
1371                                         #sound-dai-cells = <0>;
1372                                         clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_IPG>,
1373                                                  <&clk IMX8MP_CLK_DUMMY>,
1374                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>,
1375                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2>,
1376                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3>;
1377                                         clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1378                                         dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
1379                                         dma-names = "rx", "tx";
1380                                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1381                                         status = "disabled";
1382                                 };
1383
1384                                 sai2: sai@30c20000 {
1385                                         compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1386                                         reg = <0x30c20000 0x10000>;
1387                                         #sound-dai-cells = <0>;
1388                                         clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_IPG>,
1389                                                  <&clk IMX8MP_CLK_DUMMY>,
1390                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>,
1391                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2>,
1392                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3>;
1393                                         clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1394                                         dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
1395                                         dma-names = "rx", "tx";
1396                                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1397                                         status = "disabled";
1398                                 };
1399
1400                                 sai3: sai@30c30000 {
1401                                         compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1402                                         reg = <0x30c30000 0x10000>;
1403                                         #sound-dai-cells = <0>;
1404                                         clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>,
1405                                                  <&clk IMX8MP_CLK_DUMMY>,
1406                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>,
1407                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2>,
1408                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3>;
1409                                         clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1410                                         dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
1411                                         dma-names = "rx", "tx";
1412                                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1413                                         status = "disabled";
1414                                 };
1415
1416                                 sai5: sai@30c50000 {
1417                                         compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1418                                         reg = <0x30c50000 0x10000>;
1419                                         #sound-dai-cells = <0>;
1420                                         clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>,
1421                                                  <&clk IMX8MP_CLK_DUMMY>,
1422                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>,
1423                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2>,
1424                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3>;
1425                                         clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1426                                         dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
1427                                         dma-names = "rx", "tx";
1428                                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1429                                         status = "disabled";
1430                                 };
1431
1432                                 sai6: sai@30c60000 {
1433                                         compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1434                                         reg = <0x30c60000 0x10000>;
1435                                         #sound-dai-cells = <0>;
1436                                         clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_IPG>,
1437                                                  <&clk IMX8MP_CLK_DUMMY>,
1438                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>,
1439                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2>,
1440                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3>;
1441                                         clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1442                                         dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
1443                                         dma-names = "rx", "tx";
1444                                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1445                                         status = "disabled";
1446                                 };
1447
1448                                 sai7: sai@30c80000 {
1449                                         compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1450                                         reg = <0x30c80000 0x10000>;
1451                                         #sound-dai-cells = <0>;
1452                                         clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_IPG>,
1453                                                  <&clk IMX8MP_CLK_DUMMY>,
1454                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>,
1455                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2>,
1456                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3>;
1457                                         clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1458                                         dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
1459                                         dma-names = "rx", "tx";
1460                                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1461                                         status = "disabled";
1462                                 };
1463
1464                                 easrc: easrc@30c90000 {
1465                                         compatible = "fsl,imx8mp-easrc", "fsl,imx8mn-easrc";
1466                                         reg = <0x30c90000 0x10000>;
1467                                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1468                                         clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_ASRC_IPG>;
1469                                         clock-names = "mem";
1470                                         dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
1471                                                <&sdma2 18 23 0> , <&sdma2 19 23 0>,
1472                                                <&sdma2 20 23 0> , <&sdma2 21 23 0>,
1473                                                <&sdma2 22 23 0> , <&sdma2 23 23 0>;
1474                                         dma-names = "ctx0_rx", "ctx0_tx",
1475                                                     "ctx1_rx", "ctx1_tx",
1476                                                     "ctx2_rx", "ctx2_tx",
1477                                                     "ctx3_rx", "ctx3_tx";
1478                                         firmware-name = "imx/easrc/easrc-imx8mn.bin";
1479                                         fsl,asrc-rate = <8000>;
1480                                         fsl,asrc-format = <2>;
1481                                         status = "disabled";
1482                                 };
1483
1484                                 micfil: audio-controller@30ca0000 {
1485                                         compatible = "fsl,imx8mp-micfil";
1486                                         reg = <0x30ca0000 0x10000>;
1487                                         #sound-dai-cells = <0>;
1488                                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1489                                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1490                                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1491                                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1492                                         clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_IPG>,
1493                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_SEL>,
1494                                                  <&clk IMX8MP_AUDIO_PLL1_OUT>,
1495                                                  <&clk IMX8MP_AUDIO_PLL2_OUT>,
1496                                                  <&clk IMX8MP_CLK_EXT3>;
1497                                         clock-names = "ipg_clk", "ipg_clk_app",
1498                                                       "pll8k", "pll11k", "clkext3";
1499                                         dmas = <&sdma2 24 25 0x80000000>;
1500                                         dma-names = "rx";
1501                                         status = "disabled";
1502                                 };
1503
1504                         };
1505
1506                         sdma3: dma-controller@30e00000 {
1507                                 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1508                                 reg = <0x30e00000 0x10000>;
1509                                 #dma-cells = <3>;
1510                                 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>,
1511                                          <&clk IMX8MP_CLK_AUDIO_ROOT>;
1512                                 clock-names = "ipg", "ahb";
1513                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1514                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1515                         };
1516
1517                         sdma2: dma-controller@30e10000 {
1518                                 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1519                                 reg = <0x30e10000 0x10000>;
1520                                 #dma-cells = <3>;
1521                                 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>,
1522                                          <&clk IMX8MP_CLK_AUDIO_ROOT>;
1523                                 clock-names = "ipg", "ahb";
1524                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1525                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1526                         };
1527
1528                         audio_blk_ctrl: clock-controller@30e20000 {
1529                                 compatible = "fsl,imx8mp-audio-blk-ctrl";
1530                                 reg = <0x30e20000 0x10000>;
1531                                 #clock-cells = <1>;
1532                                 clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
1533                                          <&clk IMX8MP_CLK_SAI1>,
1534                                          <&clk IMX8MP_CLK_SAI2>,
1535                                          <&clk IMX8MP_CLK_SAI3>,
1536                                          <&clk IMX8MP_CLK_SAI5>,
1537                                          <&clk IMX8MP_CLK_SAI6>,
1538                                          <&clk IMX8MP_CLK_SAI7>;
1539                                 clock-names = "ahb",
1540                                               "sai1", "sai2", "sai3",
1541                                               "sai5", "sai6", "sai7";
1542                                 power-domains = <&pgc_audio>;
1543                         };
1544                 };
1545
1546                 noc: interconnect@32700000 {
1547                         compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc";
1548                         reg = <0x32700000 0x100000>;
1549                         clocks = <&clk IMX8MP_CLK_NOC>;
1550                         #interconnect-cells = <1>;
1551                         operating-points-v2 = <&noc_opp_table>;
1552
1553                         noc_opp_table: opp-table {
1554                                 compatible = "operating-points-v2";
1555
1556                                 opp-200000000 {
1557                                         opp-hz = /bits/ 64 <200000000>;
1558                                 };
1559
1560                                 opp-1000000000 {
1561                                         opp-hz = /bits/ 64 <1000000000>;
1562                                 };
1563                         };
1564                 };
1565
1566                 aips4: bus@32c00000 {
1567                         compatible = "fsl,aips-bus", "simple-bus";
1568                         reg = <0x32c00000 0x400000>;
1569                         #address-cells = <1>;
1570                         #size-cells = <1>;
1571                         ranges;
1572
1573                         isi_0: isi@32e00000 {
1574                                 compatible = "fsl,imx8mp-isi";
1575                                 reg = <0x32e00000 0x4000>;
1576                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1577                                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1578                                 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1579                                          <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
1580                                 clock-names = "axi", "apb";
1581                                 fsl,blk-ctrl = <&media_blk_ctrl>;
1582                                 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>;
1583                                 status = "disabled";
1584
1585                                 ports {
1586                                         #address-cells = <1>;
1587                                         #size-cells = <0>;
1588
1589                                         port@0 {
1590                                                 reg = <0>;
1591
1592                                                 isi_in_0: endpoint {
1593                                                         remote-endpoint = <&mipi_csi_0_out>;
1594                                                 };
1595                                         };
1596
1597                                         port@1 {
1598                                                 reg = <1>;
1599
1600                                                 isi_in_1: endpoint {
1601                                                         remote-endpoint = <&mipi_csi_1_out>;
1602                                                 };
1603                                         };
1604                                 };
1605                         };
1606
1607                         dewarp: dwe@32e30000 {
1608                                 compatible = "nxp,imx8mp-dw100";
1609                                 reg = <0x32e30000 0x10000>;
1610                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1611                                 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1612                                          <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
1613                                 clock-names = "axi", "ahb";
1614                                 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>;
1615                         };
1616
1617                         mipi_csi_0: csi@32e40000 {
1618                                 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
1619                                 reg = <0x32e40000 0x10000>;
1620                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1621                                 clock-frequency = <500000000>;
1622                                 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1623                                          <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
1624                                          <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
1625                                          <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
1626                                 clock-names = "pclk", "wrap", "phy", "axi";
1627                                 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>;
1628                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
1629                                 assigned-clock-rates = <500000000>;
1630                                 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>;
1631                                 status = "disabled";
1632
1633                                 ports {
1634                                         #address-cells = <1>;
1635                                         #size-cells = <0>;
1636
1637                                         port@0 {
1638                                                 reg = <0>;
1639                                         };
1640
1641                                         port@1 {
1642                                                 reg = <1>;
1643
1644                                                 mipi_csi_0_out: endpoint {
1645                                                         remote-endpoint = <&isi_in_0>;
1646                                                 };
1647                                         };
1648                                 };
1649                         };
1650
1651                         mipi_csi_1: csi@32e50000 {
1652                                 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
1653                                 reg = <0x32e50000 0x10000>;
1654                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1655                                 clock-frequency = <266000000>;
1656                                 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1657                                          <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
1658                                          <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
1659                                          <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
1660                                 clock-names = "pclk", "wrap", "phy", "axi";
1661                                 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>;
1662                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
1663                                 assigned-clock-rates = <266000000>;
1664                                 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>;
1665                                 status = "disabled";
1666
1667                                 ports {
1668                                         #address-cells = <1>;
1669                                         #size-cells = <0>;
1670
1671                                         port@0 {
1672                                                 reg = <0>;
1673                                         };
1674
1675                                         port@1 {
1676                                                 reg = <1>;
1677
1678                                                 mipi_csi_1_out: endpoint {
1679                                                         remote-endpoint = <&isi_in_1>;
1680                                                 };
1681                                         };
1682                                 };
1683                         };
1684
1685                         mipi_dsi: dsi@32e60000 {
1686                                 compatible = "fsl,imx8mp-mipi-dsim";
1687                                 reg = <0x32e60000 0x400>;
1688                                 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1689                                          <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
1690                                 clock-names = "bus_clk", "sclk_mipi";
1691                                 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>,
1692                                                   <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
1693                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
1694                                                          <&clk IMX8MP_CLK_24M>;
1695                                 assigned-clock-rates = <200000000>, <24000000>;
1696                                 samsung,pll-clock-frequency = <24000000>;
1697                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1698                                 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>;
1699                                 status = "disabled";
1700
1701                                 ports {
1702                                         #address-cells = <1>;
1703                                         #size-cells = <0>;
1704
1705                                         port@0 {
1706                                                 reg = <0>;
1707
1708                                                 dsim_from_lcdif1: endpoint {
1709                                                         remote-endpoint = <&lcdif1_to_dsim>;
1710                                                 };
1711                                         };
1712                                 };
1713                         };
1714
1715                         lcdif1: display-controller@32e80000 {
1716                                 compatible = "fsl,imx8mp-lcdif";
1717                                 reg = <0x32e80000 0x10000>;
1718                                 clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
1719                                          <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1720                                          <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
1721                                 clock-names = "pix", "axi", "disp_axi";
1722                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1723                                 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>;
1724                                 status = "disabled";
1725
1726                                 port {
1727                                         lcdif1_to_dsim: endpoint {
1728                                                 remote-endpoint = <&dsim_from_lcdif1>;
1729                                         };
1730                                 };
1731                         };
1732
1733                         lcdif2: display-controller@32e90000 {
1734                                 compatible = "fsl,imx8mp-lcdif";
1735                                 reg = <0x32e90000 0x10000>;
1736                                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1737                                 clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
1738                                          <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1739                                          <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
1740                                 clock-names = "pix", "axi", "disp_axi";
1741                                 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>;
1742                                 status = "disabled";
1743
1744                                 port {
1745                                         lcdif2_to_ldb: endpoint {
1746                                                 remote-endpoint = <&ldb_from_lcdif2>;
1747                                         };
1748                                 };
1749                         };
1750
1751                         media_blk_ctrl: blk-ctrl@32ec0000 {
1752                                 compatible = "fsl,imx8mp-media-blk-ctrl",
1753                                              "syscon";
1754                                 reg = <0x32ec0000 0x10000>;
1755                                 #address-cells = <1>;
1756                                 #size-cells = <1>;
1757                                 power-domains = <&pgc_mediamix>,
1758                                                 <&pgc_mipi_phy1>,
1759                                                 <&pgc_mipi_phy1>,
1760                                                 <&pgc_mediamix>,
1761                                                 <&pgc_mediamix>,
1762                                                 <&pgc_mipi_phy2>,
1763                                                 <&pgc_mediamix>,
1764                                                 <&pgc_ispdwp>,
1765                                                 <&pgc_ispdwp>,
1766                                                 <&pgc_mipi_phy2>;
1767                                 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1",
1768                                                      "lcdif1", "isi", "mipi-csi2",
1769                                                      "lcdif2", "isp", "dwe",
1770                                                      "mipi-dsi2";
1771                                 interconnects =
1772                                         <&noc IMX8MP_ICM_LCDIF_RD &noc IMX8MP_ICN_MEDIA>,
1773                                         <&noc IMX8MP_ICM_LCDIF_WR &noc IMX8MP_ICN_MEDIA>,
1774                                         <&noc IMX8MP_ICM_ISI0 &noc IMX8MP_ICN_MEDIA>,
1775                                         <&noc IMX8MP_ICM_ISI1 &noc IMX8MP_ICN_MEDIA>,
1776                                         <&noc IMX8MP_ICM_ISI2 &noc IMX8MP_ICN_MEDIA>,
1777                                         <&noc IMX8MP_ICM_ISP0 &noc IMX8MP_ICN_MEDIA>,
1778                                         <&noc IMX8MP_ICM_ISP1 &noc IMX8MP_ICN_MEDIA>,
1779                                         <&noc IMX8MP_ICM_DWE &noc IMX8MP_ICN_MEDIA>;
1780                                 interconnect-names = "lcdif-rd", "lcdif-wr", "isi0",
1781                                                      "isi1", "isi2", "isp0", "isp1",
1782                                                      "dwe";
1783                                 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1784                                          <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1785                                          <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
1786                                          <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
1787                                          <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
1788                                          <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
1789                                          <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
1790                                          <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
1791                                 clock-names = "apb", "axi", "cam1", "cam2",
1792                                               "disp1", "disp2", "isp", "phy";
1793
1794                                 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
1795                                                   <&clk IMX8MP_CLK_MEDIA_APB>,
1796                                                   <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
1797                                                   <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
1798                                                   <&clk IMX8MP_VIDEO_PLL1>;
1799                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
1800                                                          <&clk IMX8MP_SYS_PLL1_800M>,
1801                                                          <&clk IMX8MP_VIDEO_PLL1_OUT>,
1802                                                          <&clk IMX8MP_VIDEO_PLL1_OUT>;
1803                                 assigned-clock-rates = <500000000>, <200000000>,
1804                                                        <0>, <0>, <1039500000>;
1805                                 #power-domain-cells = <1>;
1806
1807                                 lvds_bridge: bridge@5c {
1808                                         compatible = "fsl,imx8mp-ldb";
1809                                         reg = <0x5c 0x4>, <0x128 0x4>;
1810                                         reg-names = "ldb", "lvds";
1811                                         clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
1812                                         clock-names = "ldb";
1813                                         assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
1814                                         assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
1815                                         status = "disabled";
1816
1817                                         ports {
1818                                                 #address-cells = <1>;
1819                                                 #size-cells = <0>;
1820
1821                                                 port@0 {
1822                                                         reg = <0>;
1823
1824                                                         ldb_from_lcdif2: endpoint {
1825                                                                 remote-endpoint = <&lcdif2_to_ldb>;
1826                                                         };
1827                                                 };
1828
1829                                                 port@1 {
1830                                                         reg = <1>;
1831
1832                                                         ldb_lvds_ch0: endpoint {
1833                                                         };
1834                                                 };
1835
1836                                                 port@2 {
1837                                                         reg = <2>;
1838
1839                                                         ldb_lvds_ch1: endpoint {
1840                                                         };
1841                                                 };
1842                                         };
1843                                 };
1844                         };
1845
1846                         pcie_phy: pcie-phy@32f00000 {
1847                                 compatible = "fsl,imx8mp-pcie-phy";
1848                                 reg = <0x32f00000 0x10000>;
1849                                 resets = <&src IMX8MP_RESET_PCIEPHY>,
1850                                          <&src IMX8MP_RESET_PCIEPHY_PERST>;
1851                                 reset-names = "pciephy", "perst";
1852                                 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>;
1853                                 #phy-cells = <0>;
1854                                 status = "disabled";
1855                         };
1856
1857                         hsio_blk_ctrl: blk-ctrl@32f10000 {
1858                                 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
1859                                 reg = <0x32f10000 0x24>;
1860                                 clocks = <&clk IMX8MP_CLK_USB_ROOT>,
1861                                          <&clk IMX8MP_CLK_PCIE_ROOT>;
1862                                 clock-names = "usb", "pcie";
1863                                 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
1864                                                 <&pgc_usb1_phy>, <&pgc_usb2_phy>,
1865                                                 <&pgc_hsiomix>, <&pgc_pcie_phy>;
1866                                 power-domain-names = "bus", "usb", "usb-phy1",
1867                                                      "usb-phy2", "pcie", "pcie-phy";
1868                                 interconnects = <&noc IMX8MP_ICM_NOC_PCIE &noc IMX8MP_ICN_HSIO>,
1869                                                 <&noc IMX8MP_ICM_USB1 &noc IMX8MP_ICN_HSIO>,
1870                                                 <&noc IMX8MP_ICM_USB2 &noc IMX8MP_ICN_HSIO>,
1871                                                 <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>;
1872                                 interconnect-names = "noc-pcie", "usb1", "usb2", "pcie";
1873                                 #power-domain-cells = <1>;
1874                                 #clock-cells = <0>;
1875                         };
1876                 };
1877
1878                 pcie: pcie@33800000 {
1879                         compatible = "fsl,imx8mp-pcie";
1880                         reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
1881                         reg-names = "dbi", "config";
1882                         clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
1883                                  <&clk IMX8MP_CLK_HSIO_AXI>,
1884                                  <&clk IMX8MP_CLK_PCIE_ROOT>;
1885                         clock-names = "pcie", "pcie_bus", "pcie_aux";
1886                         assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
1887                         assigned-clock-rates = <10000000>;
1888                         assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
1889                         #address-cells = <3>;
1890                         #size-cells = <2>;
1891                         device_type = "pci";
1892                         bus-range = <0x00 0xff>;
1893                         ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
1894                                  <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1895                         num-lanes = <1>;
1896                         num-viewport = <4>;
1897                         interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1898                         interrupt-names = "msi";
1899                         #interrupt-cells = <1>;
1900                         interrupt-map-mask = <0 0 0 0x7>;
1901                         interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1902                                         <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1903                                         <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1904                                         <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1905                         fsl,max-link-speed = <3>;
1906                         linux,pci-domain = <0>;
1907                         power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
1908                         resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
1909                                  <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
1910                         reset-names = "apps", "turnoff";
1911                         phys = <&pcie_phy>;
1912                         phy-names = "pcie-phy";
1913                         status = "disabled";
1914                 };
1915
1916                 pcie_ep: pcie-ep@33800000 {
1917                         compatible = "fsl,imx8mp-pcie-ep";
1918                         reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>;
1919                         reg-names = "dbi", "addr_space";
1920                         clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
1921                                  <&clk IMX8MP_CLK_HSIO_AXI>,
1922                                  <&clk IMX8MP_CLK_PCIE_ROOT>;
1923                         clock-names = "pcie", "pcie_bus", "pcie_aux";
1924                         assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
1925                         assigned-clock-rates = <10000000>;
1926                         assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
1927                         num-lanes = <1>;
1928                         interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
1929                         interrupt-names = "dma";
1930                         fsl,max-link-speed = <3>;
1931                         power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
1932                         resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
1933                                  <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
1934                         reset-names = "apps", "turnoff";
1935                         phys = <&pcie_phy>;
1936                         phy-names = "pcie-phy";
1937                         num-ib-windows = <4>;
1938                         num-ob-windows = <4>;
1939                         status = "disabled";
1940                 };
1941
1942                 gpu3d: gpu@38000000 {
1943                         compatible = "vivante,gc";
1944                         reg = <0x38000000 0x8000>;
1945                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1946                         clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
1947                                  <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>,
1948                                  <&clk IMX8MP_CLK_GPU_ROOT>,
1949                                  <&clk IMX8MP_CLK_GPU_AHB>;
1950                         clock-names = "core", "shader", "bus", "reg";
1951                         assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
1952                                           <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
1953                         assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
1954                                                  <&clk IMX8MP_SYS_PLL1_800M>;
1955                         assigned-clock-rates = <800000000>, <800000000>;
1956                         power-domains = <&pgc_gpu3d>;
1957                 };
1958
1959                 gpu2d: gpu@38008000 {
1960                         compatible = "vivante,gc";
1961                         reg = <0x38008000 0x8000>;
1962                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1963                         clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>,
1964                                  <&clk IMX8MP_CLK_GPU_ROOT>,
1965                                  <&clk IMX8MP_CLK_GPU_AHB>;
1966                         clock-names = "core", "bus", "reg";
1967                         assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
1968                         assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1969                         assigned-clock-rates = <800000000>;
1970                         power-domains = <&pgc_gpu2d>;
1971                 };
1972
1973                 vpu_g1: video-codec@38300000 {
1974                         compatible = "nxp,imx8mm-vpu-g1";
1975                         reg = <0x38300000 0x10000>;
1976                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1977                         clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
1978                         assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>;
1979                         assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;
1980                         assigned-clock-rates = <600000000>;
1981                         power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>;
1982                 };
1983
1984                 vpu_g2: video-codec@38310000 {
1985                         compatible = "nxp,imx8mq-vpu-g2";
1986                         reg = <0x38310000 0x10000>;
1987                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1988                         clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
1989                         assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>;
1990                         assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
1991                         assigned-clock-rates = <500000000>;
1992                         power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>;
1993                 };
1994
1995                 vpumix_blk_ctrl: blk-ctrl@38330000 {
1996                         compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon";
1997                         reg = <0x38330000 0x100>;
1998                         #power-domain-cells = <1>;
1999                         power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
2000                                         <&pgc_vpu_g2>, <&pgc_vpu_vc8000e>;
2001                         power-domain-names = "bus", "g1", "g2", "vc8000e";
2002                         clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>,
2003                                  <&clk IMX8MP_CLK_VPU_G2_ROOT>,
2004                                  <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
2005                         clock-names = "g1", "g2", "vc8000e";
2006                         assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>;
2007                         assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;
2008                         assigned-clock-rates = <600000000>, <600000000>;
2009                         interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>,
2010                                         <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>,
2011                                         <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>;
2012                         interconnect-names = "g1", "g2", "vc8000e";
2013                 };
2014
2015                 gic: interrupt-controller@38800000 {
2016                         compatible = "arm,gic-v3";
2017                         reg = <0x38800000 0x10000>,
2018                               <0x38880000 0xc0000>;
2019                         #interrupt-cells = <3>;
2020                         interrupt-controller;
2021                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2022                         interrupt-parent = <&gic>;
2023                 };
2024
2025                 edacmc: memory-controller@3d400000 {
2026                         compatible = "snps,ddrc-3.80a";
2027                         reg = <0x3d400000 0x400000>;
2028                         interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
2029                 };
2030
2031                 ddr-pmu@3d800000 {
2032                         compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
2033                         reg = <0x3d800000 0x400000>;
2034                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2035                 };
2036
2037                 usb3_phy0: usb-phy@381f0040 {
2038                         compatible = "fsl,imx8mp-usb-phy";
2039                         reg = <0x381f0040 0x40>;
2040                         clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
2041                         clock-names = "phy";
2042                         assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
2043                         assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2044                         power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
2045                         #phy-cells = <0>;
2046                         status = "disabled";
2047                 };
2048
2049                 usb3_0: usb@32f10100 {
2050                         compatible = "fsl,imx8mp-dwc3";
2051                         reg = <0x32f10100 0x8>,
2052                               <0x381f0000 0x20>;
2053                         clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
2054                                  <&clk IMX8MP_CLK_USB_SUSP>;
2055                         clock-names = "hsio", "suspend";
2056                         interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2057                         power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
2058                         #address-cells = <1>;
2059                         #size-cells = <1>;
2060                         dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2061                         ranges;
2062                         status = "disabled";
2063
2064                         usb_dwc3_0: usb@38100000 {
2065                                 compatible = "snps,dwc3";
2066                                 reg = <0x38100000 0x10000>;
2067                                 clocks = <&clk IMX8MP_CLK_USB_ROOT>,
2068                                          <&clk IMX8MP_CLK_USB_CORE_REF>,
2069                                          <&clk IMX8MP_CLK_USB_SUSP>;
2070                                 clock-names = "bus_early", "ref", "suspend";
2071                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
2072                                 phys = <&usb3_phy0>, <&usb3_phy0>;
2073                                 phy-names = "usb2-phy", "usb3-phy";
2074                                 snps,gfladj-refclk-lpm-sel-quirk;
2075                         };
2076
2077                 };
2078
2079                 usb3_phy1: usb-phy@382f0040 {
2080                         compatible = "fsl,imx8mp-usb-phy";
2081                         reg = <0x382f0040 0x40>;
2082                         clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
2083                         clock-names = "phy";
2084                         assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
2085                         assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2086                         power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
2087                         #phy-cells = <0>;
2088                         status = "disabled";
2089                 };
2090
2091                 usb3_1: usb@32f10108 {
2092                         compatible = "fsl,imx8mp-dwc3";
2093                         reg = <0x32f10108 0x8>,
2094                               <0x382f0000 0x20>;
2095                         clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
2096                                  <&clk IMX8MP_CLK_USB_SUSP>;
2097                         clock-names = "hsio", "suspend";
2098                         interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
2099                         power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
2100                         #address-cells = <1>;
2101                         #size-cells = <1>;
2102                         dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2103                         ranges;
2104                         status = "disabled";
2105
2106                         usb_dwc3_1: usb@38200000 {
2107                                 compatible = "snps,dwc3";
2108                                 reg = <0x38200000 0x10000>;
2109                                 clocks = <&clk IMX8MP_CLK_USB_ROOT>,
2110                                          <&clk IMX8MP_CLK_USB_CORE_REF>,
2111                                          <&clk IMX8MP_CLK_USB_SUSP>;
2112                                 clock-names = "bus_early", "ref", "suspend";
2113                                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
2114                                 phys = <&usb3_phy1>, <&usb3_phy1>;
2115                                 phy-names = "usb2-phy", "usb3-phy";
2116                                 snps,gfladj-refclk-lpm-sel-quirk;
2117                         };
2118                 };
2119
2120                 dsp: dsp@3b6e8000 {
2121                         compatible = "fsl,imx8mp-dsp";
2122                         reg = <0x3b6e8000 0x88000>;
2123                         mbox-names = "txdb0", "txdb1",
2124                                 "rxdb0", "rxdb1";
2125                         mboxes = <&mu2 2 0>, <&mu2 2 1>,
2126                                 <&mu2 3 0>, <&mu2 3 1>;
2127                         memory-region = <&dsp_reserved>;
2128                         status = "disabled";
2129                 };
2130         };
2131 };