1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx8mp-pinfunc.h"
15 interrupt-parent = <&gic>;
41 compatible = "arm,cortex-a53";
43 clock-latency = <61036>;
44 clocks = <&clk IMX8MP_CLK_ARM>;
45 enable-method = "psci";
46 next-level-cache = <&A53_L2>;
52 compatible = "arm,cortex-a53";
54 clock-latency = <61036>;
55 clocks = <&clk IMX8MP_CLK_ARM>;
56 enable-method = "psci";
57 next-level-cache = <&A53_L2>;
63 compatible = "arm,cortex-a53";
65 clock-latency = <61036>;
66 clocks = <&clk IMX8MP_CLK_ARM>;
67 enable-method = "psci";
68 next-level-cache = <&A53_L2>;
74 compatible = "arm,cortex-a53";
76 clock-latency = <61036>;
77 clocks = <&clk IMX8MP_CLK_ARM>;
78 enable-method = "psci";
79 next-level-cache = <&A53_L2>;
88 osc_32k: clock-osc-32k {
89 compatible = "fixed-clock";
91 clock-frequency = <32768>;
92 clock-output-names = "osc_32k";
95 osc_24m: clock-osc-24m {
96 compatible = "fixed-clock";
98 clock-frequency = <24000000>;
99 clock-output-names = "osc_24m";
102 clk_ext1: clock-ext1 {
103 compatible = "fixed-clock";
105 clock-frequency = <133000000>;
106 clock-output-names = "clk_ext1";
109 clk_ext2: clock-ext2 {
110 compatible = "fixed-clock";
112 clock-frequency = <133000000>;
113 clock-output-names = "clk_ext2";
116 clk_ext3: clock-ext3 {
117 compatible = "fixed-clock";
119 clock-frequency = <133000000>;
120 clock-output-names = "clk_ext3";
123 clk_ext4: clock-ext4 {
124 compatible = "fixed-clock";
126 clock-frequency= <133000000>;
127 clock-output-names = "clk_ext4";
131 compatible = "arm,psci-1.0";
137 polling-delay-passive = <250>;
138 polling-delay = <2000>;
139 thermal-sensors = <&tmu 0>;
142 temperature = <85000>;
148 temperature = <95000>;
156 trip = <&cpu_alert0>;
158 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
159 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
160 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
161 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
167 polling-delay-passive = <250>;
168 polling-delay = <2000>;
169 thermal-sensors = <&tmu 1>;
172 temperature = <85000>;
178 temperature = <95000>;
186 trip = <&soc_alert0>;
188 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
189 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
190 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
191 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
198 compatible = "arm,armv8-timer";
199 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
200 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
201 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
202 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
203 clock-frequency = <8000000>;
204 arm,no-tick-in-suspend;
208 compatible = "simple-bus";
209 #address-cells = <1>;
211 ranges = <0x0 0x0 0x0 0x3e000000>;
213 aips1: bus@30000000 {
214 compatible = "fsl,aips-bus", "simple-bus";
215 reg = <0x301f0000 0x10000>;
216 #address-cells = <1>;
220 gpio1: gpio@30200000 {
221 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
222 reg = <0x30200000 0x10000>;
223 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
225 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
228 interrupt-controller;
229 #interrupt-cells = <2>;
230 gpio-ranges = <&iomuxc 0 5 30>;
233 gpio2: gpio@30210000 {
234 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
235 reg = <0x30210000 0x10000>;
236 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
241 interrupt-controller;
242 #interrupt-cells = <2>;
243 gpio-ranges = <&iomuxc 0 35 21>;
246 gpio3: gpio@30220000 {
247 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
248 reg = <0x30220000 0x10000>;
249 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
251 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
254 interrupt-controller;
255 #interrupt-cells = <2>;
256 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 0 144 4>;
259 gpio4: gpio@30230000 {
260 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
261 reg = <0x30230000 0x10000>;
262 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
267 interrupt-controller;
268 #interrupt-cells = <2>;
269 gpio-ranges = <&iomuxc 0 82 32>;
272 gpio5: gpio@30240000 {
273 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
274 reg = <0x30240000 0x10000>;
275 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
280 interrupt-controller;
281 #interrupt-cells = <2>;
282 gpio-ranges = <&iomuxc 0 114 30>;
286 compatible = "fsl,imx8mp-tmu";
287 reg = <0x30260000 0x10000>;
288 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
289 #thermal-sensor-cells = <1>;
292 wdog1: watchdog@30280000 {
293 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
294 reg = <0x30280000 0x10000>;
295 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
300 iomuxc: pinctrl@30330000 {
301 compatible = "fsl,imx8mp-iomuxc";
302 reg = <0x30330000 0x10000>;
305 gpr: iomuxc-gpr@30340000 {
306 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
307 reg = <0x30340000 0x10000>;
310 ocotp: ocotp-ctrl@30350000 {
311 compatible = "fsl,imx8mp-ocotp", "syscon";
312 reg = <0x30350000 0x10000>;
313 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
314 /* For nvmem subnodes */
315 #address-cells = <1>;
318 cpu_speed_grade: speed-grade@10 {
323 anatop: anatop@30360000 {
324 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
326 reg = <0x30360000 0x10000>;
329 snvs: snvs@30370000 {
330 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
331 reg = <0x30370000 0x10000>;
333 snvs_rtc: snvs-rtc-lp {
334 compatible = "fsl,sec-v4.0-mon-rtc-lp";
337 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
339 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
340 clock-names = "snvs-rtc";
343 snvs_pwrkey: snvs-powerkey {
344 compatible = "fsl,sec-v4.0-pwrkey";
346 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
348 clock-names = "snvs-pwrkey";
349 linux,keycode = <KEY_POWER>;
355 clk: clock-controller@30380000 {
356 compatible = "fsl,imx8mp-ccm";
357 reg = <0x30380000 0x10000>;
359 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
360 <&clk_ext3>, <&clk_ext4>;
361 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
362 "clk_ext3", "clk_ext4";
363 assigned-clocks = <&clk IMX8MP_CLK_NOC>,
364 <&clk IMX8MP_CLK_NOC_IO>,
365 <&clk IMX8MP_CLK_GIC>,
366 <&clk IMX8MP_CLK_AUDIO_AHB>,
367 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
368 <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>,
369 <&clk IMX8MP_AUDIO_PLL1>,
370 <&clk IMX8MP_AUDIO_PLL2>;
371 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
372 <&clk IMX8MP_SYS_PLL1_800M>,
373 <&clk IMX8MP_SYS_PLL2_500M>,
374 <&clk IMX8MP_SYS_PLL1_800M>,
375 <&clk IMX8MP_SYS_PLL1_800M>;
376 assigned-clock-rates = <1000000000>,
386 src: reset-controller@30390000 {
387 compatible = "fsl,imx8mp-src", "syscon";
388 reg = <0x30390000 0x10000>;
393 aips2: bus@30400000 {
394 compatible = "fsl,aips-bus", "simple-bus";
395 reg = <0x305f0000 0x400000>;
396 #address-cells = <1>;
401 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
402 reg = <0x30660000 0x10000>;
403 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
405 <&clk IMX8MP_CLK_PWM1_ROOT>;
406 clock-names = "ipg", "per";
412 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
413 reg = <0x30670000 0x10000>;
414 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
416 <&clk IMX8MP_CLK_PWM2_ROOT>;
417 clock-names = "ipg", "per";
423 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
424 reg = <0x30680000 0x10000>;
425 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
427 <&clk IMX8MP_CLK_PWM3_ROOT>;
428 clock-names = "ipg", "per";
434 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
435 reg = <0x30690000 0x10000>;
436 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
438 <&clk IMX8MP_CLK_PWM4_ROOT>;
439 clock-names = "ipg", "per";
444 system_counter: timer@306a0000 {
445 compatible = "nxp,sysctr-timer";
446 reg = <0x306a0000 0x20000>;
447 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
453 aips3: bus@30800000 {
454 compatible = "fsl,aips-bus", "simple-bus";
455 reg = <0x309f0000 0x400000>;
456 #address-cells = <1>;
460 ecspi1: spi@30820000 {
461 #address-cells = <1>;
463 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
464 reg = <0x30820000 0x10000>;
465 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
467 <&clk IMX8MP_CLK_ECSPI1_ROOT>;
468 clock-names = "ipg", "per";
469 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
470 dma-names = "rx", "tx";
474 ecspi2: spi@30830000 {
475 #address-cells = <1>;
477 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
478 reg = <0x30830000 0x10000>;
479 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
480 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
481 <&clk IMX8MP_CLK_ECSPI2_ROOT>;
482 clock-names = "ipg", "per";
483 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
484 dma-names = "rx", "tx";
488 ecspi3: spi@30840000 {
489 #address-cells = <1>;
491 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
492 reg = <0x30840000 0x10000>;
493 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
495 <&clk IMX8MP_CLK_ECSPI3_ROOT>;
496 clock-names = "ipg", "per";
497 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
498 dma-names = "rx", "tx";
502 uart1: serial@30860000 {
503 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
504 reg = <0x30860000 0x10000>;
505 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
507 <&clk IMX8MP_CLK_UART1_ROOT>;
508 clock-names = "ipg", "per";
509 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
510 dma-names = "rx", "tx";
514 uart3: serial@30880000 {
515 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
516 reg = <0x30880000 0x10000>;
517 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
519 <&clk IMX8MP_CLK_UART3_ROOT>;
520 clock-names = "ipg", "per";
521 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
522 dma-names = "rx", "tx";
526 uart2: serial@30890000 {
527 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
528 reg = <0x30890000 0x10000>;
529 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
531 <&clk IMX8MP_CLK_UART2_ROOT>;
532 clock-names = "ipg", "per";
536 crypto: crypto@30900000 {
537 compatible = "fsl,sec-v4.0";
538 #address-cells = <1>;
540 reg = <0x30900000 0x40000>;
541 ranges = <0 0x30900000 0x40000>;
542 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&clk IMX8MP_CLK_AHB>,
544 <&clk IMX8MP_CLK_IPG_ROOT>;
545 clock-names = "aclk", "ipg";
548 compatible = "fsl,sec-v4.0-job-ring";
549 reg = <0x1000 0x1000>;
550 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
554 compatible = "fsl,sec-v4.0-job-ring";
555 reg = <0x2000 0x1000>;
556 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
560 compatible = "fsl,sec-v4.0-job-ring";
561 reg = <0x3000 0x1000>;
562 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
567 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
568 #address-cells = <1>;
570 reg = <0x30a20000 0x10000>;
571 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
572 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>;
577 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
578 #address-cells = <1>;
580 reg = <0x30a30000 0x10000>;
581 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
582 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>;
587 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
588 #address-cells = <1>;
590 reg = <0x30a40000 0x10000>;
591 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
592 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
597 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
598 #address-cells = <1>;
600 reg = <0x30a50000 0x10000>;
601 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>;
606 uart4: serial@30a60000 {
607 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
608 reg = <0x30a60000 0x10000>;
609 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
610 clocks = <&clk IMX8MP_CLK_UART4_ROOT>,
611 <&clk IMX8MP_CLK_UART4_ROOT>;
612 clock-names = "ipg", "per";
613 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
614 dma-names = "rx", "tx";
619 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
620 #address-cells = <1>;
622 reg = <0x30ad0000 0x10000>;
623 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
624 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>;
629 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
630 #address-cells = <1>;
632 reg = <0x30ae0000 0x10000>;
633 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>;
638 usdhc1: mmc@30b40000 {
639 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
640 reg = <0x30b40000 0x10000>;
641 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
642 clocks = <&clk IMX8MP_CLK_DUMMY>,
643 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
644 <&clk IMX8MP_CLK_USDHC1_ROOT>;
645 clock-names = "ipg", "ahb", "per";
646 fsl,tuning-start-tap = <20>;
647 fsl,tuning-step= <2>;
652 usdhc2: mmc@30b50000 {
653 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
654 reg = <0x30b50000 0x10000>;
655 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&clk IMX8MP_CLK_DUMMY>,
657 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
658 <&clk IMX8MP_CLK_USDHC2_ROOT>;
659 clock-names = "ipg", "ahb", "per";
660 fsl,tuning-start-tap = <20>;
661 fsl,tuning-step= <2>;
666 usdhc3: mmc@30b60000 {
667 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
668 reg = <0x30b60000 0x10000>;
669 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&clk IMX8MP_CLK_DUMMY>,
671 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
672 <&clk IMX8MP_CLK_USDHC3_ROOT>;
673 clock-names = "ipg", "ahb", "per";
674 fsl,tuning-start-tap = <20>;
675 fsl,tuning-step= <2>;
680 sdma1: dma-controller@30bd0000 {
681 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
682 reg = <0x30bd0000 0x10000>;
683 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
684 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
685 <&clk IMX8MP_CLK_SDMA1_ROOT>;
686 clock-names = "ipg", "ahb";
688 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
691 fec: ethernet@30be0000 {
692 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
693 reg = <0x30be0000 0x10000>;
694 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
695 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
696 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
697 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
698 <&clk IMX8MP_CLK_SIM_ENET_ROOT>,
699 <&clk IMX8MP_CLK_ENET_TIMER>,
700 <&clk IMX8MP_CLK_ENET_REF>,
701 <&clk IMX8MP_CLK_ENET_PHY_REF>;
702 clock-names = "ipg", "ahb", "ptp",
703 "enet_clk_ref", "enet_out";
704 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
705 <&clk IMX8MP_CLK_ENET_TIMER>,
706 <&clk IMX8MP_CLK_ENET_REF>,
707 <&clk IMX8MP_CLK_ENET_TIMER>;
708 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
709 <&clk IMX8MP_SYS_PLL2_100M>,
710 <&clk IMX8MP_SYS_PLL2_125M>;
711 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
712 fsl,num-tx-queues = <3>;
713 fsl,num-rx-queues = <3>;
718 gic: interrupt-controller@38800000 {
719 compatible = "arm,gic-v3";
720 reg = <0x38800000 0x10000>,
721 <0x38880000 0xc0000>;
722 #interrupt-cells = <3>;
723 interrupt-controller;
724 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
725 interrupt-parent = <&gic>;