1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2021 Gateworks Corporation
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/net/ti-dp83867.h>
13 #include "imx8mn.dtsi"
16 model = "Gateworks Venice GW7902 i.MX8MN board";
17 compatible = "gw,imx8mn-gw7902", "fsl,imx8mn";
28 device_type = "memory";
29 reg = <0x0 0x40000000 0 0x80000000>;
33 compatible = "fixed-clock";
35 clock-frequency = <20000000>;
36 clock-output-names = "can20m";
40 compatible = "gpio-keys";
44 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
51 interrupt-parent = <&gsc>;
58 interrupt-parent = <&gsc>;
65 interrupt-parent = <&gsc>;
72 interrupt-parent = <&gsc>;
77 label = "switch_hold";
79 interrupt-parent = <&gsc>;
85 compatible = "gpio-leds";
86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_gpio_leds>;
90 function = LED_FUNCTION_STATUS;
91 color = <LED_COLOR_ID_GREEN>;
93 gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
94 default-state = "off";
98 function = LED_FUNCTION_STATUS;
99 color = <LED_COLOR_ID_GREEN>;
101 gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
102 default-state = "off";
106 function = LED_FUNCTION_STATUS;
107 color = <LED_COLOR_ID_GREEN>;
109 gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
110 default-state = "off";
114 function = LED_FUNCTION_STATUS;
115 color = <LED_COLOR_ID_GREEN>;
117 gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
118 default-state = "off";
122 function = LED_FUNCTION_STATUS;
123 color = <LED_COLOR_ID_GREEN>;
125 gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
126 default-state = "off";
131 compatible = "pps-gpio";
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_pps>;
134 gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
138 reg_3p3v: regulator-3p3v {
139 compatible = "regulator-fixed";
140 regulator-name = "3P3V";
141 regulator-min-microvolt = <3300000>;
142 regulator-max-microvolt = <3300000>;
146 reg_usb1_vbus: regulator-usb1 {
147 compatible = "regulator-fixed";
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_reg_usb1>;
150 regulator-name = "usb_usb1_vbus";
151 gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
153 regulator-min-microvolt = <5000000>;
154 regulator-max-microvolt = <5000000>;
157 reg_wifi: regulator-wifi {
158 compatible = "regulator-fixed";
159 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_reg_wl>;
161 regulator-name = "wifi";
162 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
164 startup-delay-us = <100>;
165 regulator-min-microvolt = <3300000>;
166 regulator-max-microvolt = <3300000>;
171 cpu-supply = <&buck2>;
175 cpu-supply = <&buck2>;
179 cpu-supply = <&buck2>;
183 cpu-supply = <&buck2>;
187 operating-points-v2 = <&ddrc_opp_table>;
189 ddrc_opp_table: opp-table {
190 compatible = "operating-points-v2";
193 opp-hz = /bits/ 64 <25000000>;
197 opp-hz = /bits/ 64 <100000000>;
201 opp-hz = /bits/ 64 <750000000>;
207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_spi1>;
209 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
213 compatible = "microchip,mcp2515";
216 interrupt-parent = <&gpio2>;
217 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
218 spi-max-frequency = <10000000>;
226 /* off-board header */
228 pinctrl-names = "default";
229 pinctrl-0 = <&pinctrl_spi2>;
230 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
235 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_fec1>;
237 phy-mode = "rgmii-id";
238 phy-handle = <ðphy0>;
239 local-mac-address = [00 00 00 00 00 00];
243 #address-cells = <1>;
246 ethphy0: ethernet-phy@0 {
247 compatible = "ethernet-phy-ieee802.3-c22";
249 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
250 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
251 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
252 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
258 gpio-line-names = "", "", "", "", "", "", "", "",
259 "", "", "", "", "", "m2_reset", "", "m2_wdis#",
260 "", "", "", "", "", "", "", "",
261 "", "", "", "", "", "", "", "";
265 gpio-line-names = "", "", "", "", "", "", "", "",
266 "uart2_en#", "", "", "", "", "", "", "",
267 "", "", "", "", "", "", "", "",
268 "", "", "", "", "", "", "", "";
272 gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#",
273 "", "", "", "", "", "", "", "",
274 "", "", "", "", "", "", "", "",
275 "", "", "", "", "", "", "", "";
279 gpio-line-names = "", "", "", "", "", "", "", "",
280 "", "", "", "", "", "", "", "",
281 "", "", "", "", "", "app_gpio1", "", "uart1_rs485",
282 "", "uart1_term", "uart1_half", "app_gpio2",
283 "mipi_gpio1", "", "", "";
287 gpio-line-names = "", "", "", "mipi_gpio4",
288 "mipi_gpio3", "mipi_gpio2", "", "",
289 "", "", "", "", "", "", "", "",
290 "", "", "", "", "", "", "", "",
291 "", "", "", "", "", "", "", "";
299 clock-frequency = <100000>;
300 pinctrl-names = "default", "gpio";
301 pinctrl-0 = <&pinctrl_i2c1>;
302 pinctrl-1 = <&pinctrl_i2c1_gpio>;
303 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
304 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
308 compatible = "gw,gsc";
310 pinctrl-0 = <&pinctrl_gsc>;
311 interrupt-parent = <&gpio2>;
312 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
313 interrupt-controller;
314 #interrupt-cells = <1>;
317 compatible = "gw,gsc-adc";
318 #address-cells = <1>;
337 gw,voltage-divider-ohms = <22100 1000>;
338 gw,voltage-offset-microvolt = <700000>;
345 gw,voltage-divider-ohms = <10000 10000>;
352 gw,voltage-divider-ohms = <10000 10000>;
395 gw,voltage-divider-ohms = <10000 10000>;
402 gw,voltage-divider-ohms = <10000 10000>;
409 gw,voltage-divider-ohms = <10000 10000>;
415 compatible = "nxp,pca9555";
419 interrupt-parent = <&gsc>;
424 compatible = "rohm,bd71847";
426 pinctrl-names = "default";
427 pinctrl-0 = <&pinctrl_pmic>;
428 interrupt-parent = <&gpio3>;
429 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
430 rohm,reset-snvs-powered;
432 clocks = <&osc_32k 0>;
433 clock-output-names = "clk-32k-out";
436 /* vdd_soc: 0.805-0.900V (typ=0.8V) */
438 regulator-name = "buck1";
439 regulator-min-microvolt = <700000>;
440 regulator-max-microvolt = <1300000>;
443 regulator-ramp-delay = <1250>;
446 /* vdd_arm: 0.805-1.0V (typ=0.9V) */
448 regulator-name = "buck2";
449 regulator-min-microvolt = <700000>;
450 regulator-max-microvolt = <1300000>;
453 regulator-ramp-delay = <1250>;
454 rohm,dvs-run-voltage = <1000000>;
455 rohm,dvs-idle-voltage = <900000>;
458 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
460 regulator-name = "buck3";
461 regulator-min-microvolt = <700000>;
462 regulator-max-microvolt = <1350000>;
469 regulator-name = "buck4";
470 regulator-min-microvolt = <3000000>;
471 regulator-max-microvolt = <3300000>;
478 regulator-name = "buck5";
479 regulator-min-microvolt = <1605000>;
480 regulator-max-microvolt = <1995000>;
487 regulator-name = "buck6";
488 regulator-min-microvolt = <800000>;
489 regulator-max-microvolt = <1400000>;
496 regulator-name = "ldo1";
497 regulator-min-microvolt = <1600000>;
498 regulator-max-microvolt = <1900000>;
505 regulator-name = "ldo2";
506 regulator-min-microvolt = <800000>;
507 regulator-max-microvolt = <900000>;
514 regulator-name = "ldo3";
515 regulator-min-microvolt = <1800000>;
516 regulator-max-microvolt = <3300000>;
522 regulator-name = "ldo4";
523 regulator-min-microvolt = <900000>;
524 regulator-max-microvolt = <1800000>;
530 regulator-name = "ldo6";
531 regulator-min-microvolt = <900000>;
532 regulator-max-microvolt = <1800000>;
540 compatible = "atmel,24c02";
546 compatible = "atmel,24c02";
552 compatible = "atmel,24c02";
558 compatible = "atmel,24c02";
564 compatible = "dallas,ds1672";
570 clock-frequency = <400000>;
571 pinctrl-names = "default", "gpio";
572 pinctrl-0 = <&pinctrl_i2c2>;
573 pinctrl-1 = <&pinctrl_i2c2_gpio>;
574 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
575 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
579 compatible = "st,lis2de12";
580 pinctrl-names = "default";
581 pinctrl-0 = <&pinctrl_accel>;
583 st,drdy-int-pin = <1>;
584 interrupt-parent = <&gpio1>;
585 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
586 interrupt-names = "INT1";
590 /* off-board header */
592 clock-frequency = <400000>;
593 pinctrl-names = "default", "gpio";
594 pinctrl-0 = <&pinctrl_i2c3>;
595 pinctrl-1 = <&pinctrl_i2c3_gpio>;
596 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
597 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
601 /* off-board header */
603 clock-frequency = <400000>;
604 pinctrl-names = "default", "gpio";
605 pinctrl-0 = <&pinctrl_i2c4>;
606 pinctrl-1 = <&pinctrl_i2c4_gpio>;
607 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
608 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
616 /* off-board header */
618 pinctrl-names = "default";
619 pinctrl-0 = <&pinctrl_sai3>;
620 assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
621 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
622 assigned-clock-rates = <24576000>;
626 /* RS232/RS485/RS422 selectable */
628 pinctrl-names = "default";
629 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
635 pinctrl-names = "default";
636 pinctrl-0 = <&pinctrl_uart2>;
642 pinctrl-names = "default";
643 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
644 rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
645 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
650 compatible = "brcm,bcm4330-bt";
651 shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
655 /* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */
657 pinctrl-names = "default";
658 pinctrl-0 = <&pinctrl_uart4>;
664 vbus-supply = <®_usb1_vbus>;
665 disable-over-current;
671 pinctrl-names = "default";
672 pinctrl-0 = <&pinctrl_usdhc2>;
675 vmmc-supply = <®_wifi>;
681 pinctrl-names = "default", "state_100mhz", "state_200mhz";
682 pinctrl-0 = <&pinctrl_usdhc3>;
683 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
684 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
691 pinctrl-names = "default";
692 pinctrl-0 = <&pinctrl_wdog>;
693 fsl,ext-reset-output;
698 pinctrl-names = "default";
699 pinctrl-0 = <&pinctrl_hog>;
701 pinctrl_hog: hoggrp {
703 MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
704 MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */
705 MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
706 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
707 MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */
708 MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */
709 MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */
710 MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */
711 MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */
712 MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */
713 MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */
717 pinctrl_accel: accelgrp {
719 MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159
723 pinctrl_fec1: fec1grp {
725 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
726 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
727 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
728 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
729 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
730 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
731 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
732 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
733 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
734 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
735 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
736 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
737 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
738 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
739 MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */
740 MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */
741 MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141
742 MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141
746 pinctrl_gsc: gscgrp {
748 MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40
752 pinctrl_i2c1: i2c1grp {
754 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
755 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
759 pinctrl_i2c1_gpio: i2c1gpiogrp {
761 MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
762 MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
766 pinctrl_i2c2: i2c2grp {
768 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
769 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
773 pinctrl_i2c2_gpio: i2c2gpiogrp {
775 MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
776 MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
780 pinctrl_i2c3: i2c3grp {
782 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
783 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
787 pinctrl_i2c3_gpio: i2c3gpiogrp {
789 MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
790 MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
794 pinctrl_i2c4: i2c4grp {
796 MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
797 MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
801 pinctrl_i2c4_gpio: i2c4gpiogrp {
803 MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3
804 MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3
808 pinctrl_gpio_leds: gpioledgrp {
810 MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19
811 MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19
812 MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19
813 MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19
814 MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19
818 pinctrl_pmic: pmicgrp {
820 MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
824 pinctrl_pps: ppsgrp {
826 MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */
830 pinctrl_reg_wl: regwlgrp {
832 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */
836 pinctrl_reg_usb1: regusb1grp {
838 MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41
842 pinctrl_sai3: sai3grp {
844 MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
845 MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
846 MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
847 MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
848 MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
852 pinctrl_spi1: spi1grp {
854 MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
855 MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
856 MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
857 MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40
858 MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */
862 pinctrl_spi2: spi2grp {
864 MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
865 MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
866 MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
867 MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */
871 pinctrl_uart1: uart1grp {
873 MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
874 MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
878 pinctrl_uart1_gpio: uart1gpiogrp {
880 MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */
881 MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */
882 MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */
886 pinctrl_uart2: uart2grp {
888 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
889 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
893 pinctrl_uart3_gpio: uart3_gpiogrp {
895 MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */
899 pinctrl_uart3: uart3grp {
901 MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
902 MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
903 MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */
904 MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */
908 pinctrl_uart4: uart4grp {
910 MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
911 MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
912 MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */
916 pinctrl_usdhc2: usdhc2grp {
918 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
919 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
920 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
921 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
922 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
923 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
927 pinctrl_usdhc3: usdhc3grp {
929 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
930 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
931 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
932 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
933 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
934 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
935 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
936 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
937 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
938 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
939 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
943 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
945 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
946 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
947 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
948 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
949 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
950 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
951 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
952 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
953 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
954 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
955 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
959 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
961 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
962 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
963 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
964 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
965 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
966 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
967 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
968 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
969 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
970 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
971 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
975 pinctrl_wdog: wdoggrp {
977 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6