arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <dt-bindings/usb/pd.h>
   7 #include "imx8mn.dtsi"
   8
   9 / {
  10         chosen {
  11                 stdout-path = &uart2;
  12         };
  13
  14         gpio-leds {
  15                 compatible = "gpio-leds";
  16                 pinctrl-names = "default";
  17                 pinctrl-0 = <&pinctrl_gpio_led>;
  18
  19                 status {
  20                         label = "yellow:status";
  21                         gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
  22                         default-state = "on";
  23                 };
  24         };
  25
  26         memory@40000000 {
  27                 device_type = "memory";
  28                 reg = <0x0 0x40000000 0 0x80000000>;
  29         };
  30
  31         reg_usdhc2_vmmc: regulator-usdhc2 {
  32                 compatible = "regulator-fixed";
  33                 pinctrl-names = "default";
  34                 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
  35                 regulator-name = "VSD_3V3";
  36                 regulator-min-microvolt = <3300000>;
  37                 regulator-max-microvolt = <3300000>;
  38                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  39                 enable-active-high;
  40         };
  41 };
  42
  43 &fec1 {
  44         pinctrl-names = "default";
  45         pinctrl-0 = <&pinctrl_fec1>;
  46         phy-mode = "rgmii-id";
  47         phy-handle = <&ethphy0>;
  48         fsl,magic-packet;
  49         status = "okay";
  50
  51         mdio {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54
  55                 ethphy0: ethernet-phy@0 {
  56                         compatible = "ethernet-phy-ieee802.3-c22";
  57                         reg = <0>;
  58                 };
  59         };
  60 };
  61
  62 &i2c1 {
  63         clock-frequency = <400000>;
  64         pinctrl-names = "default";
  65         pinctrl-0 = <&pinctrl_i2c1>;
  66         status = "okay";
  67 };
  68
  69 &i2c2 {
  70         clock-frequency = <400000>;
  71         pinctrl-names = "default";
  72         pinctrl-0 = <&pinctrl_i2c2>;
  73         status = "okay";
  74
  75         ptn5110: tcpc@50 {
  76                 compatible = "nxp,ptn5110";
  77                 pinctrl-names = "default";
  78                 pinctrl-0 = <&pinctrl_typec1>;
  79                 reg = <0x50>;
  80                 interrupt-parent = <&gpio2>;
  81                 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
  82                 status = "okay";
  83
  84                 port {
  85                         typec1_dr_sw: endpoint {
  86                                 remote-endpoint = <&usb1_drd_sw>;
  87                         };
  88                 };
  89
  90                 typec1_con: connector {
  91                         compatible = "usb-c-connector";
  92                         label = "USB-C";
  93                         power-role = "dual";
  94                         data-role = "dual";
  95                         try-power-role = "sink";
  96                         source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
  97                         sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
  98                                      PDO_VAR(5000, 20000, 3000)>;
  99                         op-sink-microwatt = <15000000>;
 100                         self-powered;
 101                 };
 102         };
 103 };
 104
 105 &snvs_pwrkey {
 106         status = "okay";
 107 };
 108
 109 &uart2 { /* console */
 110         pinctrl-names = "default";
 111         pinctrl-0 = <&pinctrl_uart2>;
 112         status = "okay";
 113 };
 114
 115 &usbotg1 {
 116         dr_mode = "otg";
 117         hnp-disable;
 118         srp-disable;
 119         adp-disable;
 120         usb-role-switch;
 121         status = "okay";
 122
 123         port {
 124                 usb1_drd_sw: endpoint {
 125                         remote-endpoint = <&typec1_dr_sw>;
 126                 };
 127         };
 128 };
 129
 130 &usdhc2 {
 131         assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
 132         assigned-clock-rates = <200000000>;
 133         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 134         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 135         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 136         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 137         cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 138         bus-width = <4>;
 139         vmmc-supply = <&reg_usdhc2_vmmc>;
 140         status = "okay";
 141 };
 142
 143 &usdhc3 {
 144         assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
 145         assigned-clock-rates = <400000000>;
 146         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 147         pinctrl-0 = <&pinctrl_usdhc3>;
 148         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 149         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 150         bus-width = <8>;
 151         non-removable;
 152         status = "okay";
 153 };
 154
 155 &wdog1 {
 156         pinctrl-names = "default";
 157         pinctrl-0 = <&pinctrl_wdog>;
 158         fsl,ext-reset-output;
 159         status = "okay";
 160 };
 161
 162 &iomuxc {
 163         pinctrl-names = "default";
 164
 165         pinctrl_fec1: fec1grp {
 166                 fsl,pins = <
 167                         MX8MN_IOMUXC_ENET_MDC_ENET1_MDC         0x3
 168                         MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO       0x3
 169                         MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3   0x1f
 170                         MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2   0x1f
 171                         MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1   0x1f
 172                         MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0   0x1f
 173                         MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3   0x91
 174                         MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2   0x91
 175                         MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1   0x91
 176                         MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0   0x91
 177                         MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC   0x1f
 178                         MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC   0x91
 179                         MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 180                         MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 181                         MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22        0x19
 182                 >;
 183         };
 184
 185         pinctrl_gpio_led: gpioledgrp {
 186                 fsl,pins = <
 187                         MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16    0x19
 188                 >;
 189         };
 190
 191         pinctrl_i2c1: i2c1grp {
 192                 fsl,pins = <
 193                         MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL          0x400001c3
 194                         MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA          0x400001c3
 195                 >;
 196         };
 197
 198         pinctrl_i2c2: i2c2grp {
 199                 fsl,pins = <
 200                         MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL          0x400001c3
 201                         MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA          0x400001c3
 202                 >;
 203         };
 204
 205         pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
 206                 fsl,pins = <
 207                         MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19     0x41
 208                 >;
 209         };
 210
 211         pinctrl_typec1: typec1grp {
 212                 fsl,pins = <
 213                         MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11      0x159
 214                 >;
 215         };
 216
 217         pinctrl_uart2: uart2grp {
 218                 fsl,pins = <
 219                         MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140
 220                         MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140
 221                 >;
 222         };
 223
 224         pinctrl_usdhc2_gpio: usdhc2grpgpio {
 225                 fsl,pins = <
 226                         MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15      0x1c4
 227                 >;
 228         };
 229
 230         pinctrl_usdhc2: usdhc2grp {
 231                 fsl,pins = <
 232                         MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x190
 233                         MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d0
 234                         MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d0
 235                         MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d0
 236                         MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d0
 237                         MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d0
 238                         MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 239                 >;
 240         };
 241
 242         pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
 243                 fsl,pins = <
 244                         MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x194
 245                         MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d4
 246                         MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d4
 247                         MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d4
 248                         MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d4
 249                         MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d4
 250                         MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 251                 >;
 252         };
 253
 254         pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
 255                 fsl,pins = <
 256                         MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x196
 257                         MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d6
 258                         MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d6
 259                         MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d6
 260                         MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d6
 261                         MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d6
 262                         MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 263                 >;
 264         };
 265
 266         pinctrl_usdhc3: usdhc3grp {
 267                 fsl,pins = <
 268                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x40000190
 269                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d0
 270                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d0
 271                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d0
 272                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
 273                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d0
 274                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d0
 275                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d0
 276                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d0
 277                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d0
 278                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x190
 279                 >;
 280         };
 281
 282         pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 283                 fsl,pins = <
 284                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x40000194
 285                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d4
 286                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d4
 287                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d4
 288                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d4
 289                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d4
 290                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d4
 291                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d4
 292                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d4
 293                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d4
 294                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x194
 295                 >;
 296         };
 297
 298         pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 299                 fsl,pins = <
 300                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x40000196
 301                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d6
 302                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d6
 303                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d6
 304                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d6
 305                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d6
 306                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d6
 307                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d6
 308                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d6
 309                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d6
 310                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x196
 311                 >;
 312         };
 313
 314         pinctrl_wdog: wdoggrp {
 315                 fsl,pins = <
 316                         MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B            0xc6
 317                 >;
 318         };
 319 };