arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <dt-bindings/usb/pd.h>
   7 #include "imx8mn.dtsi"
   8
   9 / {
  10         chosen {
  11                 stdout-path = &uart2;
  12         };
  13
  14         gpio-leds {
  15                 compatible = "gpio-leds";
  16                 pinctrl-names = "default";
  17                 pinctrl-0 = <&pinctrl_gpio_led>;
  18
  19                 status {
  20                         label = "yellow:status";
  21                         gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
  22                         default-state = "on";
  23                 };
  24         };
  25
  26         memory@40000000 {
  27                 device_type = "memory";
  28                 reg = <0x0 0x40000000 0 0x80000000>;
  29         };
  30
  31         reg_usdhc2_vmmc: regulator-usdhc2 {
  32                 compatible = "regulator-fixed";
  33                 pinctrl-names = "default";
  34                 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
  35                 regulator-name = "VSD_3V3";
  36                 regulator-min-microvolt = <3300000>;
  37                 regulator-max-microvolt = <3300000>;
  38                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  39                 off-on-delay-us = <12000>;
  40                 enable-active-high;
  41         };
  42
  43         ir-receiver {
  44                 compatible = "gpio-ir-receiver";
  45                 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
  46                 pinctrl-names = "default";
  47                 pinctrl-0 = <&pinctrl_ir>;
  48                 linux,autosuspend-period = <125>;
  49         };
  50
  51         audio_codec_bt_sco: audio-codec-bt-sco {
  52                 compatible = "linux,bt-sco";
  53                 #sound-dai-cells = <1>;
  54         };
  55
  56         wm8524: audio-codec {
  57                 #sound-dai-cells = <0>;
  58                 compatible = "wlf,wm8524";
  59                 pinctrl-names = "default";
  60                 pinctrl-0 = <&pinctrl_gpio_wlf>;
  61                 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
  62                 clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
  63                 clock-names = "mclk";
  64         };
  65
  66         sound-bt-sco {
  67                 compatible = "simple-audio-card";
  68                 simple-audio-card,name = "bt-sco-audio";
  69                 simple-audio-card,format = "dsp_a";
  70                 simple-audio-card,bitclock-inversion;
  71                 simple-audio-card,frame-master = <&btcpu>;
  72                 simple-audio-card,bitclock-master = <&btcpu>;
  73
  74                 btcpu: simple-audio-card,cpu {
  75                         sound-dai = <&sai2>;
  76                         dai-tdm-slot-num = <2>;
  77                         dai-tdm-slot-width = <16>;
  78                 };
  79
  80                 simple-audio-card,codec {
  81                         sound-dai = <&audio_codec_bt_sco 1>;
  82                 };
  83         };
  84
  85         sound-wm8524 {
  86                 compatible = "fsl,imx-audio-wm8524";
  87                 model = "wm8524-audio";
  88                 audio-cpu = <&sai3>;
  89                 audio-codec = <&wm8524>;
  90                 audio-asrc = <&easrc>;
  91                 audio-routing =
  92                         "Line Out Jack", "LINEVOUTL",
  93                         "Line Out Jack", "LINEVOUTR";
  94         };
  95
  96         sound-spdif {
  97                 compatible = "fsl,imx-audio-spdif";
  98                 model = "imx-spdif";
  99                 spdif-controller = <&spdif1>;
 100                 spdif-out;
 101                 spdif-in;
 102         };
 103 };
 104
 105 &easrc {
 106         fsl,asrc-rate = <48000>;
 107         status = "okay";
 108 };
 109
 110 &fec1 {
 111         pinctrl-names = "default";
 112         pinctrl-0 = <&pinctrl_fec1>;
 113         phy-mode = "rgmii-id";
 114         phy-handle = <&ethphy0>;
 115         fsl,magic-packet;
 116         status = "okay";
 117
 118         mdio {
 119                 #address-cells = <1>;
 120                 #size-cells = <0>;
 121
 122                 ethphy0: ethernet-phy@0 {
 123                         compatible = "ethernet-phy-ieee802.3-c22";
 124                         reg = <0>;
 125                         reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
 126                         reset-assert-us = <10000>;
 127                         qca,disable-smarteee;
 128                         vddio-supply = <&vddio>;
 129
 130                         vddio: vddio-regulator {
 131                                 regulator-min-microvolt = <1800000>;
 132                                 regulator-max-microvolt = <1800000>;
 133                         };
 134                 };
 135         };
 136 };
 137
 138 &flexspi {
 139         pinctrl-names = "default";
 140         pinctrl-0 = <&pinctrl_flexspi>;
 141         status = "okay";
 142
 143         flash0: flash@0 {
 144                 compatible = "jedec,spi-nor";
 145                 reg = <0>;
 146                 #address-cells = <1>;
 147                 #size-cells = <1>;
 148                 spi-max-frequency = <166000000>;
 149                 spi-tx-bus-width = <4>;
 150                 spi-rx-bus-width = <4>;
 151         };
 152 };
 153
 154 &i2c1 {
 155         clock-frequency = <400000>;
 156         pinctrl-names = "default";
 157         pinctrl-0 = <&pinctrl_i2c1>;
 158         status = "okay";
 159 };
 160
 161 &i2c2 {
 162         clock-frequency = <400000>;
 163         pinctrl-names = "default", "gpio";
 164         pinctrl-0 = <&pinctrl_i2c2>;
 165         pinctrl-1 = <&pinctrl_i2c2_gpio>;
 166         scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
 167         sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
 168         status = "okay";
 169
 170         ptn5110: tcpc@50 {
 171                 compatible = "nxp,ptn5110";
 172                 pinctrl-names = "default";
 173                 pinctrl-0 = <&pinctrl_typec1>;
 174                 reg = <0x50>;
 175                 interrupt-parent = <&gpio2>;
 176                 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
 177                 status = "okay";
 178
 179                 port {
 180                         typec1_dr_sw: endpoint {
 181                                 remote-endpoint = <&usb1_drd_sw>;
 182                         };
 183                 };
 184
 185                 typec1_con: connector {
 186                         compatible = "usb-c-connector";
 187                         label = "USB-C";
 188                         power-role = "dual";
 189                         data-role = "dual";
 190                         try-power-role = "sink";
 191                         source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
 192                         sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
 193                                      PDO_VAR(5000, 20000, 3000)>;
 194                         op-sink-microwatt = <15000000>;
 195                         self-powered;
 196                 };
 197         };
 198 };
 199
 200 &i2c3 {
 201         clock-frequency = <400000>;
 202         pinctrl-names = "default", "gpio";
 203         pinctrl-0 = <&pinctrl_i2c3>;
 204         pinctrl-1 = <&pinctrl_i2c3_gpio>;
 205         scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
 206         sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
 207         status = "okay";
 208
 209         pca6416: gpio@20 {
 210                 compatible = "ti,tca6416";
 211                 reg = <0x20>;
 212                 gpio-controller;
 213                 #gpio-cells = <2>;
 214         };
 215 };
 216
 217 &sai2 {
 218         #sound-dai-cells = <0>;
 219         pinctrl-names = "default";
 220         pinctrl-0 = <&pinctrl_sai2>;
 221         assigned-clocks = <&clk IMX8MN_CLK_SAI2>;
 222         assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
 223         assigned-clock-rates = <24576000>;
 224         status = "okay";
 225 };
 226
 227 &sai3 {
 228         pinctrl-names = "default";
 229         pinctrl-0 = <&pinctrl_sai3>;
 230         assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
 231         assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
 232         assigned-clock-rates = <24576000>;
 233         fsl,sai-mclk-direction-output;
 234         status = "okay";
 235 };
 236
 237 &snvs_pwrkey {
 238         status = "okay";
 239 };
 240
 241 &spdif1 {
 242         pinctrl-names = "default";
 243         pinctrl-0 = <&pinctrl_spdif1>;
 244         assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>;
 245         assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
 246         assigned-clock-rates = <24576000>;
 247         status = "okay";
 248 };
 249
 250 &uart1 { /* BT */
 251         pinctrl-names = "default";
 252         pinctrl-0 = <&pinctrl_uart1>;
 253         assigned-clocks = <&clk IMX8MN_CLK_UART1>;
 254         assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
 255         uart-has-rtscts;
 256         status = "okay";
 257 };
 258
 259 &uart2 { /* console */
 260         pinctrl-names = "default";
 261         pinctrl-0 = <&pinctrl_uart2>;
 262         status = "okay";
 263 };
 264
 265 &uart3 {
 266         pinctrl-names = "default";
 267         pinctrl-0 = <&pinctrl_uart3>;
 268         assigned-clocks = <&clk IMX8MN_CLK_UART3>;
 269         assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
 270         uart-has-rtscts;
 271         status = "okay";
 272 };
 273
 274 &usbphynop1 {
 275         wakeup-source;
 276 };
 277
 278 &usbotg1 {
 279         dr_mode = "otg";
 280         hnp-disable;
 281         srp-disable;
 282         adp-disable;
 283         usb-role-switch;
 284         disable-over-current;
 285         samsung,picophy-pre-emp-curr-control = <3>;
 286         samsung,picophy-dc-vol-level-adjust = <7>;
 287         status = "okay";
 288
 289         port {
 290                 usb1_drd_sw: endpoint {
 291                         remote-endpoint = <&typec1_dr_sw>;
 292                 };
 293         };
 294 };
 295
 296 &usdhc2 {
 297         assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
 298         assigned-clock-rates = <200000000>;
 299         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 300         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 301         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 302         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 303         cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 304         bus-width = <4>;
 305         vmmc-supply = <&reg_usdhc2_vmmc>;
 306         status = "okay";
 307 };
 308
 309 &usdhc3 {
 310         assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
 311         assigned-clock-rates = <400000000>;
 312         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 313         pinctrl-0 = <&pinctrl_usdhc3>;
 314         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 315         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 316         bus-width = <8>;
 317         non-removable;
 318         status = "okay";
 319 };
 320
 321 &wdog1 {
 322         pinctrl-names = "default";
 323         pinctrl-0 = <&pinctrl_wdog>;
 324         fsl,ext-reset-output;
 325         status = "okay";
 326 };
 327
 328 &iomuxc {
 329         pinctrl_fec1: fec1grp {
 330                 fsl,pins = <
 331                         MX8MN_IOMUXC_ENET_MDC_ENET1_MDC         0x3
 332                         MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO       0x3
 333                         MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3   0x1f
 334                         MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2   0x1f
 335                         MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1   0x1f
 336                         MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0   0x1f
 337                         MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3   0x91
 338                         MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2   0x91
 339                         MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1   0x91
 340                         MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0   0x91
 341                         MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC   0x1f
 342                         MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC   0x91
 343                         MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 344                         MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 345                         MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22        0x19
 346                 >;
 347         };
 348
 349         pinctrl_flexspi: flexspigrp {
 350                 fsl,pins = <
 351                         MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK               0x1c2
 352                         MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B            0x82
 353                         MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0           0x82
 354                         MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1           0x82
 355                         MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2           0x82
 356                         MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3           0x82
 357                 >;
 358         };
 359
 360         pinctrl_gpio_led: gpioledgrp {
 361                 fsl,pins = <
 362                         MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16    0x19
 363                 >;
 364         };
 365
 366         pinctrl_gpio_wlf: gpiowlfgrp {
 367                 fsl,pins = <
 368                         MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21        0xd6
 369                 >;
 370         };
 371
 372         pinctrl_ir: irgrp {
 373                 fsl,pins = <
 374                         MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13              0x4f
 375                 >;
 376         };
 377
 378         pinctrl_i2c1: i2c1grp {
 379                 fsl,pins = <
 380                         MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL          0x400001c3
 381                         MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA          0x400001c3
 382                 >;
 383         };
 384
 385         pinctrl_i2c2: i2c2grp {
 386                 fsl,pins = <
 387                         MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL          0x400001c3
 388                         MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA          0x400001c3
 389                 >;
 390         };
 391
 392         pinctrl_i2c2_gpio: i2c2gpiogrp {
 393                 fsl,pins = <
 394                         MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16        0x1c3
 395                         MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17        0x1c3
 396                 >;
 397         };
 398
 399         pinctrl_i2c3: i2c3grp {
 400                 fsl,pins = <
 401                         MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL          0x400001c3
 402                         MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA          0x400001c3
 403                 >;
 404         };
 405
 406         pinctrl_i2c3_gpio: i2c3gpiogrp {
 407                 fsl,pins = <
 408                         MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18        0x1c3
 409                         MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19        0x1c3
 410                 >;
 411         };
 412
 413         pinctrl_pmic: pmicirqgrp {
 414                 fsl,pins = <
 415                         MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3       0x141
 416                 >;
 417         };
 418
 419         pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
 420                 fsl,pins = <
 421                         MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19     0x41
 422                 >;
 423         };
 424
 425         pinctrl_sai2: sai2grp {
 426                 fsl,pins = <
 427                         MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK      0xd6
 428                         MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC     0xd6
 429                         MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0    0xd6
 430                         MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0    0xd6
 431                 >;
 432         };
 433
 434         pinctrl_sai3: sai3grp {
 435                 fsl,pins = <
 436                         MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
 437                         MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
 438                         MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
 439                         MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
 440                 >;
 441         };
 442
 443         pinctrl_spdif1: spdif1grp {
 444                 fsl,pins = <
 445                         MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT        0xd6
 446                         MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN         0xd6
 447                 >;
 448         };
 449
 450         pinctrl_typec1: typec1grp {
 451                 fsl,pins = <
 452                         MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11      0x159
 453                 >;
 454         };
 455
 456         pinctrl_uart1: uart1grp {
 457                 fsl,pins = <
 458                         MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX     0x140
 459                         MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX     0x140
 460                         MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B  0x140
 461                         MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B  0x140
 462                 >;
 463         };
 464
 465         pinctrl_uart2: uart2grp {
 466                 fsl,pins = <
 467                         MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140
 468                         MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140
 469                 >;
 470         };
 471
 472         pinctrl_uart3: uart3grp {
 473                 fsl,pins = <
 474                         MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX           0x140
 475                         MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX           0x140
 476                         MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140
 477                         MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B        0x140
 478                 >;
 479         };
 480
 481         pinctrl_usdhc2_gpio: usdhc2gpiogrp {
 482                 fsl,pins = <
 483                         MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15      0x1c4
 484                 >;
 485         };
 486
 487         pinctrl_usdhc2: usdhc2grp {
 488                 fsl,pins = <
 489                         MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x190
 490                         MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d0
 491                         MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d0
 492                         MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d0
 493                         MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d0
 494                         MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d0
 495                         MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 496                 >;
 497         };
 498
 499         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 500                 fsl,pins = <
 501                         MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x194
 502                         MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d4
 503                         MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d4
 504                         MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d4
 505                         MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d4
 506                         MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d4
 507                         MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 508                 >;
 509         };
 510
 511         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 512                 fsl,pins = <
 513                         MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x196
 514                         MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d6
 515                         MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d6
 516                         MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d6
 517                         MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d6
 518                         MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d6
 519                         MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 520                 >;
 521         };
 522
 523         pinctrl_usdhc3: usdhc3grp {
 524                 fsl,pins = <
 525                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x40000190
 526                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d0
 527                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d0
 528                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d0
 529                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
 530                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d0
 531                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d0
 532                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d0
 533                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d0
 534                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d0
 535                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x190
 536                 >;
 537         };
 538
 539         pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
 540                 fsl,pins = <
 541                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x40000194
 542                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d4
 543                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d4
 544                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d4
 545                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d4
 546                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d4
 547                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d4
 548                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d4
 549                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d4
 550                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d4
 551                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x194
 552                 >;
 553         };
 554
 555         pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
 556                 fsl,pins = <
 557                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x40000196
 558                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d6
 559                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d6
 560                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d6
 561                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d6
 562                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d6
 563                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d6
 564                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d6
 565                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d6
 566                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d6
 567                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x196
 568                 >;
 569         };
 570
 571         pinctrl_wdog: wdoggrp {
 572                 fsl,pins = <
 573                         MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B            0x166
 574                 >;
 575         };
 576 };