1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mm-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx8mm-pinfunc.h"
15 interrupt-parent = <&gic>;
47 entry-method = "psci";
49 cpu_pd_wait: cpu-pd-wait {
50 compatible = "arm,idle-state";
51 arm,psci-suspend-param = <0x0010033>;
53 entry-latency-us = <1000>;
54 exit-latency-us = <700>;
55 min-residency-us = <2700>;
61 compatible = "arm,cortex-a53";
63 clock-latency = <61036>; /* two CLK32 periods */
64 clocks = <&clk IMX8MM_CLK_ARM>;
65 enable-method = "psci";
66 next-level-cache = <&A53_L2>;
67 operating-points-v2 = <&a53_opp_table>;
68 nvmem-cells = <&cpu_speed_grade>;
69 nvmem-cell-names = "speed_grade";
70 cpu-idle-states = <&cpu_pd_wait>;
76 compatible = "arm,cortex-a53";
78 clock-latency = <61036>; /* two CLK32 periods */
79 clocks = <&clk IMX8MM_CLK_ARM>;
80 enable-method = "psci";
81 next-level-cache = <&A53_L2>;
82 operating-points-v2 = <&a53_opp_table>;
83 cpu-idle-states = <&cpu_pd_wait>;
89 compatible = "arm,cortex-a53";
91 clock-latency = <61036>; /* two CLK32 periods */
92 clocks = <&clk IMX8MM_CLK_ARM>;
93 enable-method = "psci";
94 next-level-cache = <&A53_L2>;
95 operating-points-v2 = <&a53_opp_table>;
96 cpu-idle-states = <&cpu_pd_wait>;
102 compatible = "arm,cortex-a53";
104 clock-latency = <61036>; /* two CLK32 periods */
105 clocks = <&clk IMX8MM_CLK_ARM>;
106 enable-method = "psci";
107 next-level-cache = <&A53_L2>;
108 operating-points-v2 = <&a53_opp_table>;
109 cpu-idle-states = <&cpu_pd_wait>;
110 #cooling-cells = <2>;
114 compatible = "cache";
118 a53_opp_table: opp-table {
119 compatible = "operating-points-v2";
123 opp-hz = /bits/ 64 <1200000000>;
124 opp-microvolt = <850000>;
125 opp-supported-hw = <0xe>, <0x7>;
126 clock-latency-ns = <150000>;
131 opp-hz = /bits/ 64 <1600000000>;
132 opp-microvolt = <950000>;
133 opp-supported-hw = <0xc>, <0x7>;
134 clock-latency-ns = <150000>;
139 opp-hz = /bits/ 64 <1800000000>;
140 opp-microvolt = <1000000>;
141 opp-supported-hw = <0x8>, <0x3>;
142 clock-latency-ns = <150000>;
147 osc_32k: clock-osc-32k {
148 compatible = "fixed-clock";
150 clock-frequency = <32768>;
151 clock-output-names = "osc_32k";
154 osc_24m: clock-osc-24m {
155 compatible = "fixed-clock";
157 clock-frequency = <24000000>;
158 clock-output-names = "osc_24m";
161 clk_ext1: clock-ext1 {
162 compatible = "fixed-clock";
164 clock-frequency = <133000000>;
165 clock-output-names = "clk_ext1";
168 clk_ext2: clock-ext2 {
169 compatible = "fixed-clock";
171 clock-frequency = <133000000>;
172 clock-output-names = "clk_ext2";
175 clk_ext3: clock-ext3 {
176 compatible = "fixed-clock";
178 clock-frequency = <133000000>;
179 clock-output-names = "clk_ext3";
182 clk_ext4: clock-ext4 {
183 compatible = "fixed-clock";
185 clock-frequency= <133000000>;
186 clock-output-names = "clk_ext4";
190 compatible = "arm,psci-1.0";
195 compatible = "arm,armv8-pmuv3";
196 interrupts = <GIC_PPI 7
197 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
198 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
202 compatible = "arm,armv8-timer";
203 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
204 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
205 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
206 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
207 clock-frequency = <8000000>;
208 arm,no-tick-in-suspend;
213 polling-delay-passive = <250>;
214 polling-delay = <2000>;
215 thermal-sensors = <&tmu>;
218 temperature = <85000>;
224 temperature = <95000>;
232 trip = <&cpu_alert0>;
234 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
235 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
236 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
237 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
243 usbphynop1: usbphynop1 {
244 compatible = "usb-nop-xceiv";
245 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
246 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
247 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
248 clock-names = "main_clk";
251 usbphynop2: usbphynop2 {
252 compatible = "usb-nop-xceiv";
253 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
254 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
255 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
256 clock-names = "main_clk";
260 compatible = "fsl,imx8mm-soc", "simple-bus";
261 #address-cells = <1>;
263 ranges = <0x0 0x0 0x0 0x3e000000>;
264 nvmem-cells = <&imx8mm_uid>;
265 nvmem-cell-names = "soc_unique_id";
267 aips1: bus@30000000 {
268 compatible = "fsl,aips-bus", "simple-bus";
269 reg = <0x30000000 0x400000>;
270 #address-cells = <1>;
272 ranges = <0x30000000 0x30000000 0x400000>;
275 #sound-dai-cells = <0>;
276 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
277 reg = <0x30010000 0x10000>;
278 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
280 <&clk IMX8MM_CLK_SAI1_ROOT>,
281 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
282 clock-names = "bus", "mclk1", "mclk2", "mclk3";
283 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
284 dma-names = "rx", "tx";
289 #sound-dai-cells = <0>;
290 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
291 reg = <0x30020000 0x10000>;
292 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
294 <&clk IMX8MM_CLK_SAI2_ROOT>,
295 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
296 clock-names = "bus", "mclk1", "mclk2", "mclk3";
297 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
298 dma-names = "rx", "tx";
303 #sound-dai-cells = <0>;
304 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
305 reg = <0x30030000 0x10000>;
306 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
307 clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
308 <&clk IMX8MM_CLK_SAI3_ROOT>,
309 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
310 clock-names = "bus", "mclk1", "mclk2", "mclk3";
311 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
312 dma-names = "rx", "tx";
317 #sound-dai-cells = <0>;
318 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
319 reg = <0x30050000 0x10000>;
320 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
321 clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
322 <&clk IMX8MM_CLK_SAI5_ROOT>,
323 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
324 clock-names = "bus", "mclk1", "mclk2", "mclk3";
325 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
326 dma-names = "rx", "tx";
331 #sound-dai-cells = <0>;
332 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
333 reg = <0x30060000 0x10000>;
334 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
336 <&clk IMX8MM_CLK_SAI6_ROOT>,
337 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
338 clock-names = "bus", "mclk1", "mclk2", "mclk3";
339 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
340 dma-names = "rx", "tx";
344 micfil: audio-controller@30080000 {
345 compatible = "fsl,imx8mm-micfil";
346 reg = <0x30080000 0x10000>;
347 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
350 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
351 clocks = <&clk IMX8MM_CLK_PDM_IPG>,
352 <&clk IMX8MM_CLK_PDM_ROOT>,
353 <&clk IMX8MM_AUDIO_PLL1_OUT>,
354 <&clk IMX8MM_AUDIO_PLL2_OUT>,
355 <&clk IMX8MM_CLK_EXT3>;
356 clock-names = "ipg_clk", "ipg_clk_app",
357 "pll8k", "pll11k", "clkext3";
358 dmas = <&sdma2 24 25 0x80000000>;
363 spdif1: spdif@30090000 {
364 compatible = "fsl,imx35-spdif";
365 reg = <0x30090000 0x10000>;
366 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */
368 <&clk IMX8MM_CLK_24M>, /* rxtx0 */
369 <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */
370 <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */
371 <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */
372 <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */
373 <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */
374 <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */
375 <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */
376 <&clk IMX8MM_CLK_DUMMY>; /* spba */
377 clock-names = "core", "rxtx0",
382 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
383 dma-names = "rx", "tx";
387 gpio1: gpio@30200000 {
388 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
389 reg = <0x30200000 0x10000>;
390 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
391 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>;
395 interrupt-controller;
396 #interrupt-cells = <2>;
397 gpio-ranges = <&iomuxc 0 10 30>;
400 gpio2: gpio@30210000 {
401 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
402 reg = <0x30210000 0x10000>;
403 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>;
408 interrupt-controller;
409 #interrupt-cells = <2>;
410 gpio-ranges = <&iomuxc 0 40 21>;
413 gpio3: gpio@30220000 {
414 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
415 reg = <0x30220000 0x10000>;
416 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>;
421 interrupt-controller;
422 #interrupt-cells = <2>;
423 gpio-ranges = <&iomuxc 0 61 26>;
426 gpio4: gpio@30230000 {
427 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
428 reg = <0x30230000 0x10000>;
429 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
430 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>;
434 interrupt-controller;
435 #interrupt-cells = <2>;
436 gpio-ranges = <&iomuxc 0 87 32>;
439 gpio5: gpio@30240000 {
440 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
441 reg = <0x30240000 0x10000>;
442 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>;
447 interrupt-controller;
448 #interrupt-cells = <2>;
449 gpio-ranges = <&iomuxc 0 119 30>;
453 compatible = "fsl,imx8mm-tmu";
454 reg = <0x30260000 0x10000>;
455 clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
456 #thermal-sensor-cells = <0>;
459 wdog1: watchdog@30280000 {
460 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
461 reg = <0x30280000 0x10000>;
462 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>;
467 wdog2: watchdog@30290000 {
468 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
469 reg = <0x30290000 0x10000>;
470 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
471 clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>;
475 wdog3: watchdog@302a0000 {
476 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
477 reg = <0x302a0000 0x10000>;
478 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>;
483 sdma2: dma-controller@302c0000 {
484 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
485 reg = <0x302c0000 0x10000>;
486 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
487 clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
488 <&clk IMX8MM_CLK_SDMA2_ROOT>;
489 clock-names = "ipg", "ahb";
491 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
494 sdma3: dma-controller@302b0000 {
495 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
496 reg = <0x302b0000 0x10000>;
497 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
499 <&clk IMX8MM_CLK_SDMA3_ROOT>;
500 clock-names = "ipg", "ahb";
502 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
505 iomuxc: pinctrl@30330000 {
506 compatible = "fsl,imx8mm-iomuxc";
507 reg = <0x30330000 0x10000>;
510 gpr: iomuxc-gpr@30340000 {
511 compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
512 reg = <0x30340000 0x10000>;
515 ocotp: efuse@30350000 {
516 compatible = "fsl,imx8mm-ocotp", "syscon";
517 reg = <0x30350000 0x10000>;
518 clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
519 /* For nvmem subnodes */
520 #address-cells = <1>;
523 imx8mm_uid: unique-id@410 {
527 cpu_speed_grade: speed-grade@10 {
531 fec_mac_address: mac-address@90 {
536 anatop: anatop@30360000 {
537 compatible = "fsl,imx8mm-anatop", "syscon";
538 reg = <0x30360000 0x10000>;
541 snvs: snvs@30370000 {
542 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
543 reg = <0x30370000 0x10000>;
545 snvs_rtc: snvs-rtc-lp {
546 compatible = "fsl,sec-v4.0-mon-rtc-lp";
549 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
550 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
552 clock-names = "snvs-rtc";
555 snvs_pwrkey: snvs-powerkey {
556 compatible = "fsl,sec-v4.0-pwrkey";
558 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
560 clock-names = "snvs-pwrkey";
561 linux,keycode = <KEY_POWER>;
567 clk: clock-controller@30380000 {
568 compatible = "fsl,imx8mm-ccm";
569 reg = <0x30380000 0x10000>;
571 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
572 <&clk_ext3>, <&clk_ext4>;
573 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
574 "clk_ext3", "clk_ext4";
575 assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>,
576 <&clk IMX8MM_CLK_A53_CORE>,
577 <&clk IMX8MM_CLK_NOC>,
578 <&clk IMX8MM_CLK_AUDIO_AHB>,
579 <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
580 <&clk IMX8MM_SYS_PLL3>,
581 <&clk IMX8MM_VIDEO_PLL1>,
582 <&clk IMX8MM_AUDIO_PLL1>,
583 <&clk IMX8MM_AUDIO_PLL2>;
584 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
585 <&clk IMX8MM_ARM_PLL_OUT>,
586 <&clk IMX8MM_SYS_PLL3_OUT>,
587 <&clk IMX8MM_SYS_PLL1_800M>;
588 assigned-clock-rates = <0>, <0>, <0>,
597 src: reset-controller@30390000 {
598 compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon";
599 reg = <0x30390000 0x10000>;
600 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
605 aips2: bus@30400000 {
606 compatible = "fsl,aips-bus", "simple-bus";
607 reg = <0x30400000 0x400000>;
608 #address-cells = <1>;
610 ranges = <0x30400000 0x30400000 0x400000>;
613 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
614 reg = <0x30660000 0x10000>;
615 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
616 clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
617 <&clk IMX8MM_CLK_PWM1_ROOT>;
618 clock-names = "ipg", "per";
624 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
625 reg = <0x30670000 0x10000>;
626 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
627 clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
628 <&clk IMX8MM_CLK_PWM2_ROOT>;
629 clock-names = "ipg", "per";
635 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
636 reg = <0x30680000 0x10000>;
637 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
638 clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
639 <&clk IMX8MM_CLK_PWM3_ROOT>;
640 clock-names = "ipg", "per";
646 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
647 reg = <0x30690000 0x10000>;
648 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
649 clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
650 <&clk IMX8MM_CLK_PWM4_ROOT>;
651 clock-names = "ipg", "per";
656 system_counter: timer@306a0000 {
657 compatible = "nxp,sysctr-timer";
658 reg = <0x306a0000 0x20000>;
659 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
665 aips3: bus@30800000 {
666 compatible = "fsl,aips-bus", "simple-bus";
667 reg = <0x30800000 0x400000>;
668 #address-cells = <1>;
670 ranges = <0x30800000 0x30800000 0x400000>,
671 <0x8000000 0x8000000 0x10000000>;
673 ecspi1: spi@30820000 {
674 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
675 #address-cells = <1>;
677 reg = <0x30820000 0x10000>;
678 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
679 clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
680 <&clk IMX8MM_CLK_ECSPI1_ROOT>;
681 clock-names = "ipg", "per";
682 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
683 dma-names = "rx", "tx";
687 ecspi2: spi@30830000 {
688 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
689 #address-cells = <1>;
691 reg = <0x30830000 0x10000>;
692 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
693 clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
694 <&clk IMX8MM_CLK_ECSPI2_ROOT>;
695 clock-names = "ipg", "per";
696 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
697 dma-names = "rx", "tx";
701 ecspi3: spi@30840000 {
702 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
703 #address-cells = <1>;
705 reg = <0x30840000 0x10000>;
706 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
707 clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
708 <&clk IMX8MM_CLK_ECSPI3_ROOT>;
709 clock-names = "ipg", "per";
710 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
711 dma-names = "rx", "tx";
715 uart1: serial@30860000 {
716 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
717 reg = <0x30860000 0x10000>;
718 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
719 clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
720 <&clk IMX8MM_CLK_UART1_ROOT>;
721 clock-names = "ipg", "per";
722 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
723 dma-names = "rx", "tx";
727 uart3: serial@30880000 {
728 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
729 reg = <0x30880000 0x10000>;
730 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
731 clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
732 <&clk IMX8MM_CLK_UART3_ROOT>;
733 clock-names = "ipg", "per";
734 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
735 dma-names = "rx", "tx";
739 uart2: serial@30890000 {
740 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
741 reg = <0x30890000 0x10000>;
742 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
743 clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
744 <&clk IMX8MM_CLK_UART2_ROOT>;
745 clock-names = "ipg", "per";
749 crypto: crypto@30900000 {
750 compatible = "fsl,sec-v4.0";
751 #address-cells = <1>;
753 reg = <0x30900000 0x40000>;
754 ranges = <0 0x30900000 0x40000>;
755 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
756 clocks = <&clk IMX8MM_CLK_AHB>,
757 <&clk IMX8MM_CLK_IPG_ROOT>;
758 clock-names = "aclk", "ipg";
761 compatible = "fsl,sec-v4.0-job-ring";
762 reg = <0x1000 0x1000>;
763 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
767 compatible = "fsl,sec-v4.0-job-ring";
768 reg = <0x2000 0x1000>;
769 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
773 compatible = "fsl,sec-v4.0-job-ring";
774 reg = <0x3000 0x1000>;
775 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
780 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
781 #address-cells = <1>;
783 reg = <0x30a20000 0x10000>;
784 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
785 clocks = <&clk IMX8MM_CLK_I2C1_ROOT>;
790 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
791 #address-cells = <1>;
793 reg = <0x30a30000 0x10000>;
794 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
795 clocks = <&clk IMX8MM_CLK_I2C2_ROOT>;
800 #address-cells = <1>;
802 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
803 reg = <0x30a40000 0x10000>;
804 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
805 clocks = <&clk IMX8MM_CLK_I2C3_ROOT>;
810 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
811 #address-cells = <1>;
813 reg = <0x30a50000 0x10000>;
814 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
815 clocks = <&clk IMX8MM_CLK_I2C4_ROOT>;
819 uart4: serial@30a60000 {
820 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
821 reg = <0x30a60000 0x10000>;
822 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
823 clocks = <&clk IMX8MM_CLK_UART4_ROOT>,
824 <&clk IMX8MM_CLK_UART4_ROOT>;
825 clock-names = "ipg", "per";
826 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
827 dma-names = "rx", "tx";
831 mu: mailbox@30aa0000 {
832 compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
833 reg = <0x30aa0000 0x10000>;
834 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
835 clocks = <&clk IMX8MM_CLK_MU_ROOT>;
839 usdhc1: mmc@30b40000 {
840 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
841 reg = <0x30b40000 0x10000>;
842 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
843 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
844 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
845 <&clk IMX8MM_CLK_USDHC1_ROOT>;
846 clock-names = "ipg", "ahb", "per";
847 fsl,tuning-start-tap = <20>;
848 fsl,tuning-step= <2>;
853 usdhc2: mmc@30b50000 {
854 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
855 reg = <0x30b50000 0x10000>;
856 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
857 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
858 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
859 <&clk IMX8MM_CLK_USDHC2_ROOT>;
860 clock-names = "ipg", "ahb", "per";
861 fsl,tuning-start-tap = <20>;
862 fsl,tuning-step= <2>;
867 usdhc3: mmc@30b60000 {
868 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
869 reg = <0x30b60000 0x10000>;
870 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
872 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
873 <&clk IMX8MM_CLK_USDHC3_ROOT>;
874 clock-names = "ipg", "ahb", "per";
875 fsl,tuning-start-tap = <20>;
876 fsl,tuning-step= <2>;
881 flexspi: spi@30bb0000 {
882 #address-cells = <1>;
884 compatible = "nxp,imx8mm-fspi";
885 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
886 reg-names = "fspi_base", "fspi_mmap";
887 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
888 clocks = <&clk IMX8MM_CLK_QSPI_ROOT>,
889 <&clk IMX8MM_CLK_QSPI_ROOT>;
890 clock-names = "fspi_en", "fspi";
894 sdma1: dma-controller@30bd0000 {
895 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
896 reg = <0x30bd0000 0x10000>;
897 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
898 clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
899 <&clk IMX8MM_CLK_AHB>;
900 clock-names = "ipg", "ahb";
902 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
905 fec1: ethernet@30be0000 {
906 compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec";
907 reg = <0x30be0000 0x10000>;
908 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
909 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
910 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
911 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
912 clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
913 <&clk IMX8MM_CLK_ENET1_ROOT>,
914 <&clk IMX8MM_CLK_ENET_TIMER>,
915 <&clk IMX8MM_CLK_ENET_REF>,
916 <&clk IMX8MM_CLK_ENET_PHY_REF>;
917 clock-names = "ipg", "ahb", "ptp",
918 "enet_clk_ref", "enet_out";
919 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
920 <&clk IMX8MM_CLK_ENET_TIMER>,
921 <&clk IMX8MM_CLK_ENET_REF>,
922 <&clk IMX8MM_CLK_ENET_PHY_REF>;
923 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
924 <&clk IMX8MM_SYS_PLL2_100M>,
925 <&clk IMX8MM_SYS_PLL2_125M>,
926 <&clk IMX8MM_SYS_PLL2_50M>;
927 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
928 fsl,num-tx-queues = <3>;
929 fsl,num-rx-queues = <3>;
930 nvmem-cells = <&fec_mac_address>;
931 nvmem-cell-names = "mac-address";
933 fsl,stop-mode = <&gpr 0x10 3>;
939 aips4: bus@32c00000 {
940 compatible = "fsl,aips-bus", "simple-bus";
941 reg = <0x32c00000 0x400000>;
942 #address-cells = <1>;
944 ranges = <0x32c00000 0x32c00000 0x400000>;
946 usbotg1: usb@32e40000 {
947 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
948 reg = <0x32e40000 0x200>;
949 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
950 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
951 clock-names = "usb1_ctrl_root_clk";
952 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
953 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
954 fsl,usbphy = <&usbphynop1>;
955 fsl,usbmisc = <&usbmisc1 0>;
959 usbmisc1: usbmisc@32e40200 {
960 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
962 reg = <0x32e40200 0x200>;
965 usbotg2: usb@32e50000 {
966 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
967 reg = <0x32e50000 0x200>;
968 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
969 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
970 clock-names = "usb1_ctrl_root_clk";
971 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
972 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
973 fsl,usbphy = <&usbphynop2>;
974 fsl,usbmisc = <&usbmisc2 0>;
978 usbmisc2: usbmisc@32e50200 {
979 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
981 reg = <0x32e50200 0x200>;
986 dma_apbh: dma-controller@33000000 {
987 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
988 reg = <0x33000000 0x2000>;
989 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
990 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
991 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
992 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
993 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
996 clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
999 gpmi: nand-controller@33002000{
1000 compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
1001 #address-cells = <1>;
1003 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1004 reg-names = "gpmi-nand", "bch";
1005 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1006 interrupt-names = "bch";
1007 clocks = <&clk IMX8MM_CLK_NAND_ROOT>,
1008 <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1009 clock-names = "gpmi_io", "gpmi_bch_apb";
1010 dmas = <&dma_apbh 0>;
1011 dma-names = "rx-tx";
1012 status = "disabled";
1015 gic: interrupt-controller@38800000 {
1016 compatible = "arm,gic-v3";
1017 reg = <0x38800000 0x10000>, /* GIC Dist */
1018 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
1019 #interrupt-cells = <3>;
1020 interrupt-controller;
1021 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1024 ddrc: memory-controller@3d400000 {
1025 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
1026 reg = <0x3d400000 0x400000>;
1027 clock-names = "core", "pll", "alt", "apb";
1028 clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
1029 <&clk IMX8MM_DRAM_PLL>,
1030 <&clk IMX8MM_CLK_DRAM_ALT>,
1031 <&clk IMX8MM_CLK_DRAM_APB>;
1035 compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
1036 reg = <0x3d800000 0x400000>;
1037 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;