1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mm-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/imx8mm-power.h>
11 #include <dt-bindings/reset/imx8mq-reset.h>
12 #include <dt-bindings/thermal/thermal.h>
14 #include "imx8mm-pinfunc.h"
17 interrupt-parent = <&gic>;
49 entry-method = "psci";
51 cpu_pd_wait: cpu-pd-wait {
52 compatible = "arm,idle-state";
53 arm,psci-suspend-param = <0x0010033>;
55 entry-latency-us = <1000>;
56 exit-latency-us = <700>;
57 min-residency-us = <2700>;
63 compatible = "arm,cortex-a53";
65 clock-latency = <61036>; /* two CLK32 periods */
66 clocks = <&clk IMX8MM_CLK_ARM>;
67 enable-method = "psci";
68 i-cache-size = <0x8000>;
69 i-cache-line-size = <64>;
71 d-cache-size = <0x8000>;
72 d-cache-line-size = <64>;
74 next-level-cache = <&A53_L2>;
75 operating-points-v2 = <&a53_opp_table>;
76 nvmem-cells = <&cpu_speed_grade>;
77 nvmem-cell-names = "speed_grade";
78 cpu-idle-states = <&cpu_pd_wait>;
84 compatible = "arm,cortex-a53";
86 clock-latency = <61036>; /* two CLK32 periods */
87 clocks = <&clk IMX8MM_CLK_ARM>;
88 enable-method = "psci";
89 i-cache-size = <0x8000>;
90 i-cache-line-size = <64>;
92 d-cache-size = <0x8000>;
93 d-cache-line-size = <64>;
95 next-level-cache = <&A53_L2>;
96 operating-points-v2 = <&a53_opp_table>;
97 cpu-idle-states = <&cpu_pd_wait>;
103 compatible = "arm,cortex-a53";
105 clock-latency = <61036>; /* two CLK32 periods */
106 clocks = <&clk IMX8MM_CLK_ARM>;
107 enable-method = "psci";
108 i-cache-size = <0x8000>;
109 i-cache-line-size = <64>;
110 i-cache-sets = <256>;
111 d-cache-size = <0x8000>;
112 d-cache-line-size = <64>;
113 d-cache-sets = <128>;
114 next-level-cache = <&A53_L2>;
115 operating-points-v2 = <&a53_opp_table>;
116 cpu-idle-states = <&cpu_pd_wait>;
117 #cooling-cells = <2>;
122 compatible = "arm,cortex-a53";
124 clock-latency = <61036>; /* two CLK32 periods */
125 clocks = <&clk IMX8MM_CLK_ARM>;
126 enable-method = "psci";
127 i-cache-size = <0x8000>;
128 i-cache-line-size = <64>;
129 i-cache-sets = <256>;
130 d-cache-size = <0x8000>;
131 d-cache-line-size = <64>;
132 d-cache-sets = <128>;
133 next-level-cache = <&A53_L2>;
134 operating-points-v2 = <&a53_opp_table>;
135 cpu-idle-states = <&cpu_pd_wait>;
136 #cooling-cells = <2>;
140 compatible = "cache";
142 cache-size = <0x80000>;
143 cache-line-size = <64>;
148 a53_opp_table: opp-table {
149 compatible = "operating-points-v2";
153 opp-hz = /bits/ 64 <1200000000>;
154 opp-microvolt = <850000>;
155 opp-supported-hw = <0xe>, <0x7>;
156 clock-latency-ns = <150000>;
161 opp-hz = /bits/ 64 <1600000000>;
162 opp-microvolt = <950000>;
163 opp-supported-hw = <0xc>, <0x7>;
164 clock-latency-ns = <150000>;
169 opp-hz = /bits/ 64 <1800000000>;
170 opp-microvolt = <1000000>;
171 opp-supported-hw = <0x8>, <0x3>;
172 clock-latency-ns = <150000>;
177 osc_32k: clock-osc-32k {
178 compatible = "fixed-clock";
180 clock-frequency = <32768>;
181 clock-output-names = "osc_32k";
184 osc_24m: clock-osc-24m {
185 compatible = "fixed-clock";
187 clock-frequency = <24000000>;
188 clock-output-names = "osc_24m";
191 clk_ext1: clock-ext1 {
192 compatible = "fixed-clock";
194 clock-frequency = <133000000>;
195 clock-output-names = "clk_ext1";
198 clk_ext2: clock-ext2 {
199 compatible = "fixed-clock";
201 clock-frequency = <133000000>;
202 clock-output-names = "clk_ext2";
205 clk_ext3: clock-ext3 {
206 compatible = "fixed-clock";
208 clock-frequency = <133000000>;
209 clock-output-names = "clk_ext3";
212 clk_ext4: clock-ext4 {
213 compatible = "fixed-clock";
215 clock-frequency= <133000000>;
216 clock-output-names = "clk_ext4";
220 compatible = "arm,psci-1.0";
225 compatible = "arm,cortex-a53-pmu";
226 interrupts = <GIC_PPI 7
227 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
231 compatible = "arm,armv8-timer";
232 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
233 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
234 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
235 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
236 clock-frequency = <8000000>;
237 arm,no-tick-in-suspend;
242 polling-delay-passive = <250>;
243 polling-delay = <2000>;
244 thermal-sensors = <&tmu>;
247 temperature = <85000>;
253 temperature = <95000>;
261 trip = <&cpu_alert0>;
263 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
264 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
265 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
266 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
272 usbphynop1: usbphynop1 {
274 compatible = "usb-nop-xceiv";
275 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
276 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
277 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
278 clock-names = "main_clk";
281 usbphynop2: usbphynop2 {
283 compatible = "usb-nop-xceiv";
284 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
285 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
286 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
287 clock-names = "main_clk";
291 compatible = "fsl,imx8mm-soc", "simple-bus";
292 #address-cells = <1>;
294 ranges = <0x0 0x0 0x0 0x3e000000>;
295 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
296 nvmem-cells = <&imx8mm_uid>;
297 nvmem-cell-names = "soc_unique_id";
299 aips1: bus@30000000 {
300 compatible = "fsl,aips-bus", "simple-bus";
301 reg = <0x30000000 0x400000>;
302 #address-cells = <1>;
304 ranges = <0x30000000 0x30000000 0x400000>;
306 spba2: spba-bus@30000000 {
307 compatible = "fsl,spba-bus", "simple-bus";
308 #address-cells = <1>;
310 reg = <0x30000000 0x100000>;
314 #sound-dai-cells = <0>;
315 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
316 reg = <0x30010000 0x10000>;
317 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
319 <&clk IMX8MM_CLK_SAI1_ROOT>,
320 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
321 clock-names = "bus", "mclk1", "mclk2", "mclk3";
322 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
323 dma-names = "rx", "tx";
328 #sound-dai-cells = <0>;
329 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
330 reg = <0x30020000 0x10000>;
331 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
333 <&clk IMX8MM_CLK_SAI2_ROOT>,
334 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
335 clock-names = "bus", "mclk1", "mclk2", "mclk3";
336 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
337 dma-names = "rx", "tx";
342 #sound-dai-cells = <0>;
343 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
344 reg = <0x30030000 0x10000>;
345 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
347 <&clk IMX8MM_CLK_SAI3_ROOT>,
348 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
349 clock-names = "bus", "mclk1", "mclk2", "mclk3";
350 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
351 dma-names = "rx", "tx";
356 #sound-dai-cells = <0>;
357 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
358 reg = <0x30050000 0x10000>;
359 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
361 <&clk IMX8MM_CLK_SAI5_ROOT>,
362 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
363 clock-names = "bus", "mclk1", "mclk2", "mclk3";
364 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
365 dma-names = "rx", "tx";
370 #sound-dai-cells = <0>;
371 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
372 reg = <0x30060000 0x10000>;
373 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
375 <&clk IMX8MM_CLK_SAI6_ROOT>,
376 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
377 clock-names = "bus", "mclk1", "mclk2", "mclk3";
378 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
379 dma-names = "rx", "tx";
383 micfil: audio-controller@30080000 {
384 compatible = "fsl,imx8mm-micfil";
385 reg = <0x30080000 0x10000>;
386 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
387 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
388 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
389 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&clk IMX8MM_CLK_PDM_IPG>,
391 <&clk IMX8MM_CLK_PDM_ROOT>,
392 <&clk IMX8MM_AUDIO_PLL1_OUT>,
393 <&clk IMX8MM_AUDIO_PLL2_OUT>,
394 <&clk IMX8MM_CLK_EXT3>;
395 clock-names = "ipg_clk", "ipg_clk_app",
396 "pll8k", "pll11k", "clkext3";
397 dmas = <&sdma2 24 25 0x80000000>;
402 spdif1: spdif@30090000 {
403 compatible = "fsl,imx35-spdif";
404 reg = <0x30090000 0x10000>;
405 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */
407 <&clk IMX8MM_CLK_24M>, /* rxtx0 */
408 <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */
409 <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */
410 <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */
411 <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */
412 <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */
413 <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */
414 <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */
415 <&clk IMX8MM_CLK_DUMMY>; /* spba */
416 clock-names = "core", "rxtx0",
421 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
422 dma-names = "rx", "tx";
427 gpio1: gpio@30200000 {
428 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
429 reg = <0x30200000 0x10000>;
430 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
431 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>;
435 interrupt-controller;
436 #interrupt-cells = <2>;
437 gpio-ranges = <&iomuxc 0 10 30>;
440 gpio2: gpio@30210000 {
441 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
442 reg = <0x30210000 0x10000>;
443 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>;
448 interrupt-controller;
449 #interrupt-cells = <2>;
450 gpio-ranges = <&iomuxc 0 40 21>;
453 gpio3: gpio@30220000 {
454 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
455 reg = <0x30220000 0x10000>;
456 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>;
461 interrupt-controller;
462 #interrupt-cells = <2>;
463 gpio-ranges = <&iomuxc 0 61 26>;
466 gpio4: gpio@30230000 {
467 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
468 reg = <0x30230000 0x10000>;
469 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
470 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
471 clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>;
474 interrupt-controller;
475 #interrupt-cells = <2>;
476 gpio-ranges = <&iomuxc 0 87 32>;
479 gpio5: gpio@30240000 {
480 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
481 reg = <0x30240000 0x10000>;
482 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
483 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>;
487 interrupt-controller;
488 #interrupt-cells = <2>;
489 gpio-ranges = <&iomuxc 0 119 30>;
493 compatible = "fsl,imx8mm-tmu";
494 reg = <0x30260000 0x10000>;
495 clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
496 #thermal-sensor-cells = <0>;
499 wdog1: watchdog@30280000 {
500 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
501 reg = <0x30280000 0x10000>;
502 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>;
507 wdog2: watchdog@30290000 {
508 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
509 reg = <0x30290000 0x10000>;
510 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>;
515 wdog3: watchdog@302a0000 {
516 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
517 reg = <0x302a0000 0x10000>;
518 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
519 clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>;
523 sdma2: dma-controller@302c0000 {
524 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
525 reg = <0x302c0000 0x10000>;
526 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
527 clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
528 <&clk IMX8MM_CLK_SDMA2_ROOT>;
529 clock-names = "ipg", "ahb";
531 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
534 sdma3: dma-controller@302b0000 {
535 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
536 reg = <0x302b0000 0x10000>;
537 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
538 clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
539 <&clk IMX8MM_CLK_SDMA3_ROOT>;
540 clock-names = "ipg", "ahb";
542 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
545 iomuxc: pinctrl@30330000 {
546 compatible = "fsl,imx8mm-iomuxc";
547 reg = <0x30330000 0x10000>;
550 gpr: iomuxc-gpr@30340000 {
551 compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
552 reg = <0x30340000 0x10000>;
555 ocotp: efuse@30350000 {
556 compatible = "fsl,imx8mm-ocotp", "syscon";
557 reg = <0x30350000 0x10000>;
558 clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
559 /* For nvmem subnodes */
560 #address-cells = <1>;
563 imx8mm_uid: unique-id@410 {
567 cpu_speed_grade: speed-grade@10 {
571 fec_mac_address: mac-address@90 {
576 anatop: anatop@30360000 {
577 compatible = "fsl,imx8mm-anatop", "syscon";
578 reg = <0x30360000 0x10000>;
581 snvs: snvs@30370000 {
582 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
583 reg = <0x30370000 0x10000>;
585 snvs_rtc: snvs-rtc-lp {
586 compatible = "fsl,sec-v4.0-mon-rtc-lp";
589 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
591 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
592 clock-names = "snvs-rtc";
595 snvs_pwrkey: snvs-powerkey {
596 compatible = "fsl,sec-v4.0-pwrkey";
598 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
599 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
600 clock-names = "snvs-pwrkey";
601 linux,keycode = <KEY_POWER>;
607 clk: clock-controller@30380000 {
608 compatible = "fsl,imx8mm-ccm";
609 reg = <0x30380000 0x10000>;
611 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
612 <&clk_ext3>, <&clk_ext4>;
613 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
614 "clk_ext3", "clk_ext4";
615 assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>,
616 <&clk IMX8MM_CLK_A53_CORE>,
617 <&clk IMX8MM_CLK_NOC>,
618 <&clk IMX8MM_CLK_AUDIO_AHB>,
619 <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
620 <&clk IMX8MM_SYS_PLL3>,
621 <&clk IMX8MM_VIDEO_PLL1>,
622 <&clk IMX8MM_AUDIO_PLL1>;
623 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
624 <&clk IMX8MM_ARM_PLL_OUT>,
625 <&clk IMX8MM_SYS_PLL3_OUT>,
626 <&clk IMX8MM_SYS_PLL1_800M>;
627 assigned-clock-rates = <0>, <0>, <0>,
635 src: reset-controller@30390000 {
636 compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon";
637 reg = <0x30390000 0x10000>;
638 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
643 compatible = "fsl,imx8mm-gpc";
644 reg = <0x303a0000 0x10000>;
645 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
646 interrupt-parent = <&gic>;
647 interrupt-controller;
648 #interrupt-cells = <3>;
651 #address-cells = <1>;
654 pgc_hsiomix: power-domain@0 {
655 #power-domain-cells = <0>;
656 reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>;
657 clocks = <&clk IMX8MM_CLK_USB_BUS>;
658 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
659 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
662 pgc_pcie: power-domain@1 {
663 #power-domain-cells = <0>;
664 reg = <IMX8MM_POWER_DOMAIN_PCIE>;
665 power-domains = <&pgc_hsiomix>;
666 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>;
669 pgc_otg1: power-domain@2 {
670 #power-domain-cells = <0>;
671 reg = <IMX8MM_POWER_DOMAIN_OTG1>;
672 power-domains = <&pgc_hsiomix>;
675 pgc_otg2: power-domain@3 {
676 #power-domain-cells = <0>;
677 reg = <IMX8MM_POWER_DOMAIN_OTG2>;
678 power-domains = <&pgc_hsiomix>;
681 pgc_gpumix: power-domain@4 {
682 #power-domain-cells = <0>;
683 reg = <IMX8MM_POWER_DOMAIN_GPUMIX>;
684 clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
685 <&clk IMX8MM_CLK_GPU_AHB>;
686 assigned-clocks = <&clk IMX8MM_CLK_GPU_AXI>,
687 <&clk IMX8MM_CLK_GPU_AHB>;
688 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
689 <&clk IMX8MM_SYS_PLL1_800M>;
690 assigned-clock-rates = <800000000>, <400000000>;
693 pgc_gpu: power-domain@5 {
694 #power-domain-cells = <0>;
695 reg = <IMX8MM_POWER_DOMAIN_GPU>;
696 clocks = <&clk IMX8MM_CLK_GPU_AHB>,
697 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
698 <&clk IMX8MM_CLK_GPU2D_ROOT>,
699 <&clk IMX8MM_CLK_GPU3D_ROOT>;
700 resets = <&src IMX8MQ_RESET_GPU_RESET>;
701 power-domains = <&pgc_gpumix>;
704 pgc_vpumix: power-domain@6 {
705 #power-domain-cells = <0>;
706 reg = <IMX8MM_POWER_DOMAIN_VPUMIX>;
707 clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
708 assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>;
709 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>;
710 resets = <&src IMX8MQ_RESET_VPU_RESET>;
713 pgc_vpu_g1: power-domain@7 {
714 #power-domain-cells = <0>;
715 reg = <IMX8MM_POWER_DOMAIN_VPUG1>;
718 pgc_vpu_g2: power-domain@8 {
719 #power-domain-cells = <0>;
720 reg = <IMX8MM_POWER_DOMAIN_VPUG2>;
723 pgc_vpu_h1: power-domain@9 {
724 #power-domain-cells = <0>;
725 reg = <IMX8MM_POWER_DOMAIN_VPUH1>;
728 pgc_dispmix: power-domain@10 {
729 #power-domain-cells = <0>;
730 reg = <IMX8MM_POWER_DOMAIN_DISPMIX>;
731 clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
732 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
733 assigned-clocks = <&clk IMX8MM_CLK_DISP_AXI>,
734 <&clk IMX8MM_CLK_DISP_APB>;
735 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
736 <&clk IMX8MM_SYS_PLL1_800M>;
737 assigned-clock-rates = <500000000>, <200000000>;
740 pgc_mipi: power-domain@11 {
741 #power-domain-cells = <0>;
742 reg = <IMX8MM_POWER_DOMAIN_MIPI>;
748 aips2: bus@30400000 {
749 compatible = "fsl,aips-bus", "simple-bus";
750 reg = <0x30400000 0x400000>;
751 #address-cells = <1>;
753 ranges = <0x30400000 0x30400000 0x400000>;
756 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
757 reg = <0x30660000 0x10000>;
758 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
759 clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
760 <&clk IMX8MM_CLK_PWM1_ROOT>;
761 clock-names = "ipg", "per";
767 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
768 reg = <0x30670000 0x10000>;
769 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
770 clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
771 <&clk IMX8MM_CLK_PWM2_ROOT>;
772 clock-names = "ipg", "per";
778 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
779 reg = <0x30680000 0x10000>;
780 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
781 clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
782 <&clk IMX8MM_CLK_PWM3_ROOT>;
783 clock-names = "ipg", "per";
789 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
790 reg = <0x30690000 0x10000>;
791 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
793 <&clk IMX8MM_CLK_PWM4_ROOT>;
794 clock-names = "ipg", "per";
799 system_counter: timer@306a0000 {
800 compatible = "nxp,sysctr-timer";
801 reg = <0x306a0000 0x20000>;
802 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
808 aips3: bus@30800000 {
809 compatible = "fsl,aips-bus", "simple-bus";
810 reg = <0x30800000 0x400000>;
811 #address-cells = <1>;
813 ranges = <0x30800000 0x30800000 0x400000>,
814 <0x8000000 0x8000000 0x10000000>;
816 spba1: spba-bus@30800000 {
817 compatible = "fsl,spba-bus", "simple-bus";
818 #address-cells = <1>;
820 reg = <0x30800000 0x100000>;
823 ecspi1: spi@30820000 {
824 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
825 #address-cells = <1>;
827 reg = <0x30820000 0x10000>;
828 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
829 clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
830 <&clk IMX8MM_CLK_ECSPI1_ROOT>;
831 clock-names = "ipg", "per";
832 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
833 dma-names = "rx", "tx";
837 ecspi2: spi@30830000 {
838 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
839 #address-cells = <1>;
841 reg = <0x30830000 0x10000>;
842 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
843 clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
844 <&clk IMX8MM_CLK_ECSPI2_ROOT>;
845 clock-names = "ipg", "per";
846 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
847 dma-names = "rx", "tx";
851 ecspi3: spi@30840000 {
852 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
853 #address-cells = <1>;
855 reg = <0x30840000 0x10000>;
856 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
857 clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
858 <&clk IMX8MM_CLK_ECSPI3_ROOT>;
859 clock-names = "ipg", "per";
860 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
861 dma-names = "rx", "tx";
865 uart1: serial@30860000 {
866 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
867 reg = <0x30860000 0x10000>;
868 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
869 clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
870 <&clk IMX8MM_CLK_UART1_ROOT>;
871 clock-names = "ipg", "per";
872 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
873 dma-names = "rx", "tx";
877 uart3: serial@30880000 {
878 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
879 reg = <0x30880000 0x10000>;
880 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
881 clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
882 <&clk IMX8MM_CLK_UART3_ROOT>;
883 clock-names = "ipg", "per";
884 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
885 dma-names = "rx", "tx";
889 uart2: serial@30890000 {
890 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
891 reg = <0x30890000 0x10000>;
892 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
893 clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
894 <&clk IMX8MM_CLK_UART2_ROOT>;
895 clock-names = "ipg", "per";
900 crypto: crypto@30900000 {
901 compatible = "fsl,sec-v4.0";
902 #address-cells = <1>;
904 reg = <0x30900000 0x40000>;
905 ranges = <0 0x30900000 0x40000>;
906 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
907 clocks = <&clk IMX8MM_CLK_AHB>,
908 <&clk IMX8MM_CLK_IPG_ROOT>;
909 clock-names = "aclk", "ipg";
912 compatible = "fsl,sec-v4.0-job-ring";
913 reg = <0x1000 0x1000>;
914 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
918 compatible = "fsl,sec-v4.0-job-ring";
919 reg = <0x2000 0x1000>;
920 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
924 compatible = "fsl,sec-v4.0-job-ring";
925 reg = <0x3000 0x1000>;
926 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
931 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
932 #address-cells = <1>;
934 reg = <0x30a20000 0x10000>;
935 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
936 clocks = <&clk IMX8MM_CLK_I2C1_ROOT>;
941 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
942 #address-cells = <1>;
944 reg = <0x30a30000 0x10000>;
945 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
946 clocks = <&clk IMX8MM_CLK_I2C2_ROOT>;
951 #address-cells = <1>;
953 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
954 reg = <0x30a40000 0x10000>;
955 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
956 clocks = <&clk IMX8MM_CLK_I2C3_ROOT>;
961 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
962 #address-cells = <1>;
964 reg = <0x30a50000 0x10000>;
965 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
966 clocks = <&clk IMX8MM_CLK_I2C4_ROOT>;
970 uart4: serial@30a60000 {
971 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
972 reg = <0x30a60000 0x10000>;
973 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
974 clocks = <&clk IMX8MM_CLK_UART4_ROOT>,
975 <&clk IMX8MM_CLK_UART4_ROOT>;
976 clock-names = "ipg", "per";
977 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
978 dma-names = "rx", "tx";
982 mu: mailbox@30aa0000 {
983 compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
984 reg = <0x30aa0000 0x10000>;
985 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
986 clocks = <&clk IMX8MM_CLK_MU_ROOT>;
990 usdhc1: mmc@30b40000 {
991 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
992 reg = <0x30b40000 0x10000>;
993 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
994 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
995 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
996 <&clk IMX8MM_CLK_USDHC1_ROOT>;
997 clock-names = "ipg", "ahb", "per";
998 fsl,tuning-start-tap = <20>;
999 fsl,tuning-step= <2>;
1001 status = "disabled";
1004 usdhc2: mmc@30b50000 {
1005 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1006 reg = <0x30b50000 0x10000>;
1007 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1008 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
1009 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
1010 <&clk IMX8MM_CLK_USDHC2_ROOT>;
1011 clock-names = "ipg", "ahb", "per";
1012 fsl,tuning-start-tap = <20>;
1013 fsl,tuning-step= <2>;
1015 status = "disabled";
1018 usdhc3: mmc@30b60000 {
1019 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1020 reg = <0x30b60000 0x10000>;
1021 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1022 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
1023 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
1024 <&clk IMX8MM_CLK_USDHC3_ROOT>;
1025 clock-names = "ipg", "ahb", "per";
1026 fsl,tuning-start-tap = <20>;
1027 fsl,tuning-step= <2>;
1029 status = "disabled";
1032 flexspi: spi@30bb0000 {
1033 #address-cells = <1>;
1035 compatible = "nxp,imx8mm-fspi";
1036 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
1037 reg-names = "fspi_base", "fspi_mmap";
1038 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1039 clocks = <&clk IMX8MM_CLK_QSPI_ROOT>,
1040 <&clk IMX8MM_CLK_QSPI_ROOT>;
1041 clock-names = "fspi_en", "fspi";
1042 status = "disabled";
1045 sdma1: dma-controller@30bd0000 {
1046 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
1047 reg = <0x30bd0000 0x10000>;
1048 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1049 clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
1050 <&clk IMX8MM_CLK_AHB>;
1051 clock-names = "ipg", "ahb";
1053 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1056 fec1: ethernet@30be0000 {
1057 compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1058 reg = <0x30be0000 0x10000>;
1059 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1060 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1061 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1062 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1063 clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
1064 <&clk IMX8MM_CLK_ENET1_ROOT>,
1065 <&clk IMX8MM_CLK_ENET_TIMER>,
1066 <&clk IMX8MM_CLK_ENET_REF>,
1067 <&clk IMX8MM_CLK_ENET_PHY_REF>;
1068 clock-names = "ipg", "ahb", "ptp",
1069 "enet_clk_ref", "enet_out";
1070 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
1071 <&clk IMX8MM_CLK_ENET_TIMER>,
1072 <&clk IMX8MM_CLK_ENET_REF>,
1073 <&clk IMX8MM_CLK_ENET_PHY_REF>;
1074 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
1075 <&clk IMX8MM_SYS_PLL2_100M>,
1076 <&clk IMX8MM_SYS_PLL2_125M>,
1077 <&clk IMX8MM_SYS_PLL2_50M>;
1078 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1079 fsl,num-tx-queues = <3>;
1080 fsl,num-rx-queues = <3>;
1081 nvmem-cells = <&fec_mac_address>;
1082 nvmem-cell-names = "mac-address";
1083 fsl,stop-mode = <&gpr 0x10 3>;
1084 status = "disabled";
1089 aips4: bus@32c00000 {
1090 compatible = "fsl,aips-bus", "simple-bus";
1091 reg = <0x32c00000 0x400000>;
1092 #address-cells = <1>;
1094 ranges = <0x32c00000 0x32c00000 0x400000>;
1097 compatible = "fsl,imx8mm-csi", "fsl,imx7-csi";
1098 reg = <0x32e20000 0x1000>;
1099 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1100 clocks = <&clk IMX8MM_CLK_CSI1_ROOT>;
1101 clock-names = "mclk";
1102 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_CSI_BRIDGE>;
1103 status = "disabled";
1107 remote-endpoint = <&imx8mm_mipi_csi_out>;
1112 disp_blk_ctrl: blk-ctrl@32e28000 {
1113 compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
1114 reg = <0x32e28000 0x100>;
1115 power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
1116 <&pgc_dispmix>, <&pgc_mipi>,
1118 power-domain-names = "bus", "csi-bridge",
1119 "lcdif", "mipi-dsi",
1121 clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
1122 <&clk IMX8MM_CLK_DISP_APB_ROOT>,
1123 <&clk IMX8MM_CLK_CSI1_ROOT>,
1124 <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
1125 <&clk IMX8MM_CLK_DISP_APB_ROOT>,
1126 <&clk IMX8MM_CLK_DISP_ROOT>,
1127 <&clk IMX8MM_CLK_DSI_CORE>,
1128 <&clk IMX8MM_CLK_DSI_PHY_REF>,
1129 <&clk IMX8MM_CLK_CSI1_CORE>,
1130 <&clk IMX8MM_CLK_CSI1_PHY_REF>;
1131 clock-names = "csi-bridge-axi","csi-bridge-apb",
1132 "csi-bridge-core", "lcdif-axi",
1133 "lcdif-apb", "lcdif-pix",
1134 "dsi-pclk", "dsi-ref",
1135 "csi-aclk", "csi-pclk";
1136 #power-domain-cells = <1>;
1139 mipi_csi: mipi-csi@32e30000 {
1140 compatible = "fsl,imx8mm-mipi-csi2";
1141 reg = <0x32e30000 0x1000>;
1142 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1143 assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>,
1144 <&clk IMX8MM_CLK_CSI1_PHY_REF>;
1145 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
1146 <&clk IMX8MM_SYS_PLL2_1000M>;
1147 clock-frequency = <333000000>;
1148 clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
1149 <&clk IMX8MM_CLK_CSI1_ROOT>,
1150 <&clk IMX8MM_CLK_CSI1_PHY_REF>,
1151 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
1152 clock-names = "pclk", "wrap", "phy", "axi";
1153 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_CSI>;
1154 status = "disabled";
1157 #address-cells = <1>;
1167 imx8mm_mipi_csi_out: endpoint {
1168 remote-endpoint = <&csi_in>;
1174 usbotg1: usb@32e40000 {
1175 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
1176 reg = <0x32e40000 0x200>;
1177 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1178 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
1179 clock-names = "usb1_ctrl_root_clk";
1180 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
1181 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
1182 phys = <&usbphynop1>;
1183 fsl,usbmisc = <&usbmisc1 0>;
1184 power-domains = <&pgc_otg1>;
1185 status = "disabled";
1188 usbmisc1: usbmisc@32e40200 {
1189 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
1191 reg = <0x32e40200 0x200>;
1194 usbotg2: usb@32e50000 {
1195 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
1196 reg = <0x32e50000 0x200>;
1197 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1198 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
1199 clock-names = "usb1_ctrl_root_clk";
1200 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
1201 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
1202 phys = <&usbphynop2>;
1203 fsl,usbmisc = <&usbmisc2 0>;
1204 power-domains = <&pgc_otg2>;
1205 status = "disabled";
1208 usbmisc2: usbmisc@32e50200 {
1209 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
1211 reg = <0x32e50200 0x200>;
1216 dma_apbh: dma-controller@33000000 {
1217 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1218 reg = <0x33000000 0x2000>;
1219 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1220 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1221 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1222 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1223 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1226 clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1229 gpmi: nand-controller@33002000{
1230 compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
1231 #address-cells = <1>;
1233 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1234 reg-names = "gpmi-nand", "bch";
1235 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1236 interrupt-names = "bch";
1237 clocks = <&clk IMX8MM_CLK_NAND_ROOT>,
1238 <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1239 clock-names = "gpmi_io", "gpmi_bch_apb";
1240 dmas = <&dma_apbh 0>;
1241 dma-names = "rx-tx";
1242 status = "disabled";
1245 gpu_3d: gpu@38000000 {
1246 compatible = "vivante,gc";
1247 reg = <0x38000000 0x8000>;
1248 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1249 clocks = <&clk IMX8MM_CLK_GPU_AHB>,
1250 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
1251 <&clk IMX8MM_CLK_GPU3D_ROOT>,
1252 <&clk IMX8MM_CLK_GPU3D_ROOT>;
1253 clock-names = "reg", "bus", "core", "shader";
1254 assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
1255 <&clk IMX8MM_GPU_PLL_OUT>;
1256 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
1257 assigned-clock-rates = <0>, <1000000000>;
1258 power-domains = <&pgc_gpu>;
1261 gpu_2d: gpu@38008000 {
1262 compatible = "vivante,gc";
1263 reg = <0x38008000 0x8000>;
1264 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1265 clocks = <&clk IMX8MM_CLK_GPU_AHB>,
1266 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
1267 <&clk IMX8MM_CLK_GPU2D_ROOT>;
1268 clock-names = "reg", "bus", "core";
1269 assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
1270 <&clk IMX8MM_GPU_PLL_OUT>;
1271 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
1272 assigned-clock-rates = <0>, <1000000000>;
1273 power-domains = <&pgc_gpu>;
1276 vpu_blk_ctrl: blk-ctrl@38330000 {
1277 compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
1278 reg = <0x38330000 0x100>;
1279 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
1280 <&pgc_vpu_g2>, <&pgc_vpu_h1>;
1281 power-domain-names = "bus", "g1", "g2", "h1";
1282 clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>,
1283 <&clk IMX8MM_CLK_VPU_G2_ROOT>,
1284 <&clk IMX8MM_CLK_VPU_H1_ROOT>;
1285 clock-names = "g1", "g2", "h1";
1286 #power-domain-cells = <1>;
1289 gic: interrupt-controller@38800000 {
1290 compatible = "arm,gic-v3";
1291 reg = <0x38800000 0x10000>, /* GIC Dist */
1292 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
1293 #interrupt-cells = <3>;
1294 interrupt-controller;
1295 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1298 ddrc: memory-controller@3d400000 {
1299 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
1300 reg = <0x3d400000 0x400000>;
1301 clock-names = "core", "pll", "alt", "apb";
1302 clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
1303 <&clk IMX8MM_DRAM_PLL>,
1304 <&clk IMX8MM_CLK_DRAM_ALT>,
1305 <&clk IMX8MM_CLK_DRAM_APB>;
1309 compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
1310 reg = <0x3d800000 0x400000>;
1311 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;