1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mm-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/imx8mm-power.h>
11 #include <dt-bindings/reset/imx8mq-reset.h>
12 #include <dt-bindings/thermal/thermal.h>
14 #include "imx8mm-pinfunc.h"
17 interrupt-parent = <&gic>;
49 entry-method = "psci";
51 cpu_pd_wait: cpu-pd-wait {
52 compatible = "arm,idle-state";
53 arm,psci-suspend-param = <0x0010033>;
55 entry-latency-us = <1000>;
56 exit-latency-us = <700>;
57 min-residency-us = <2700>;
63 compatible = "arm,cortex-a53";
65 clock-latency = <61036>; /* two CLK32 periods */
66 clocks = <&clk IMX8MM_CLK_ARM>;
67 enable-method = "psci";
68 i-cache-size = <0x8000>;
69 i-cache-line-size = <64>;
71 d-cache-size = <0x8000>;
72 d-cache-line-size = <64>;
74 next-level-cache = <&A53_L2>;
75 operating-points-v2 = <&a53_opp_table>;
76 nvmem-cells = <&cpu_speed_grade>;
77 nvmem-cell-names = "speed_grade";
78 cpu-idle-states = <&cpu_pd_wait>;
84 compatible = "arm,cortex-a53";
86 clock-latency = <61036>; /* two CLK32 periods */
87 clocks = <&clk IMX8MM_CLK_ARM>;
88 enable-method = "psci";
89 i-cache-size = <0x8000>;
90 i-cache-line-size = <64>;
92 d-cache-size = <0x8000>;
93 d-cache-line-size = <64>;
95 next-level-cache = <&A53_L2>;
96 operating-points-v2 = <&a53_opp_table>;
97 cpu-idle-states = <&cpu_pd_wait>;
103 compatible = "arm,cortex-a53";
105 clock-latency = <61036>; /* two CLK32 periods */
106 clocks = <&clk IMX8MM_CLK_ARM>;
107 enable-method = "psci";
108 i-cache-size = <0x8000>;
109 i-cache-line-size = <64>;
110 i-cache-sets = <256>;
111 d-cache-size = <0x8000>;
112 d-cache-line-size = <64>;
113 d-cache-sets = <128>;
114 next-level-cache = <&A53_L2>;
115 operating-points-v2 = <&a53_opp_table>;
116 cpu-idle-states = <&cpu_pd_wait>;
117 #cooling-cells = <2>;
122 compatible = "arm,cortex-a53";
124 clock-latency = <61036>; /* two CLK32 periods */
125 clocks = <&clk IMX8MM_CLK_ARM>;
126 enable-method = "psci";
127 i-cache-size = <0x8000>;
128 i-cache-line-size = <64>;
129 i-cache-sets = <256>;
130 d-cache-size = <0x8000>;
131 d-cache-line-size = <64>;
132 d-cache-sets = <128>;
133 next-level-cache = <&A53_L2>;
134 operating-points-v2 = <&a53_opp_table>;
135 cpu-idle-states = <&cpu_pd_wait>;
136 #cooling-cells = <2>;
140 compatible = "cache";
143 cache-size = <0x80000>;
144 cache-line-size = <64>;
149 a53_opp_table: opp-table {
150 compatible = "operating-points-v2";
154 opp-hz = /bits/ 64 <1200000000>;
155 opp-microvolt = <850000>;
156 opp-supported-hw = <0xe>, <0x7>;
157 clock-latency-ns = <150000>;
162 opp-hz = /bits/ 64 <1600000000>;
163 opp-microvolt = <950000>;
164 opp-supported-hw = <0xc>, <0x7>;
165 clock-latency-ns = <150000>;
170 opp-hz = /bits/ 64 <1800000000>;
171 opp-microvolt = <1000000>;
172 opp-supported-hw = <0x8>, <0x3>;
173 clock-latency-ns = <150000>;
178 osc_32k: clock-osc-32k {
179 compatible = "fixed-clock";
181 clock-frequency = <32768>;
182 clock-output-names = "osc_32k";
185 osc_24m: clock-osc-24m {
186 compatible = "fixed-clock";
188 clock-frequency = <24000000>;
189 clock-output-names = "osc_24m";
192 clk_ext1: clock-ext1 {
193 compatible = "fixed-clock";
195 clock-frequency = <133000000>;
196 clock-output-names = "clk_ext1";
199 clk_ext2: clock-ext2 {
200 compatible = "fixed-clock";
202 clock-frequency = <133000000>;
203 clock-output-names = "clk_ext2";
206 clk_ext3: clock-ext3 {
207 compatible = "fixed-clock";
209 clock-frequency = <133000000>;
210 clock-output-names = "clk_ext3";
213 clk_ext4: clock-ext4 {
214 compatible = "fixed-clock";
216 clock-frequency = <133000000>;
217 clock-output-names = "clk_ext4";
221 compatible = "arm,psci-1.0";
226 compatible = "arm,cortex-a53-pmu";
227 interrupts = <GIC_PPI 7
228 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
232 compatible = "arm,armv8-timer";
233 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
234 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
235 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
236 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
237 clock-frequency = <8000000>;
238 arm,no-tick-in-suspend;
243 polling-delay-passive = <250>;
244 polling-delay = <2000>;
245 thermal-sensors = <&tmu>;
248 temperature = <85000>;
254 temperature = <95000>;
262 trip = <&cpu_alert0>;
264 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
265 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
266 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
267 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
273 usbphynop1: usbphynop1 {
275 compatible = "usb-nop-xceiv";
276 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
277 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
278 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
279 clock-names = "main_clk";
280 power-domains = <&pgc_otg1>;
283 usbphynop2: usbphynop2 {
285 compatible = "usb-nop-xceiv";
286 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
287 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
288 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
289 clock-names = "main_clk";
290 power-domains = <&pgc_otg2>;
294 compatible = "fsl,imx8mm-soc", "simple-bus";
295 #address-cells = <1>;
297 ranges = <0x0 0x0 0x0 0x3e000000>;
298 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
299 nvmem-cells = <&imx8mm_uid>;
300 nvmem-cell-names = "soc_unique_id";
302 aips1: bus@30000000 {
303 compatible = "fsl,aips-bus", "simple-bus";
304 reg = <0x30000000 0x400000>;
305 #address-cells = <1>;
307 ranges = <0x30000000 0x30000000 0x400000>;
309 spba2: spba-bus@30000000 {
310 compatible = "fsl,spba-bus", "simple-bus";
311 #address-cells = <1>;
313 reg = <0x30000000 0x100000>;
317 #sound-dai-cells = <0>;
318 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
319 reg = <0x30010000 0x10000>;
320 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
321 clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
322 <&clk IMX8MM_CLK_SAI1_ROOT>,
323 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
324 clock-names = "bus", "mclk1", "mclk2", "mclk3";
325 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
326 dma-names = "rx", "tx";
331 #sound-dai-cells = <0>;
332 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
333 reg = <0x30020000 0x10000>;
334 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
336 <&clk IMX8MM_CLK_SAI2_ROOT>,
337 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
338 clock-names = "bus", "mclk1", "mclk2", "mclk3";
339 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
340 dma-names = "rx", "tx";
345 #sound-dai-cells = <0>;
346 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
347 reg = <0x30030000 0x10000>;
348 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
350 <&clk IMX8MM_CLK_SAI3_ROOT>,
351 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
352 clock-names = "bus", "mclk1", "mclk2", "mclk3";
353 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
354 dma-names = "rx", "tx";
359 #sound-dai-cells = <0>;
360 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
361 reg = <0x30050000 0x10000>;
362 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
363 clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
364 <&clk IMX8MM_CLK_SAI5_ROOT>,
365 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
366 clock-names = "bus", "mclk1", "mclk2", "mclk3";
367 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
368 dma-names = "rx", "tx";
373 #sound-dai-cells = <0>;
374 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
375 reg = <0x30060000 0x10000>;
376 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
378 <&clk IMX8MM_CLK_SAI6_ROOT>,
379 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
380 clock-names = "bus", "mclk1", "mclk2", "mclk3";
381 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
382 dma-names = "rx", "tx";
386 micfil: audio-controller@30080000 {
387 compatible = "fsl,imx8mm-micfil";
388 reg = <0x30080000 0x10000>;
389 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
390 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
391 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
392 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&clk IMX8MM_CLK_PDM_IPG>,
394 <&clk IMX8MM_CLK_PDM_ROOT>,
395 <&clk IMX8MM_AUDIO_PLL1_OUT>,
396 <&clk IMX8MM_AUDIO_PLL2_OUT>,
397 <&clk IMX8MM_CLK_EXT3>;
398 clock-names = "ipg_clk", "ipg_clk_app",
399 "pll8k", "pll11k", "clkext3";
400 dmas = <&sdma2 24 25 0x80000000>;
405 spdif1: spdif@30090000 {
406 compatible = "fsl,imx35-spdif";
407 reg = <0x30090000 0x10000>;
408 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
409 clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */
410 <&clk IMX8MM_CLK_24M>, /* rxtx0 */
411 <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */
412 <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */
413 <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */
414 <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */
415 <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */
416 <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */
417 <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */
418 <&clk IMX8MM_CLK_DUMMY>; /* spba */
419 clock-names = "core", "rxtx0",
424 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
425 dma-names = "rx", "tx";
430 gpio1: gpio@30200000 {
431 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
432 reg = <0x30200000 0x10000>;
433 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
434 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>;
438 interrupt-controller;
439 #interrupt-cells = <2>;
440 gpio-ranges = <&iomuxc 0 10 30>;
443 gpio2: gpio@30210000 {
444 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
445 reg = <0x30210000 0x10000>;
446 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
447 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>;
451 interrupt-controller;
452 #interrupt-cells = <2>;
453 gpio-ranges = <&iomuxc 0 40 21>;
456 gpio3: gpio@30220000 {
457 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
458 reg = <0x30220000 0x10000>;
459 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
461 clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>;
464 interrupt-controller;
465 #interrupt-cells = <2>;
466 gpio-ranges = <&iomuxc 0 61 26>;
469 gpio4: gpio@30230000 {
470 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
471 reg = <0x30230000 0x10000>;
472 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>;
477 interrupt-controller;
478 #interrupt-cells = <2>;
479 gpio-ranges = <&iomuxc 0 87 32>;
482 gpio5: gpio@30240000 {
483 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
484 reg = <0x30240000 0x10000>;
485 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
486 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
487 clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>;
490 interrupt-controller;
491 #interrupt-cells = <2>;
492 gpio-ranges = <&iomuxc 0 119 30>;
496 compatible = "fsl,imx8mm-tmu";
497 reg = <0x30260000 0x10000>;
498 clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
499 #thermal-sensor-cells = <0>;
502 wdog1: watchdog@30280000 {
503 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
504 reg = <0x30280000 0x10000>;
505 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>;
510 wdog2: watchdog@30290000 {
511 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
512 reg = <0x30290000 0x10000>;
513 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>;
518 wdog3: watchdog@302a0000 {
519 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
520 reg = <0x302a0000 0x10000>;
521 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>;
526 sdma2: dma-controller@302c0000 {
527 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
528 reg = <0x302c0000 0x10000>;
529 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
531 <&clk IMX8MM_CLK_SDMA2_ROOT>;
532 clock-names = "ipg", "ahb";
534 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
537 sdma3: dma-controller@302b0000 {
538 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
539 reg = <0x302b0000 0x10000>;
540 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
541 clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
542 <&clk IMX8MM_CLK_SDMA3_ROOT>;
543 clock-names = "ipg", "ahb";
545 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
548 iomuxc: pinctrl@30330000 {
549 compatible = "fsl,imx8mm-iomuxc";
550 reg = <0x30330000 0x10000>;
553 gpr: iomuxc-gpr@30340000 {
554 compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
555 reg = <0x30340000 0x10000>;
558 ocotp: efuse@30350000 {
559 compatible = "fsl,imx8mm-ocotp", "syscon";
560 reg = <0x30350000 0x10000>;
561 clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
562 /* For nvmem subnodes */
563 #address-cells = <1>;
566 imx8mm_uid: unique-id@4 {
570 cpu_speed_grade: speed-grade@10 {
574 fec_mac_address: mac-address@90 {
579 anatop: clock-controller@30360000 {
580 compatible = "fsl,imx8mm-anatop";
581 reg = <0x30360000 0x10000>;
585 snvs: snvs@30370000 {
586 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
587 reg = <0x30370000 0x10000>;
589 snvs_rtc: snvs-rtc-lp {
590 compatible = "fsl,sec-v4.0-mon-rtc-lp";
593 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
595 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
596 clock-names = "snvs-rtc";
599 snvs_pwrkey: snvs-powerkey {
600 compatible = "fsl,sec-v4.0-pwrkey";
602 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
604 clock-names = "snvs-pwrkey";
605 linux,keycode = <KEY_POWER>;
610 snvs_lpgpr: snvs-lpgpr {
611 compatible = "fsl,imx8mm-snvs-lpgpr",
612 "fsl,imx7d-snvs-lpgpr";
616 clk: clock-controller@30380000 {
617 compatible = "fsl,imx8mm-ccm";
618 reg = <0x30380000 0x10000>;
620 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
621 <&clk_ext3>, <&clk_ext4>;
622 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
623 "clk_ext3", "clk_ext4";
624 assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>,
625 <&clk IMX8MM_CLK_A53_CORE>,
626 <&clk IMX8MM_CLK_NOC>,
627 <&clk IMX8MM_CLK_AUDIO_AHB>,
628 <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
629 <&clk IMX8MM_SYS_PLL3>,
630 <&clk IMX8MM_VIDEO_PLL1>,
631 <&clk IMX8MM_AUDIO_PLL1>;
632 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
633 <&clk IMX8MM_ARM_PLL_OUT>,
634 <&clk IMX8MM_SYS_PLL3_OUT>,
635 <&clk IMX8MM_SYS_PLL1_800M>;
636 assigned-clock-rates = <0>, <0>, <0>,
644 src: reset-controller@30390000 {
645 compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon";
646 reg = <0x30390000 0x10000>;
647 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
652 compatible = "fsl,imx8mm-gpc";
653 reg = <0x303a0000 0x10000>;
654 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
655 interrupt-parent = <&gic>;
656 interrupt-controller;
657 #interrupt-cells = <3>;
660 #address-cells = <1>;
663 pgc_hsiomix: power-domain@0 {
664 #power-domain-cells = <0>;
665 reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>;
666 clocks = <&clk IMX8MM_CLK_USB_BUS>;
667 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
668 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
671 pgc_pcie: power-domain@1 {
672 #power-domain-cells = <0>;
673 reg = <IMX8MM_POWER_DOMAIN_PCIE>;
674 power-domains = <&pgc_hsiomix>;
675 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>;
678 pgc_otg1: power-domain@2 {
679 #power-domain-cells = <0>;
680 reg = <IMX8MM_POWER_DOMAIN_OTG1>;
683 pgc_otg2: power-domain@3 {
684 #power-domain-cells = <0>;
685 reg = <IMX8MM_POWER_DOMAIN_OTG2>;
688 pgc_gpumix: power-domain@4 {
689 #power-domain-cells = <0>;
690 reg = <IMX8MM_POWER_DOMAIN_GPUMIX>;
691 clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
692 <&clk IMX8MM_CLK_GPU_AHB>;
693 assigned-clocks = <&clk IMX8MM_CLK_GPU_AXI>,
694 <&clk IMX8MM_CLK_GPU_AHB>;
695 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
696 <&clk IMX8MM_SYS_PLL1_800M>;
697 assigned-clock-rates = <800000000>, <400000000>;
700 pgc_gpu: power-domain@5 {
701 #power-domain-cells = <0>;
702 reg = <IMX8MM_POWER_DOMAIN_GPU>;
703 clocks = <&clk IMX8MM_CLK_GPU_AHB>,
704 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
705 <&clk IMX8MM_CLK_GPU2D_ROOT>,
706 <&clk IMX8MM_CLK_GPU3D_ROOT>;
707 resets = <&src IMX8MQ_RESET_GPU_RESET>;
708 power-domains = <&pgc_gpumix>;
711 pgc_vpumix: power-domain@6 {
712 #power-domain-cells = <0>;
713 reg = <IMX8MM_POWER_DOMAIN_VPUMIX>;
714 clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
715 assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>;
716 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>;
719 pgc_vpu_g1: power-domain@7 {
720 #power-domain-cells = <0>;
721 reg = <IMX8MM_POWER_DOMAIN_VPUG1>;
724 pgc_vpu_g2: power-domain@8 {
725 #power-domain-cells = <0>;
726 reg = <IMX8MM_POWER_DOMAIN_VPUG2>;
729 pgc_vpu_h1: power-domain@9 {
730 #power-domain-cells = <0>;
731 reg = <IMX8MM_POWER_DOMAIN_VPUH1>;
734 pgc_dispmix: power-domain@10 {
735 #power-domain-cells = <0>;
736 reg = <IMX8MM_POWER_DOMAIN_DISPMIX>;
737 clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
738 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
739 assigned-clocks = <&clk IMX8MM_CLK_DISP_AXI>,
740 <&clk IMX8MM_CLK_DISP_APB>;
741 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
742 <&clk IMX8MM_SYS_PLL1_800M>;
743 assigned-clock-rates = <500000000>, <200000000>;
746 pgc_mipi: power-domain@11 {
747 #power-domain-cells = <0>;
748 reg = <IMX8MM_POWER_DOMAIN_MIPI>;
754 aips2: bus@30400000 {
755 compatible = "fsl,aips-bus", "simple-bus";
756 reg = <0x30400000 0x400000>;
757 #address-cells = <1>;
759 ranges = <0x30400000 0x30400000 0x400000>;
762 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
763 reg = <0x30660000 0x10000>;
764 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
765 clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
766 <&clk IMX8MM_CLK_PWM1_ROOT>;
767 clock-names = "ipg", "per";
773 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
774 reg = <0x30670000 0x10000>;
775 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
776 clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
777 <&clk IMX8MM_CLK_PWM2_ROOT>;
778 clock-names = "ipg", "per";
784 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
785 reg = <0x30680000 0x10000>;
786 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
787 clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
788 <&clk IMX8MM_CLK_PWM3_ROOT>;
789 clock-names = "ipg", "per";
795 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
796 reg = <0x30690000 0x10000>;
797 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
798 clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
799 <&clk IMX8MM_CLK_PWM4_ROOT>;
800 clock-names = "ipg", "per";
805 system_counter: timer@306a0000 {
806 compatible = "nxp,sysctr-timer";
807 reg = <0x306a0000 0x20000>;
808 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
814 aips3: bus@30800000 {
815 compatible = "fsl,aips-bus", "simple-bus";
816 reg = <0x30800000 0x400000>;
817 #address-cells = <1>;
819 ranges = <0x30800000 0x30800000 0x400000>,
820 <0x8000000 0x8000000 0x10000000>;
822 spba1: spba-bus@30800000 {
823 compatible = "fsl,spba-bus", "simple-bus";
824 #address-cells = <1>;
826 reg = <0x30800000 0x100000>;
829 ecspi1: spi@30820000 {
830 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
831 #address-cells = <1>;
833 reg = <0x30820000 0x10000>;
834 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
835 clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
836 <&clk IMX8MM_CLK_ECSPI1_ROOT>;
837 clock-names = "ipg", "per";
838 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
839 dma-names = "rx", "tx";
843 ecspi2: spi@30830000 {
844 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
845 #address-cells = <1>;
847 reg = <0x30830000 0x10000>;
848 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
849 clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
850 <&clk IMX8MM_CLK_ECSPI2_ROOT>;
851 clock-names = "ipg", "per";
852 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
853 dma-names = "rx", "tx";
857 ecspi3: spi@30840000 {
858 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
859 #address-cells = <1>;
861 reg = <0x30840000 0x10000>;
862 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
863 clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
864 <&clk IMX8MM_CLK_ECSPI3_ROOT>;
865 clock-names = "ipg", "per";
866 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
867 dma-names = "rx", "tx";
871 uart1: serial@30860000 {
872 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
873 reg = <0x30860000 0x10000>;
874 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
875 clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
876 <&clk IMX8MM_CLK_UART1_ROOT>;
877 clock-names = "ipg", "per";
878 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
879 dma-names = "rx", "tx";
883 uart3: serial@30880000 {
884 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
885 reg = <0x30880000 0x10000>;
886 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
887 clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
888 <&clk IMX8MM_CLK_UART3_ROOT>;
889 clock-names = "ipg", "per";
890 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
891 dma-names = "rx", "tx";
895 uart2: serial@30890000 {
896 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
897 reg = <0x30890000 0x10000>;
898 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
899 clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
900 <&clk IMX8MM_CLK_UART2_ROOT>;
901 clock-names = "ipg", "per";
906 crypto: crypto@30900000 {
907 compatible = "fsl,sec-v4.0";
908 #address-cells = <1>;
910 reg = <0x30900000 0x40000>;
911 ranges = <0 0x30900000 0x40000>;
912 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
913 clocks = <&clk IMX8MM_CLK_AHB>,
914 <&clk IMX8MM_CLK_IPG_ROOT>;
915 clock-names = "aclk", "ipg";
918 compatible = "fsl,sec-v4.0-job-ring";
919 reg = <0x1000 0x1000>;
920 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
925 compatible = "fsl,sec-v4.0-job-ring";
926 reg = <0x2000 0x1000>;
927 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
931 compatible = "fsl,sec-v4.0-job-ring";
932 reg = <0x3000 0x1000>;
933 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
938 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
939 #address-cells = <1>;
941 reg = <0x30a20000 0x10000>;
942 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
943 clocks = <&clk IMX8MM_CLK_I2C1_ROOT>;
948 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
949 #address-cells = <1>;
951 reg = <0x30a30000 0x10000>;
952 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
953 clocks = <&clk IMX8MM_CLK_I2C2_ROOT>;
958 #address-cells = <1>;
960 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
961 reg = <0x30a40000 0x10000>;
962 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
963 clocks = <&clk IMX8MM_CLK_I2C3_ROOT>;
968 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
969 #address-cells = <1>;
971 reg = <0x30a50000 0x10000>;
972 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
973 clocks = <&clk IMX8MM_CLK_I2C4_ROOT>;
977 uart4: serial@30a60000 {
978 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
979 reg = <0x30a60000 0x10000>;
980 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
981 clocks = <&clk IMX8MM_CLK_UART4_ROOT>,
982 <&clk IMX8MM_CLK_UART4_ROOT>;
983 clock-names = "ipg", "per";
984 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
985 dma-names = "rx", "tx";
989 mu: mailbox@30aa0000 {
990 compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
991 reg = <0x30aa0000 0x10000>;
992 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
993 clocks = <&clk IMX8MM_CLK_MU_ROOT>;
997 usdhc1: mmc@30b40000 {
998 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
999 reg = <0x30b40000 0x10000>;
1000 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1001 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
1002 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
1003 <&clk IMX8MM_CLK_USDHC1_ROOT>;
1004 clock-names = "ipg", "ahb", "per";
1005 fsl,tuning-start-tap = <20>;
1006 fsl,tuning-step = <2>;
1008 status = "disabled";
1011 usdhc2: mmc@30b50000 {
1012 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1013 reg = <0x30b50000 0x10000>;
1014 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1015 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
1016 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
1017 <&clk IMX8MM_CLK_USDHC2_ROOT>;
1018 clock-names = "ipg", "ahb", "per";
1019 fsl,tuning-start-tap = <20>;
1020 fsl,tuning-step = <2>;
1022 status = "disabled";
1025 usdhc3: mmc@30b60000 {
1026 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1027 reg = <0x30b60000 0x10000>;
1028 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1029 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
1030 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
1031 <&clk IMX8MM_CLK_USDHC3_ROOT>;
1032 clock-names = "ipg", "ahb", "per";
1033 fsl,tuning-start-tap = <20>;
1034 fsl,tuning-step = <2>;
1036 status = "disabled";
1039 flexspi: spi@30bb0000 {
1040 #address-cells = <1>;
1042 compatible = "nxp,imx8mm-fspi";
1043 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
1044 reg-names = "fspi_base", "fspi_mmap";
1045 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1046 clocks = <&clk IMX8MM_CLK_QSPI_ROOT>,
1047 <&clk IMX8MM_CLK_QSPI_ROOT>;
1048 clock-names = "fspi_en", "fspi";
1049 status = "disabled";
1052 sdma1: dma-controller@30bd0000 {
1053 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
1054 reg = <0x30bd0000 0x10000>;
1055 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1056 clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
1057 <&clk IMX8MM_CLK_AHB>;
1058 clock-names = "ipg", "ahb";
1060 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1063 fec1: ethernet@30be0000 {
1064 compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1065 reg = <0x30be0000 0x10000>;
1066 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1067 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1068 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1069 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1070 clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
1071 <&clk IMX8MM_CLK_ENET1_ROOT>,
1072 <&clk IMX8MM_CLK_ENET_TIMER>,
1073 <&clk IMX8MM_CLK_ENET_REF>,
1074 <&clk IMX8MM_CLK_ENET_PHY_REF>;
1075 clock-names = "ipg", "ahb", "ptp",
1076 "enet_clk_ref", "enet_out";
1077 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
1078 <&clk IMX8MM_CLK_ENET_TIMER>,
1079 <&clk IMX8MM_CLK_ENET_REF>,
1080 <&clk IMX8MM_CLK_ENET_PHY_REF>;
1081 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
1082 <&clk IMX8MM_SYS_PLL2_100M>,
1083 <&clk IMX8MM_SYS_PLL2_125M>,
1084 <&clk IMX8MM_SYS_PLL2_50M>;
1085 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1086 fsl,num-tx-queues = <3>;
1087 fsl,num-rx-queues = <3>;
1088 nvmem-cells = <&fec_mac_address>;
1089 nvmem-cell-names = "mac-address";
1090 fsl,stop-mode = <&gpr 0x10 3>;
1091 status = "disabled";
1096 aips4: bus@32c00000 {
1097 compatible = "fsl,aips-bus", "simple-bus";
1098 reg = <0x32c00000 0x400000>;
1099 #address-cells = <1>;
1101 ranges = <0x32c00000 0x32c00000 0x400000>;
1104 compatible = "fsl,imx8mm-csi", "fsl,imx7-csi";
1105 reg = <0x32e20000 0x1000>;
1106 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1107 clocks = <&clk IMX8MM_CLK_CSI1_ROOT>;
1108 clock-names = "mclk";
1109 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_CSI_BRIDGE>;
1110 status = "disabled";
1114 remote-endpoint = <&imx8mm_mipi_csi_out>;
1119 disp_blk_ctrl: blk-ctrl@32e28000 {
1120 compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
1121 reg = <0x32e28000 0x100>;
1122 power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
1123 <&pgc_dispmix>, <&pgc_mipi>,
1125 power-domain-names = "bus", "csi-bridge",
1126 "lcdif", "mipi-dsi",
1128 clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
1129 <&clk IMX8MM_CLK_DISP_APB_ROOT>,
1130 <&clk IMX8MM_CLK_CSI1_ROOT>,
1131 <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
1132 <&clk IMX8MM_CLK_DISP_APB_ROOT>,
1133 <&clk IMX8MM_CLK_DISP_ROOT>,
1134 <&clk IMX8MM_CLK_DSI_CORE>,
1135 <&clk IMX8MM_CLK_DSI_PHY_REF>,
1136 <&clk IMX8MM_CLK_CSI1_CORE>,
1137 <&clk IMX8MM_CLK_CSI1_PHY_REF>;
1138 clock-names = "csi-bridge-axi","csi-bridge-apb",
1139 "csi-bridge-core", "lcdif-axi",
1140 "lcdif-apb", "lcdif-pix",
1141 "dsi-pclk", "dsi-ref",
1142 "csi-aclk", "csi-pclk";
1143 #power-domain-cells = <1>;
1146 mipi_csi: mipi-csi@32e30000 {
1147 compatible = "fsl,imx8mm-mipi-csi2";
1148 reg = <0x32e30000 0x1000>;
1149 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1150 assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>,
1151 <&clk IMX8MM_CLK_CSI1_PHY_REF>;
1152 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
1153 <&clk IMX8MM_SYS_PLL2_1000M>;
1154 clock-frequency = <333000000>;
1155 clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
1156 <&clk IMX8MM_CLK_CSI1_ROOT>,
1157 <&clk IMX8MM_CLK_CSI1_PHY_REF>,
1158 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
1159 clock-names = "pclk", "wrap", "phy", "axi";
1160 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_CSI>;
1161 status = "disabled";
1164 #address-cells = <1>;
1174 imx8mm_mipi_csi_out: endpoint {
1175 remote-endpoint = <&csi_in>;
1181 usbotg1: usb@32e40000 {
1182 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
1183 reg = <0x32e40000 0x200>;
1184 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1185 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
1186 clock-names = "usb1_ctrl_root_clk";
1187 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
1188 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
1189 phys = <&usbphynop1>;
1190 fsl,usbmisc = <&usbmisc1 0>;
1191 power-domains = <&pgc_hsiomix>;
1192 status = "disabled";
1195 usbmisc1: usbmisc@32e40200 {
1196 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
1198 reg = <0x32e40200 0x200>;
1201 usbotg2: usb@32e50000 {
1202 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
1203 reg = <0x32e50000 0x200>;
1204 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1205 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
1206 clock-names = "usb1_ctrl_root_clk";
1207 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
1208 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
1209 phys = <&usbphynop2>;
1210 fsl,usbmisc = <&usbmisc2 0>;
1211 power-domains = <&pgc_hsiomix>;
1212 status = "disabled";
1215 usbmisc2: usbmisc@32e50200 {
1216 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
1218 reg = <0x32e50200 0x200>;
1221 pcie_phy: pcie-phy@32f00000 {
1222 compatible = "fsl,imx8mm-pcie-phy";
1223 reg = <0x32f00000 0x10000>;
1224 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
1225 clock-names = "ref";
1226 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
1227 assigned-clock-rates = <100000000>;
1228 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
1229 resets = <&src IMX8MQ_RESET_PCIEPHY>;
1230 reset-names = "pciephy";
1232 status = "disabled";
1236 dma_apbh: dma-controller@33000000 {
1237 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1238 reg = <0x33000000 0x2000>;
1239 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1240 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1241 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1242 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1243 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1246 clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1249 gpmi: nand-controller@33002000 {
1250 compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
1251 #address-cells = <1>;
1253 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1254 reg-names = "gpmi-nand", "bch";
1255 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1256 interrupt-names = "bch";
1257 clocks = <&clk IMX8MM_CLK_NAND_ROOT>,
1258 <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1259 clock-names = "gpmi_io", "gpmi_bch_apb";
1260 dmas = <&dma_apbh 0>;
1261 dma-names = "rx-tx";
1262 status = "disabled";
1265 pcie0: pcie@33800000 {
1266 compatible = "fsl,imx8mm-pcie";
1267 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
1268 reg-names = "dbi", "config";
1269 #address-cells = <3>;
1271 device_type = "pci";
1272 bus-range = <0x00 0xff>;
1273 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
1274 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1277 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1278 interrupt-names = "msi";
1279 #interrupt-cells = <1>;
1280 interrupt-map-mask = <0 0 0 0x7>;
1281 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1282 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1283 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1284 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1285 fsl,max-link-speed = <2>;
1286 linux,pci-domain = <0>;
1287 power-domains = <&pgc_pcie>;
1288 resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
1289 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
1290 reset-names = "apps", "turnoff";
1292 phy-names = "pcie-phy";
1293 status = "disabled";
1296 gpu_3d: gpu@38000000 {
1297 compatible = "vivante,gc";
1298 reg = <0x38000000 0x8000>;
1299 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1300 clocks = <&clk IMX8MM_CLK_GPU_AHB>,
1301 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
1302 <&clk IMX8MM_CLK_GPU3D_ROOT>,
1303 <&clk IMX8MM_CLK_GPU3D_ROOT>;
1304 clock-names = "reg", "bus", "core", "shader";
1305 assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
1306 <&clk IMX8MM_GPU_PLL_OUT>;
1307 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
1308 assigned-clock-rates = <0>, <1000000000>;
1309 power-domains = <&pgc_gpu>;
1312 gpu_2d: gpu@38008000 {
1313 compatible = "vivante,gc";
1314 reg = <0x38008000 0x8000>;
1315 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1316 clocks = <&clk IMX8MM_CLK_GPU_AHB>,
1317 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
1318 <&clk IMX8MM_CLK_GPU2D_ROOT>;
1319 clock-names = "reg", "bus", "core";
1320 assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
1321 <&clk IMX8MM_GPU_PLL_OUT>;
1322 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
1323 assigned-clock-rates = <0>, <1000000000>;
1324 power-domains = <&pgc_gpu>;
1327 vpu_g1: video-codec@38300000 {
1328 compatible = "nxp,imx8mm-vpu-g1";
1329 reg = <0x38300000 0x10000>;
1330 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1331 clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>;
1332 power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>;
1335 vpu_g2: video-codec@38310000 {
1336 compatible = "nxp,imx8mq-vpu-g2";
1337 reg = <0x38310000 0x10000>;
1338 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1339 clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>;
1340 power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>;
1343 vpu_blk_ctrl: blk-ctrl@38330000 {
1344 compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
1345 reg = <0x38330000 0x100>;
1346 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
1347 <&pgc_vpu_g2>, <&pgc_vpu_h1>;
1348 power-domain-names = "bus", "g1", "g2", "h1";
1349 clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>,
1350 <&clk IMX8MM_CLK_VPU_G2_ROOT>,
1351 <&clk IMX8MM_CLK_VPU_H1_ROOT>;
1352 clock-names = "g1", "g2", "h1";
1353 assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>,
1354 <&clk IMX8MM_CLK_VPU_G2>;
1355 assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>,
1356 <&clk IMX8MM_VPU_PLL_OUT>;
1357 assigned-clock-rates = <600000000>,
1359 #power-domain-cells = <1>;
1362 gic: interrupt-controller@38800000 {
1363 compatible = "arm,gic-v3";
1364 reg = <0x38800000 0x10000>, /* GIC Dist */
1365 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
1366 #interrupt-cells = <3>;
1367 interrupt-controller;
1368 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1371 ddrc: memory-controller@3d400000 {
1372 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
1373 reg = <0x3d400000 0x400000>;
1374 clock-names = "core", "pll", "alt", "apb";
1375 clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
1376 <&clk IMX8MM_DRAM_PLL>,
1377 <&clk IMX8MM_CLK_DRAM_ALT>,
1378 <&clk IMX8MM_CLK_DRAM_APB>;
1382 compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
1383 reg = <0x3d800000 0x400000>;
1384 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;