arch/arm64/boot/dts/freescale/imx8mm.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <dt-bindings/clock/imx8mm-clock.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/input/input.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/thermal/thermal.h>
  11
  12 #include "imx8mm-pinfunc.h"
  13
  14 / {
  15         interrupt-parent = <&gic>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 ethernet0 = &fec1;
  21                 i2c0 = &i2c1;
  22                 i2c1 = &i2c2;
  23                 i2c2 = &i2c3;
  24                 i2c3 = &i2c4;
  25                 serial0 = &uart1;
  26                 serial1 = &uart2;
  27                 serial2 = &uart3;
  28                 serial3 = &uart4;
  29                 spi0 = &ecspi1;
  30                 spi1 = &ecspi2;
  31                 spi2 = &ecspi3;
  32                 mmc0 = &usdhc1;
  33                 mmc1 = &usdhc2;
  34                 mmc2 = &usdhc3;
  35                 gpio0 = &gpio1;
  36                 gpio1 = &gpio2;
  37                 gpio2 = &gpio3;
  38                 gpio3 = &gpio4;
  39                 gpio4 = &gpio5;
  40         };
  41
  42         cpus {
  43                 #address-cells = <1>;
  44                 #size-cells = <0>;
  45
  46                 idle-states {
  47                         entry-method = "psci";
  48
  49                         cpu_pd_wait: cpu-pd-wait {
  50                                 compatible = "arm,idle-state";
  51                                 arm,psci-suspend-param = <0x0010033>;
  52                                 local-timer-stop;
  53                                 entry-latency-us = <1000>;
  54                                 exit-latency-us = <700>;
  55                                 min-residency-us = <2700>;
  56                         };
  57                 };
  58
  59                 A53_0: cpu@0 {
  60                         device_type = "cpu";
  61                         compatible = "arm,cortex-a53";
  62                         reg = <0x0>;
  63                         clock-latency = <61036>; /* two CLK32 periods */
  64                         clocks = <&clk IMX8MM_CLK_ARM>;
  65                         enable-method = "psci";
  66                         next-level-cache = <&A53_L2>;
  67                         operating-points-v2 = <&a53_opp_table>;
  68                         nvmem-cells = <&cpu_speed_grade>;
  69                         nvmem-cell-names = "speed_grade";
  70                         cpu-idle-states = <&cpu_pd_wait>;
  71                         #cooling-cells = <2>;
  72                 };
  73
  74                 A53_1: cpu@1 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a53";
  77                         reg = <0x1>;
  78                         clock-latency = <61036>; /* two CLK32 periods */
  79                         clocks = <&clk IMX8MM_CLK_ARM>;
  80                         enable-method = "psci";
  81                         next-level-cache = <&A53_L2>;
  82                         operating-points-v2 = <&a53_opp_table>;
  83                         cpu-idle-states = <&cpu_pd_wait>;
  84                         #cooling-cells = <2>;
  85                 };
  86
  87                 A53_2: cpu@2 {
  88                         device_type = "cpu";
  89                         compatible = "arm,cortex-a53";
  90                         reg = <0x2>;
  91                         clock-latency = <61036>; /* two CLK32 periods */
  92                         clocks = <&clk IMX8MM_CLK_ARM>;
  93                         enable-method = "psci";
  94                         next-level-cache = <&A53_L2>;
  95                         operating-points-v2 = <&a53_opp_table>;
  96                         cpu-idle-states = <&cpu_pd_wait>;
  97                         #cooling-cells = <2>;
  98                 };
  99
 100                 A53_3: cpu@3 {
 101                         device_type = "cpu";
 102                         compatible = "arm,cortex-a53";
 103                         reg = <0x3>;
 104                         clock-latency = <61036>; /* two CLK32 periods */
 105                         clocks = <&clk IMX8MM_CLK_ARM>;
 106                         enable-method = "psci";
 107                         next-level-cache = <&A53_L2>;
 108                         operating-points-v2 = <&a53_opp_table>;
 109                         cpu-idle-states = <&cpu_pd_wait>;
 110                         #cooling-cells = <2>;
 111                 };
 112
 113                 A53_L2: l2-cache0 {
 114                         compatible = "cache";
 115                 };
 116         };
 117
 118         a53_opp_table: opp-table {
 119                 compatible = "operating-points-v2";
 120                 opp-shared;
 121
 122                 opp-1200000000 {
 123                         opp-hz = /bits/ 64 <1200000000>;
 124                         opp-microvolt = <850000>;
 125                         opp-supported-hw = <0xe>, <0x7>;
 126                         clock-latency-ns = <150000>;
 127                         opp-suspend;
 128                 };
 129
 130                 opp-1600000000 {
 131                         opp-hz = /bits/ 64 <1600000000>;
 132                         opp-microvolt = <900000>;
 133                         opp-supported-hw = <0xc>, <0x7>;
 134                         clock-latency-ns = <150000>;
 135                         opp-suspend;
 136                 };
 137
 138                 opp-1800000000 {
 139                         opp-hz = /bits/ 64 <1800000000>;
 140                         opp-microvolt = <1000000>;
 141                         opp-supported-hw = <0x8>, <0x3>;
 142                         clock-latency-ns = <150000>;
 143                         opp-suspend;
 144                 };
 145         };
 146
 147         osc_32k: clock-osc-32k {
 148                 compatible = "fixed-clock";
 149                 #clock-cells = <0>;
 150                 clock-frequency = <32768>;
 151                 clock-output-names = "osc_32k";
 152         };
 153
 154         osc_24m: clock-osc-24m {
 155                 compatible = "fixed-clock";
 156                 #clock-cells = <0>;
 157                 clock-frequency = <24000000>;
 158                 clock-output-names = "osc_24m";
 159         };
 160
 161         clk_ext1: clock-ext1 {
 162                 compatible = "fixed-clock";
 163                 #clock-cells = <0>;
 164                 clock-frequency = <133000000>;
 165                 clock-output-names = "clk_ext1";
 166         };
 167
 168         clk_ext2: clock-ext2 {
 169                 compatible = "fixed-clock";
 170                 #clock-cells = <0>;
 171                 clock-frequency = <133000000>;
 172                 clock-output-names = "clk_ext2";
 173         };
 174
 175         clk_ext3: clock-ext3 {
 176                 compatible = "fixed-clock";
 177                 #clock-cells = <0>;
 178                 clock-frequency = <133000000>;
 179                 clock-output-names = "clk_ext3";
 180         };
 181
 182         clk_ext4: clock-ext4 {
 183                 compatible = "fixed-clock";
 184                 #clock-cells = <0>;
 185                 clock-frequency= <133000000>;
 186                 clock-output-names = "clk_ext4";
 187         };
 188
 189         psci {
 190                 compatible = "arm,psci-1.0";
 191                 method = "smc";
 192         };
 193
 194         pmu {
 195                 compatible = "arm,armv8-pmuv3";
 196                 interrupts = <GIC_PPI 7
 197                              (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
 198                 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
 199         };
 200
 201         timer {
 202                 compatible = "arm,armv8-timer";
 203                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
 204                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
 205                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
 206                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
 207                 clock-frequency = <8000000>;
 208                 arm,no-tick-in-suspend;
 209         };
 210
 211         thermal-zones {
 212                 cpu-thermal {
 213                         polling-delay-passive = <250>;
 214                         polling-delay = <2000>;
 215                         thermal-sensors = <&tmu>;
 216                         trips {
 217                                 cpu_alert0: trip0 {
 218                                         temperature = <85000>;
 219                                         hysteresis = <2000>;
 220                                         type = "passive";
 221                                 };
 222
 223                                 cpu_crit0: trip1 {
 224                                         temperature = <95000>;
 225                                         hysteresis = <2000>;
 226                                         type = "critical";
 227                                 };
 228                         };
 229
 230                         cooling-maps {
 231                                 map0 {
 232                                         trip = <&cpu_alert0>;
 233                                         cooling-device =
 234                                                 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 235                                                 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 236                                                 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 237                                                 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 238                                 };
 239                         };
 240                 };
 241         };
 242
 243         usbphynop1: usbphynop1 {
 244                 compatible = "usb-nop-xceiv";
 245                 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
 246                 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
 247                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
 248                 clock-names = "main_clk";
 249         };
 250
 251         usbphynop2: usbphynop2 {
 252                 compatible = "usb-nop-xceiv";
 253                 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
 254                 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
 255                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
 256                 clock-names = "main_clk";
 257         };
 258
 259         soc@0 {
 260                 compatible = "simple-bus";
 261                 #address-cells = <1>;
 262                 #size-cells = <1>;
 263                 ranges = <0x0 0x0 0x0 0x3e000000>;
 264
 265                 aips1: bus@30000000 {
 266                         compatible = "fsl,aips-bus", "simple-bus";
 267                         reg = <0x301f0000 0x10000>;
 268                         #address-cells = <1>;
 269                         #size-cells = <1>;
 270                         ranges = <0x30000000 0x30000000 0x400000>;
 271
 272                         sai1: sai@30010000 {
 273                                 #sound-dai-cells = <0>;
 274                                 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 275                                 reg = <0x30010000 0x10000>;
 276                                 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 277                                 clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
 278                                          <&clk IMX8MM_CLK_SAI1_ROOT>,
 279                                          <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
 280                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 281                                 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
 282                                 dma-names = "rx", "tx";
 283                                 status = "disabled";
 284                         };
 285
 286                         sai2: sai@30020000 {
 287                                 #sound-dai-cells = <0>;
 288                                 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 289                                 reg = <0x30020000 0x10000>;
 290                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 291                                 clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
 292                                         <&clk IMX8MM_CLK_SAI2_ROOT>,
 293                                         <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
 294                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 295                                 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
 296                                 dma-names = "rx", "tx";
 297                                 status = "disabled";
 298                         };
 299
 300                         sai3: sai@30030000 {
 301                                 #sound-dai-cells = <0>;
 302                                 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 303                                 reg = <0x30030000 0x10000>;
 304                                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 305                                 clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
 306                                          <&clk IMX8MM_CLK_SAI3_ROOT>,
 307                                          <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
 308                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 309                                 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
 310                                 dma-names = "rx", "tx";
 311                                 status = "disabled";
 312                         };
 313
 314                         sai5: sai@30050000 {
 315                                 #sound-dai-cells = <0>;
 316                                 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 317                                 reg = <0x30050000 0x10000>;
 318                                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 319                                 clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
 320                                          <&clk IMX8MM_CLK_SAI5_ROOT>,
 321                                          <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
 322                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 323                                 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
 324                                 dma-names = "rx", "tx";
 325                                 status = "disabled";
 326                         };
 327
 328                         sai6: sai@30060000 {
 329                                 #sound-dai-cells = <0>;
 330                                 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 331                                 reg = <0x30060000 0x10000>;
 332                                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 333                                 clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
 334                                          <&clk IMX8MM_CLK_SAI6_ROOT>,
 335                                          <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
 336                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 337                                 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
 338                                 dma-names = "rx", "tx";
 339                                 status = "disabled";
 340                         };
 341
 342                         gpio1: gpio@30200000 {
 343                                 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
 344                                 reg = <0x30200000 0x10000>;
 345                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 346                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 347                                 clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>;
 348                                 gpio-controller;
 349                                 #gpio-cells = <2>;
 350                                 interrupt-controller;
 351                                 #interrupt-cells = <2>;
 352                                 gpio-ranges = <&iomuxc 0 10 30>;
 353                         };
 354
 355                         gpio2: gpio@30210000 {
 356                                 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
 357                                 reg = <0x30210000 0x10000>;
 358                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 359                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 360                                 clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>;
 361                                 gpio-controller;
 362                                 #gpio-cells = <2>;
 363                                 interrupt-controller;
 364                                 #interrupt-cells = <2>;
 365                                 gpio-ranges = <&iomuxc 0 40 21>;
 366                         };
 367
 368                         gpio3: gpio@30220000 {
 369                                 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
 370                                 reg = <0x30220000 0x10000>;
 371                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 372                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 373                                 clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>;
 374                                 gpio-controller;
 375                                 #gpio-cells = <2>;
 376                                 interrupt-controller;
 377                                 #interrupt-cells = <2>;
 378                                 gpio-ranges = <&iomuxc 0 61 26>;
 379                         };
 380
 381                         gpio4: gpio@30230000 {
 382                                 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
 383                                 reg = <0x30230000 0x10000>;
 384                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 385                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 386                                 clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>;
 387                                 gpio-controller;
 388                                 #gpio-cells = <2>;
 389                                 interrupt-controller;
 390                                 #interrupt-cells = <2>;
 391                                 gpio-ranges = <&iomuxc 0 87 32>;
 392                         };
 393
 394                         gpio5: gpio@30240000 {
 395                                 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
 396                                 reg = <0x30240000 0x10000>;
 397                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 398                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 399                                 clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>;
 400                                 gpio-controller;
 401                                 #gpio-cells = <2>;
 402                                 interrupt-controller;
 403                                 #interrupt-cells = <2>;
 404                                 gpio-ranges = <&iomuxc 0 119 30>;
 405                         };
 406
 407                         tmu: tmu@30260000 {
 408                                 compatible = "fsl,imx8mm-tmu";
 409                                 reg = <0x30260000 0x10000>;
 410                                 clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
 411                                 #thermal-sensor-cells = <0>;
 412                         };
 413
 414                         wdog1: watchdog@30280000 {
 415                                 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
 416                                 reg = <0x30280000 0x10000>;
 417                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 418                                 clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>;
 419                                 status = "disabled";
 420                         };
 421
 422                         wdog2: watchdog@30290000 {
 423                                 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
 424                                 reg = <0x30290000 0x10000>;
 425                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 426                                 clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>;
 427                                 status = "disabled";
 428                         };
 429
 430                         wdog3: watchdog@302a0000 {
 431                                 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
 432                                 reg = <0x302a0000 0x10000>;
 433                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 434                                 clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>;
 435                                 status = "disabled";
 436                         };
 437
 438                         sdma2: dma-controller@302c0000 {
 439                                 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
 440                                 reg = <0x302c0000 0x10000>;
 441                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 442                                 clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
 443                                          <&clk IMX8MM_CLK_SDMA2_ROOT>;
 444                                 clock-names = "ipg", "ahb";
 445                                 #dma-cells = <3>;
 446                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
 447                         };
 448
 449                         sdma3: dma-controller@302b0000 {
 450                                 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
 451                                 reg = <0x302b0000 0x10000>;
 452                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 453                                 clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
 454                                  <&clk IMX8MM_CLK_SDMA3_ROOT>;
 455                                 clock-names = "ipg", "ahb";
 456                                 #dma-cells = <3>;
 457                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
 458                         };
 459
 460                         iomuxc: pinctrl@30330000 {
 461                                 compatible = "fsl,imx8mm-iomuxc";
 462                                 reg = <0x30330000 0x10000>;
 463                         };
 464
 465                         gpr: iomuxc-gpr@30340000 {
 466                                 compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
 467                                 reg = <0x30340000 0x10000>;
 468                         };
 469
 470                         ocotp: ocotp-ctrl@30350000 {
 471                                 compatible = "fsl,imx8mm-ocotp", "syscon";
 472                                 reg = <0x30350000 0x10000>;
 473                                 clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
 474                                 /* For nvmem subnodes */
 475                                 #address-cells = <1>;
 476                                 #size-cells = <1>;
 477
 478                                 cpu_speed_grade: speed-grade@10 {
 479                                         reg = <0x10 4>;
 480                                 };
 481                         };
 482
 483                         anatop: anatop@30360000 {
 484                                 compatible = "fsl,imx8mm-anatop", "syscon";
 485                                 reg = <0x30360000 0x10000>;
 486                         };
 487
 488                         snvs: snvs@30370000 {
 489                                 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
 490                                 reg = <0x30370000 0x10000>;
 491
 492                                 snvs_rtc: snvs-rtc-lp {
 493                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 494                                         regmap = <&snvs>;
 495                                         offset = <0x34>;
 496                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 497                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 498                                         clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
 499                                         clock-names = "snvs-rtc";
 500                                 };
 501
 502                                 snvs_pwrkey: snvs-powerkey {
 503                                         compatible = "fsl,sec-v4.0-pwrkey";
 504                                         regmap = <&snvs>;
 505                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 506                                         clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
 507                                         clock-names = "snvs-pwrkey";
 508                                         linux,keycode = <KEY_POWER>;
 509                                         wakeup-source;
 510                                         status = "disabled";
 511                                 };
 512                         };
 513
 514                         clk: clock-controller@30380000 {
 515                                 compatible = "fsl,imx8mm-ccm";
 516                                 reg = <0x30380000 0x10000>;
 517                                 #clock-cells = <1>;
 518                                 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
 519                                          <&clk_ext3>, <&clk_ext4>;
 520                                 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
 521                                               "clk_ext3", "clk_ext4";
 522                                 assigned-clocks = <&clk IMX8MM_CLK_NOC>,
 523                                                 <&clk IMX8MM_CLK_AUDIO_AHB>,
 524                                                 <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
 525                                                 <&clk IMX8MM_SYS_PLL3>,
 526                                                 <&clk IMX8MM_VIDEO_PLL1>,
 527                                                 <&clk IMX8MM_AUDIO_PLL1>,
 528                                                 <&clk IMX8MM_AUDIO_PLL2>;
 529                                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
 530                                                          <&clk IMX8MM_SYS_PLL1_800M>;
 531                                 assigned-clock-rates = <0>,
 532                                                         <400000000>,
 533                                                         <400000000>,
 534                                                         <750000000>,
 535                                                         <594000000>,
 536                                                         <393216000>,
 537                                                         <361267200>;
 538                         };
 539
 540                         src: reset-controller@30390000 {
 541                                 compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon";
 542                                 reg = <0x30390000 0x10000>;
 543                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 544                                 #reset-cells = <1>;
 545                         };
 546                 };
 547
 548                 aips2: bus@30400000 {
 549                         compatible = "fsl,aips-bus", "simple-bus";
 550                         reg = <0x305f0000 0x10000>;
 551                         #address-cells = <1>;
 552                         #size-cells = <1>;
 553                         ranges = <0x30400000 0x30400000 0x400000>;
 554
 555                         pwm1: pwm@30660000 {
 556                                 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
 557                                 reg = <0x30660000 0x10000>;
 558                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 559                                 clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
 560                                         <&clk IMX8MM_CLK_PWM1_ROOT>;
 561                                 clock-names = "ipg", "per";
 562                                 #pwm-cells = <2>;
 563                                 status = "disabled";
 564                         };
 565
 566                         pwm2: pwm@30670000 {
 567                                 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
 568                                 reg = <0x30670000 0x10000>;
 569                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 570                                 clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
 571                                          <&clk IMX8MM_CLK_PWM2_ROOT>;
 572                                 clock-names = "ipg", "per";
 573                                 #pwm-cells = <2>;
 574                                 status = "disabled";
 575                         };
 576
 577                         pwm3: pwm@30680000 {
 578                                 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
 579                                 reg = <0x30680000 0x10000>;
 580                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 581                                 clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
 582                                          <&clk IMX8MM_CLK_PWM3_ROOT>;
 583                                 clock-names = "ipg", "per";
 584                                 #pwm-cells = <2>;
 585                                 status = "disabled";
 586                         };
 587
 588                         pwm4: pwm@30690000 {
 589                                 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
 590                                 reg = <0x30690000 0x10000>;
 591                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 592                                 clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
 593                                          <&clk IMX8MM_CLK_PWM4_ROOT>;
 594                                 clock-names = "ipg", "per";
 595                                 #pwm-cells = <2>;
 596                                 status = "disabled";
 597                         };
 598
 599                         system_counter: timer@306a0000 {
 600                                 compatible = "nxp,sysctr-timer";
 601                                 reg = <0x306a0000 0x20000>;
 602                                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 603                                 clocks = <&osc_24m>;
 604                                 clock-names = "per";
 605                         };
 606                 };
 607
 608                 aips3: bus@30800000 {
 609                         compatible = "fsl,aips-bus", "simple-bus";
 610                         reg = <0x309f0000 0x10000>;
 611                         #address-cells = <1>;
 612                         #size-cells = <1>;
 613                         ranges = <0x30800000 0x30800000 0x400000>,
 614                                  <0x8000000 0x8000000 0x10000000>;
 615
 616                         ecspi1: spi@30820000 {
 617                                 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
 618                                 #address-cells = <1>;
 619                                 #size-cells = <0>;
 620                                 reg = <0x30820000 0x10000>;
 621                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 622                                 clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
 623                                          <&clk IMX8MM_CLK_ECSPI1_ROOT>;
 624                                 clock-names = "ipg", "per";
 625                                 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
 626                                 dma-names = "rx", "tx";
 627                                 status = "disabled";
 628                         };
 629
 630                         ecspi2: spi@30830000 {
 631                                 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
 632                                 #address-cells = <1>;
 633                                 #size-cells = <0>;
 634                                 reg = <0x30830000 0x10000>;
 635                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 636                                 clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
 637                                          <&clk IMX8MM_CLK_ECSPI2_ROOT>;
 638                                 clock-names = "ipg", "per";
 639                                 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
 640                                 dma-names = "rx", "tx";
 641                                 status = "disabled";
 642                         };
 643
 644                         ecspi3: spi@30840000 {
 645                                 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
 646                                 #address-cells = <1>;
 647                                 #size-cells = <0>;
 648                                 reg = <0x30840000 0x10000>;
 649                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 650                                 clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
 651                                          <&clk IMX8MM_CLK_ECSPI3_ROOT>;
 652                                 clock-names = "ipg", "per";
 653                                 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
 654                                 dma-names = "rx", "tx";
 655                                 status = "disabled";
 656                         };
 657
 658                         uart1: serial@30860000 {
 659                                 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
 660                                 reg = <0x30860000 0x10000>;
 661                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 662                                 clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
 663                                          <&clk IMX8MM_CLK_UART1_ROOT>;
 664                                 clock-names = "ipg", "per";
 665                                 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
 666                                 dma-names = "rx", "tx";
 667                                 status = "disabled";
 668                         };
 669
 670                         uart3: serial@30880000 {
 671                                 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
 672                                 reg = <0x30880000 0x10000>;
 673                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 674                                 clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
 675                                          <&clk IMX8MM_CLK_UART3_ROOT>;
 676                                 clock-names = "ipg", "per";
 677                                 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
 678                                 dma-names = "rx", "tx";
 679                                 status = "disabled";
 680                         };
 681
 682                         uart2: serial@30890000 {
 683                                 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
 684                                 reg = <0x30890000 0x10000>;
 685                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 686                                 clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
 687                                          <&clk IMX8MM_CLK_UART2_ROOT>;
 688                                 clock-names = "ipg", "per";
 689                                 status = "disabled";
 690                         };
 691
 692                         crypto: crypto@30900000 {
 693                                 compatible = "fsl,sec-v4.0";
 694                                 #address-cells = <1>;
 695                                 #size-cells = <1>;
 696                                 reg = <0x30900000 0x40000>;
 697                                 ranges = <0 0x30900000 0x40000>;
 698                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 699                                 clocks = <&clk IMX8MM_CLK_AHB>,
 700                                          <&clk IMX8MM_CLK_IPG_ROOT>;
 701                                 clock-names = "aclk", "ipg";
 702
 703                                 sec_jr0: jr@1000 {
 704                                         compatible = "fsl,sec-v4.0-job-ring";
 705                                         reg = <0x1000 0x1000>;
 706                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 707                                 };
 708
 709                                 sec_jr1: jr@2000 {
 710                                         compatible = "fsl,sec-v4.0-job-ring";
 711                                         reg = <0x2000 0x1000>;
 712                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 713                                 };
 714
 715                                 sec_jr2: jr@3000 {
 716                                         compatible = "fsl,sec-v4.0-job-ring";
 717                                         reg = <0x3000 0x1000>;
 718                                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 719                                 };
 720                         };
 721
 722                         i2c1: i2c@30a20000 {
 723                                 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
 724                                 #address-cells = <1>;
 725                                 #size-cells = <0>;
 726                                 reg = <0x30a20000 0x10000>;
 727                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 728                                 clocks = <&clk IMX8MM_CLK_I2C1_ROOT>;
 729                                 status = "disabled";
 730                         };
 731
 732                         i2c2: i2c@30a30000 {
 733                                 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
 734                                 #address-cells = <1>;
 735                                 #size-cells = <0>;
 736                                 reg = <0x30a30000 0x10000>;
 737                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 738                                 clocks = <&clk IMX8MM_CLK_I2C2_ROOT>;
 739                                 status = "disabled";
 740                         };
 741
 742                         i2c3: i2c@30a40000 {
 743                                 #address-cells = <1>;
 744                                 #size-cells = <0>;
 745                                 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
 746                                 reg = <0x30a40000 0x10000>;
 747                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 748                                 clocks = <&clk IMX8MM_CLK_I2C3_ROOT>;
 749                                 status = "disabled";
 750                         };
 751
 752                         i2c4: i2c@30a50000 {
 753                                 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
 754                                 #address-cells = <1>;
 755                                 #size-cells = <0>;
 756                                 reg = <0x30a50000 0x10000>;
 757                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 758                                 clocks = <&clk IMX8MM_CLK_I2C4_ROOT>;
 759                                 status = "disabled";
 760                         };
 761
 762                         uart4: serial@30a60000 {
 763                                 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
 764                                 reg = <0x30a60000 0x10000>;
 765                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 766                                 clocks = <&clk IMX8MM_CLK_UART4_ROOT>,
 767                                          <&clk IMX8MM_CLK_UART4_ROOT>;
 768                                 clock-names = "ipg", "per";
 769                                 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
 770                                 dma-names = "rx", "tx";
 771                                 status = "disabled";
 772                         };
 773
 774                         usdhc1: mmc@30b40000 {
 775                                 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
 776                                 reg = <0x30b40000 0x10000>;
 777                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 778                                 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
 779                                          <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
 780                                          <&clk IMX8MM_CLK_USDHC1_ROOT>;
 781                                 clock-names = "ipg", "ahb", "per";
 782                                 fsl,tuning-start-tap = <20>;
 783                                 fsl,tuning-step= <2>;
 784                                 bus-width = <4>;
 785                                 status = "disabled";
 786                         };
 787
 788                         usdhc2: mmc@30b50000 {
 789                                 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
 790                                 reg = <0x30b50000 0x10000>;
 791                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 792                                 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
 793                                          <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
 794                                          <&clk IMX8MM_CLK_USDHC2_ROOT>;
 795                                 clock-names = "ipg", "ahb", "per";
 796                                 fsl,tuning-start-tap = <20>;
 797                                 fsl,tuning-step= <2>;
 798                                 bus-width = <4>;
 799                                 status = "disabled";
 800                         };
 801
 802                         usdhc3: mmc@30b60000 {
 803                                 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
 804                                 reg = <0x30b60000 0x10000>;
 805                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 806                                 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
 807                                          <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
 808                                          <&clk IMX8MM_CLK_USDHC3_ROOT>;
 809                                 clock-names = "ipg", "ahb", "per";
 810                                 fsl,tuning-start-tap = <20>;
 811                                 fsl,tuning-step= <2>;
 812                                 bus-width = <4>;
 813                                 status = "disabled";
 814                         };
 815
 816                         flexspi: spi@30bb0000 {
 817                                 #address-cells = <1>;
 818                                 #size-cells = <0>;
 819                                 compatible = "nxp,imx8mm-fspi";
 820                                 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
 821                                 reg-names = "fspi_base", "fspi_mmap";
 822                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 823                                 clocks = <&clk IMX8MM_CLK_QSPI_ROOT>,
 824                                          <&clk IMX8MM_CLK_QSPI_ROOT>;
 825                                 clock-names = "fspi", "fspi_en";
 826                                 status = "disabled";
 827                         };
 828
 829                         sdma1: dma-controller@30bd0000 {
 830                                 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
 831                                 reg = <0x30bd0000 0x10000>;
 832                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 833                                 clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
 834                                          <&clk IMX8MM_CLK_AHB>;
 835                                 clock-names = "ipg", "ahb";
 836                                 #dma-cells = <3>;
 837                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
 838                         };
 839
 840                         fec1: ethernet@30be0000 {
 841                                 compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec";
 842                                 reg = <0x30be0000 0x10000>;
 843                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 844                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 845                                              <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 846                                 clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
 847                                          <&clk IMX8MM_CLK_ENET1_ROOT>,
 848                                          <&clk IMX8MM_CLK_ENET_TIMER>,
 849                                          <&clk IMX8MM_CLK_ENET_REF>,
 850                                          <&clk IMX8MM_CLK_ENET_PHY_REF>;
 851                                 clock-names = "ipg", "ahb", "ptp",
 852                                               "enet_clk_ref", "enet_out";
 853                                 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
 854                                                   <&clk IMX8MM_CLK_ENET_TIMER>,
 855                                                   <&clk IMX8MM_CLK_ENET_REF>,
 856                                                   <&clk IMX8MM_CLK_ENET_TIMER>;
 857                                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
 858                                                          <&clk IMX8MM_SYS_PLL2_100M>,
 859                                                          <&clk IMX8MM_SYS_PLL2_125M>;
 860                                 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
 861                                 fsl,num-tx-queues = <3>;
 862                                 fsl,num-rx-queues = <3>;
 863                                 status = "disabled";
 864                         };
 865
 866                 };
 867
 868                 aips4: bus@32c00000 {
 869                         compatible = "fsl,aips-bus", "simple-bus";
 870                         reg = <0x32df0000 0x10000>;
 871                         #address-cells = <1>;
 872                         #size-cells = <1>;
 873                         ranges = <0x32c00000 0x32c00000 0x400000>;
 874
 875                         usbotg1: usb@32e40000 {
 876                                 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
 877                                 reg = <0x32e40000 0x200>;
 878                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 879                                 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
 880                                 clock-names = "usb1_ctrl_root_clk";
 881                                 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
 882                                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
 883                                 fsl,usbphy = <&usbphynop1>;
 884                                 fsl,usbmisc = <&usbmisc1 0>;
 885                                 status = "disabled";
 886                         };
 887
 888                         usbmisc1: usbmisc@32e40200 {
 889                                 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
 890                                 #index-cells = <1>;
 891                                 reg = <0x32e40200 0x200>;
 892                         };
 893
 894                         usbotg2: usb@32e50000 {
 895                                 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
 896                                 reg = <0x32e50000 0x200>;
 897                                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 898                                 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
 899                                 clock-names = "usb1_ctrl_root_clk";
 900                                 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
 901                                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
 902                                 fsl,usbphy = <&usbphynop2>;
 903                                 fsl,usbmisc = <&usbmisc2 0>;
 904                                 status = "disabled";
 905                         };
 906
 907                         usbmisc2: usbmisc@32e50200 {
 908                                 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
 909                                 #index-cells = <1>;
 910                                 reg = <0x32e50200 0x200>;
 911                         };
 912
 913                 };
 914
 915                 dma_apbh: dma-controller@33000000 {
 916                         compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
 917                         reg = <0x33000000 0x2000>;
 918                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 919                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 920                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 921                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 922                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
 923                         #dma-cells = <1>;
 924                         dma-channels = <4>;
 925                         clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
 926                 };
 927
 928                 gpmi: nand-controller@33002000{
 929                         compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
 930                         #address-cells = <1>;
 931                         #size-cells = <1>;
 932                         reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
 933                         reg-names = "gpmi-nand", "bch";
 934                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 935                         interrupt-names = "bch";
 936                         clocks = <&clk IMX8MM_CLK_NAND_ROOT>,
 937                                  <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
 938                         clock-names = "gpmi_io", "gpmi_bch_apb";
 939                         dmas = <&dma_apbh 0>;
 940                         dma-names = "rx-tx";
 941                         status = "disabled";
 942                 };
 943
 944                 gic: interrupt-controller@38800000 {
 945                         compatible = "arm,gic-v3";
 946                         reg = <0x38800000 0x10000>, /* GIC Dist */
 947                               <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
 948                         #interrupt-cells = <3>;
 949                         interrupt-controller;
 950                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 951                 };
 952
 953                 ddrc: memory-controller@3d400000 {
 954                         compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
 955                         reg = <0x3d400000 0x400000>;
 956                         clock-names = "core", "pll", "alt", "apb";
 957                         clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
 958                                  <&clk IMX8MM_DRAM_PLL>,
 959                                  <&clk IMX8MM_CLK_DRAM_ALT>,
 960                                  <&clk IMX8MM_CLK_DRAM_APB>;
 961                 };
 962
 963                 ddr-pmu@3d800000 {
 964                         compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
 965                         reg = <0x3d800000 0x400000>;
 966                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 967                 };
 968         };
 969 };