1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2022 Gateworks Corporation
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
13 #include "imx8mm.dtsi"
16 model = "Gateworks Venice GW7903 i.MX8MM board";
17 compatible = "gw,imx8mm-gw7903", "fsl,imx8mm";
29 device_type = "memory";
30 reg = <0x0 0x40000000 0 0x80000000>;
34 compatible = "gpio-keys";
38 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
45 interrupt-parent = <&gsc>;
52 interrupt-parent = <&gsc>;
59 interrupt-parent = <&gsc>;
64 label = "switch_hold";
66 interrupt-parent = <&gsc>;
72 compatible = "gpio-leds";
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_gpio_leds>;
77 function = LED_FUNCTION_STATUS;
78 color = <LED_COLOR_ID_RED>;
80 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
81 default-state = "off";
85 function = LED_FUNCTION_STATUS;
86 color = <LED_COLOR_ID_GREEN>;
88 gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
89 default-state = "off";
93 function = LED_FUNCTION_STATUS;
94 color = <LED_COLOR_ID_RED>;
96 gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
97 default-state = "off";
101 function = LED_FUNCTION_STATUS;
102 color = <LED_COLOR_ID_GREEN>;
104 gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
105 default-state = "off";
109 function = LED_FUNCTION_STATUS;
110 color = <LED_COLOR_ID_RED>;
112 gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
113 default-state = "off";
117 function = LED_FUNCTION_STATUS;
118 color = <LED_COLOR_ID_GREEN>;
120 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
121 default-state = "off";
125 function = LED_FUNCTION_STATUS;
126 color = <LED_COLOR_ID_RED>;
128 gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
129 default-state = "off";
133 function = LED_FUNCTION_STATUS;
134 color = <LED_COLOR_ID_GREEN>;
136 gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
137 default-state = "off";
141 function = LED_FUNCTION_STATUS;
142 color = <LED_COLOR_ID_RED>;
144 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
145 default-state = "off";
149 function = LED_FUNCTION_STATUS;
150 color = <LED_COLOR_ID_GREEN>;
152 gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
153 default-state = "off";
157 function = LED_FUNCTION_STATUS;
158 color = <LED_COLOR_ID_RED>;
160 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
161 default-state = "off";
165 function = LED_FUNCTION_STATUS;
166 color = <LED_COLOR_ID_GREEN>;
168 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
169 default-state = "off";
173 pcie0_refclk: pcie0-refclk {
174 compatible = "fixed-clock";
176 clock-frequency = <100000000>;
179 reg_3p3v: regulator-3p3v {
180 compatible = "regulator-fixed";
181 regulator-name = "3P3V";
182 regulator-min-microvolt = <3300000>;
183 regulator-max-microvolt = <3300000>;
189 cpu-supply = <&buck2>;
193 cpu-supply = <&buck2>;
197 cpu-supply = <&buck2>;
201 cpu-supply = <&buck2>;
205 operating-points-v2 = <&ddrc_opp_table>;
207 ddrc_opp_table: opp-table {
208 compatible = "operating-points-v2";
211 opp-hz = /bits/ 64 <25000000>;
215 opp-hz = /bits/ 64 <100000000>;
219 opp-hz = /bits/ 64 <750000000>;
225 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_fec1>;
227 phy-mode = "rgmii-id";
228 phy-handle = <ðphy0>;
229 local-mac-address = [00 00 00 00 00 00];
233 #address-cells = <1>;
236 ethphy0: ethernet-phy@0 {
237 compatible = "ethernet-phy-ieee802.3-c22";
239 rx-internal-delay-ps = <2000>;
240 tx-internal-delay-ps = <2500>;
246 gpio-line-names = "", "", "", "", "", "", "", "",
247 "", "", "rs422_en#", "rs485_en#", "rs232_en#", "", "", "",
248 "", "", "", "", "", "", "", "",
249 "", "", "", "", "", "", "", "";
253 gpio-line-names = "dig2_in", "dig2_out#", "dig2_ctl", "", "", "", "dig1_ctl", "",
254 "dig1_out#", "dig1_in", "", "", "", "", "", "",
255 "", "", "", "", "", "", "", "",
256 "", "", "", "", "", "", "", "";
260 gpio-line-names = "", "", "", "", "", "", "", "sim1_det#",
261 "sim2_det#", "sim2_sel", "", "", "pci_wdis#", "", "", "",
262 "", "", "", "", "", "", "", "",
263 "", "", "", "", "", "", "", "";
267 clock-frequency = <100000>;
268 pinctrl-names = "default";
269 pinctrl-0 = <&pinctrl_i2c1>;
273 compatible = "gw,gsc";
275 pinctrl-0 = <&pinctrl_gsc>;
276 interrupt-parent = <&gpio4>;
277 interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
278 interrupt-controller;
279 #interrupt-cells = <1>;
282 compatible = "gw,gsc-adc";
283 #address-cells = <1>;
302 gw,voltage-divider-ohms = <22100 1000>;
303 gw,voltage-offset-microvolt = <700000>;
310 gw,voltage-divider-ohms = <10000 10000>;
317 gw,voltage-divider-ohms = <10000 10000>;
354 gw,voltage-divider-ohms = <10000 10000>;
360 compatible = "nxp,pca9555";
364 interrupt-parent = <&gsc>;
369 compatible = "atmel,24c02";
375 compatible = "atmel,24c02";
381 compatible = "atmel,24c02";
387 compatible = "atmel,24c02";
393 compatible = "dallas,ds1672";
399 clock-frequency = <400000>;
400 pinctrl-names = "default";
401 pinctrl-0 = <&pinctrl_i2c2>;
405 compatible = "rohm,bd71847";
407 pinctrl-names = "default";
408 pinctrl-0 = <&pinctrl_pmic>;
409 interrupt-parent = <&gpio3>;
410 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
411 rohm,reset-snvs-powered;
413 clocks = <&osc_32k 0>;
414 clock-output-names = "clk-32k-out";
417 /* vdd_soc: 0.805-0.900V (typ=0.8V) */
419 regulator-name = "buck1";
420 regulator-min-microvolt = <700000>;
421 regulator-max-microvolt = <1300000>;
424 regulator-ramp-delay = <1250>;
427 /* vdd_arm: 0.805-1.0V (typ=0.9V) */
429 regulator-name = "buck2";
430 regulator-min-microvolt = <700000>;
431 regulator-max-microvolt = <1300000>;
434 regulator-ramp-delay = <1250>;
435 rohm,dvs-run-voltage = <1000000>;
436 rohm,dvs-idle-voltage = <900000>;
439 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
441 regulator-name = "buck3";
442 regulator-min-microvolt = <700000>;
443 regulator-max-microvolt = <1350000>;
450 regulator-name = "buck4";
451 regulator-min-microvolt = <3000000>;
452 regulator-max-microvolt = <3300000>;
459 regulator-name = "buck5";
460 regulator-min-microvolt = <1605000>;
461 regulator-max-microvolt = <1995000>;
468 regulator-name = "buck6";
469 regulator-min-microvolt = <800000>;
470 regulator-max-microvolt = <1400000>;
477 regulator-name = "ldo1";
478 regulator-min-microvolt = <1600000>;
479 regulator-max-microvolt = <1900000>;
486 regulator-name = "ldo2";
487 regulator-min-microvolt = <800000>;
488 regulator-max-microvolt = <900000>;
495 regulator-name = "ldo3";
496 regulator-min-microvolt = <1800000>;
497 regulator-max-microvolt = <3300000>;
503 regulator-name = "ldo4";
504 regulator-min-microvolt = <900000>;
505 regulator-max-microvolt = <1800000>;
511 regulator-name = "ldo6";
512 regulator-min-microvolt = <900000>;
513 regulator-max-microvolt = <1800000>;
522 clock-frequency = <400000>;
523 pinctrl-names = "default";
524 pinctrl-0 = <&pinctrl_i2c3>;
528 pinctrl-names = "default";
529 pinctrl-0 = <&pinctrl_accel>;
530 compatible = "st,lis2de12";
532 st,drdy-int-pin = <1>;
533 interrupt-parent = <&gpio1>;
534 interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
535 interrupt-names = "INT1";
540 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
541 fsl,clkreq-unsupported;
542 clocks = <&pcie0_refclk>;
548 pinctrl-names = "default";
549 pinctrl-0 = <&pinctrl_pcie0>;
550 reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
551 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
553 clock-names = "pcie", "pcie_aux", "pcie_bus";
554 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
555 <&clk IMX8MM_CLK_PCIE1_CTRL>;
556 assigned-clock-rates = <10000000>, <250000000>;
557 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
558 <&clk IMX8MM_SYS_PLL2_250M>;
566 /* off-board RS232/RS485/RS422 */
568 pinctrl-names = "default";
569 pinctrl-0 = <&pinctrl_uart1>;
570 cts-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
571 rts-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
572 dtr-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
573 dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
574 dcd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
581 pinctrl-names = "default";
582 pinctrl-0 = <&pinctrl_uart2>;
588 disable-over-current;
594 pinctrl-names = "default", "state_100mhz", "state_200mhz";
595 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
596 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
597 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
598 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
600 vmmc-supply = <®_3p3v>;
606 pinctrl-names = "default", "state_100mhz", "state_200mhz";
607 pinctrl-0 = <&pinctrl_usdhc3>;
608 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
609 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
616 pinctrl-names = "default";
617 pinctrl-0 = <&pinctrl_wdog>;
618 fsl,ext-reset-output;
623 pinctrl-names = "default";
624 pinctrl-0 = <&pinctrl_hog>;
626 pinctrl_hog: hoggrp {
628 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000041 /* RS422# */
629 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000041 /* RS485# */
630 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* RS232# */
631 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x40000041 /* DIG1_IN */
632 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* DIG1_OUT */
633 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40000041 /* DIG1_CTL */
634 MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x40000041 /* DIG2_CTL */
635 MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x40000041 /* DIG2_IN */
636 MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x40000041 /* DIG2_OUT */
637 MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x40000041 /* SIM1DET# */
638 MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x40000041 /* SIM2DET# */
639 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000041 /* SIM2SEL */
640 MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x40000041 /* PCI_WDIS# */
644 pinctrl_accel: accelgrp {
646 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x159
650 pinctrl_fec1: fec1grp {
652 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
653 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
654 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
655 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
656 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
657 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
658 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
659 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
660 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
661 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
662 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
663 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
664 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
665 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
666 MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x19 /* IRQ# */
667 MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* RST# */
671 pinctrl_gsc: gscgrp {
673 MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x159
677 pinctrl_i2c1: i2c1grp {
679 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
680 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
684 pinctrl_i2c2: i2c2grp {
686 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
687 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
691 pinctrl_i2c3: i2c3grp {
693 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
694 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
698 pinctrl_gpio_leds: gpioledgrp {
700 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
701 MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x19
702 MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19
703 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x19
704 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
705 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x19
706 MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19
707 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19
708 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
709 MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x19
710 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
711 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
715 pinctrl_pcie0: pciegrp {
717 MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41
721 pinctrl_pmic: pmicgrp {
723 MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
727 pinctrl_uart1: uart1grp {
729 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
730 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
731 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x140
732 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140
733 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x140
734 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x140
735 MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x140
739 pinctrl_uart2: uart2grp {
741 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
742 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
746 pinctrl_usdhc2: usdhc2grp {
748 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
749 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
750 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
751 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
752 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
753 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
757 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
759 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
760 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
761 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
762 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
763 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
764 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
768 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
770 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
771 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
772 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
773 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
774 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
775 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
779 pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
781 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
782 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
786 pinctrl_usdhc3: usdhc3grp {
788 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
789 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
790 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
791 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
792 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
793 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
794 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
795 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
796 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
797 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
798 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
802 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
804 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
805 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
806 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
807 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
808 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
809 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
810 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
811 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
812 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
813 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
814 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
818 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
820 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
821 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
822 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
823 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
824 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
825 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
826 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
827 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
828 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
829 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
830 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
834 pinctrl_wdog: wdoggrp {
836 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6