arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2021 Gateworks Corporation
   4  */
   5
   6 /dts-v1/;
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/input/linux-event-codes.h>
  10 #include <dt-bindings/leds/common.h>
  11 #include <dt-bindings/net/ti-dp83867.h>
  12 #include <dt-bindings/phy/phy-imx8-pcie.h>
  13
  14 #include "imx8mm.dtsi"
  15
  16 / {
  17         model = "Gateworks Venice GW7902 i.MX8MM board";
  18         compatible = "gw,imx8mm-gw7902", "fsl,imx8mm";
  19
  20         aliases {
  21                 ethernet1 = &eth1;
  22                 usb0 = &usbotg1;
  23                 usb1 = &usbotg2;
  24         };
  25
  26         chosen {
  27                 stdout-path = &uart2;
  28         };
  29
  30         memory@40000000 {
  31                 device_type = "memory";
  32                 reg = <0x0 0x40000000 0 0x80000000>;
  33         };
  34
  35         can20m: can20m {
  36                 compatible = "fixed-clock";
  37                 #clock-cells = <0>;
  38                 clock-frequency = <20000000>;
  39                 clock-output-names = "can20m";
  40         };
  41
  42         gpio-keys {
  43                 compatible = "gpio-keys";
  44
  45                 key-user-pb {
  46                         label = "user_pb";
  47                         gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
  48                         linux,code = <BTN_0>;
  49                 };
  50
  51                 key-user-pb1x {
  52                         label = "user_pb1x";
  53                         linux,code = <BTN_1>;
  54                         interrupt-parent = <&gsc>;
  55                         interrupts = <0>;
  56                 };
  57
  58                 key-erased {
  59                         label = "key_erased";
  60                         linux,code = <BTN_2>;
  61                         interrupt-parent = <&gsc>;
  62                         interrupts = <1>;
  63                 };
  64
  65                 key-eeprom-wp {
  66                         label = "eeprom_wp";
  67                         linux,code = <BTN_3>;
  68                         interrupt-parent = <&gsc>;
  69                         interrupts = <2>;
  70                 };
  71
  72                 key-tamper {
  73                         label = "tamper";
  74                         linux,code = <BTN_4>;
  75                         interrupt-parent = <&gsc>;
  76                         interrupts = <5>;
  77                 };
  78
  79                 switch-hold {
  80                         label = "switch_hold";
  81                         linux,code = <BTN_5>;
  82                         interrupt-parent = <&gsc>;
  83                         interrupts = <7>;
  84                 };
  85         };
  86
  87         led-controller {
  88                 compatible = "gpio-leds";
  89                 pinctrl-names = "default";
  90                 pinctrl-0 = <&pinctrl_gpio_leds>;
  91
  92                 led-0 {
  93                         function = LED_FUNCTION_STATUS;
  94                         color = <LED_COLOR_ID_GREEN>;
  95                         label = "panel1";
  96                         gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
  97                         default-state = "off";
  98                 };
  99
 100                 led-1 {
 101                         function = LED_FUNCTION_STATUS;
 102                         color = <LED_COLOR_ID_GREEN>;
 103                         label = "panel2";
 104                         gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
 105                         default-state = "off";
 106                 };
 107
 108                 led-2 {
 109                         function = LED_FUNCTION_STATUS;
 110                         color = <LED_COLOR_ID_GREEN>;
 111                         label = "panel3";
 112                         gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
 113                         default-state = "off";
 114                 };
 115
 116                 led-3 {
 117                         function = LED_FUNCTION_STATUS;
 118                         color = <LED_COLOR_ID_GREEN>;
 119                         label = "panel4";
 120                         gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
 121                         default-state = "off";
 122                 };
 123
 124                 led-4 {
 125                         function = LED_FUNCTION_STATUS;
 126                         color = <LED_COLOR_ID_GREEN>;
 127                         label = "panel5";
 128                         gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
 129                         default-state = "off";
 130                 };
 131         };
 132
 133         pcie0_refclk: pcie0-refclk {
 134                 compatible = "fixed-clock";
 135                 #clock-cells = <0>;
 136                 clock-frequency = <100000000>;
 137         };
 138
 139         pps {
 140                 compatible = "pps-gpio";
 141                 pinctrl-names = "default";
 142                 pinctrl-0 = <&pinctrl_pps>;
 143                 gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
 144                 status = "okay";
 145         };
 146
 147         reg_3p3v: regulator-3p3v {
 148                 compatible = "regulator-fixed";
 149                 regulator-name = "3P3V";
 150                 regulator-min-microvolt = <3300000>;
 151                 regulator-max-microvolt = <3300000>;
 152                 regulator-always-on;
 153         };
 154
 155         reg_usb1_vbus: regulator-usb1 {
 156                 compatible = "regulator-fixed";
 157                 pinctrl-names = "default";
 158                 pinctrl-0 = <&pinctrl_reg_usb1>;
 159                 regulator-name = "usb_usb1_vbus";
 160                 gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
 161                 enable-active-high;
 162                 regulator-min-microvolt = <5000000>;
 163                 regulator-max-microvolt = <5000000>;
 164         };
 165
 166         reg_wifi: regulator-wifi {
 167                 compatible = "regulator-fixed";
 168                 pinctrl-names = "default";
 169                 pinctrl-0 = <&pinctrl_reg_wl>;
 170                 regulator-name = "wifi";
 171                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
 172                 enable-active-high;
 173                 startup-delay-us = <100>;
 174                 regulator-min-microvolt = <3300000>;
 175                 regulator-max-microvolt = <3300000>;
 176         };
 177 };
 178
 179 &A53_0 {
 180         cpu-supply = <&buck2>;
 181 };
 182
 183 &A53_1 {
 184         cpu-supply = <&buck2>;
 185 };
 186
 187 &A53_2 {
 188         cpu-supply = <&buck2>;
 189 };
 190
 191 &A53_3 {
 192         cpu-supply = <&buck2>;
 193 };
 194
 195 &ddrc {
 196         operating-points-v2 = <&ddrc_opp_table>;
 197
 198         ddrc_opp_table: opp-table {
 199                 compatible = "operating-points-v2";
 200
 201                 opp-25M {
 202                         opp-hz = /bits/ 64 <25000000>;
 203                 };
 204
 205                 opp-100M {
 206                         opp-hz = /bits/ 64 <100000000>;
 207                 };
 208
 209                 opp-750M {
 210                         opp-hz = /bits/ 64 <750000000>;
 211                 };
 212         };
 213 };
 214
 215 &ecspi1 {
 216         pinctrl-names = "default";
 217         pinctrl-0 = <&pinctrl_spi1>;
 218         cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
 219         status = "okay";
 220
 221         can@0 {
 222                 compatible = "microchip,mcp2515";
 223                 reg = <0>;
 224                 clocks = <&can20m>;
 225                 interrupt-parent = <&gpio2>;
 226                 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 227                 spi-max-frequency = <10000000>;
 228         };
 229 };
 230
 231 /* off-board header */
 232 &ecspi2 {
 233         pinctrl-names = "default";
 234         pinctrl-0 = <&pinctrl_spi2>;
 235         cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
 236         status = "okay";
 237 };
 238
 239 &fec1 {
 240         pinctrl-names = "default";
 241         pinctrl-0 = <&pinctrl_fec1>;
 242         phy-mode = "rgmii-id";
 243         phy-handle = <&ethphy0>;
 244         local-mac-address = [00 00 00 00 00 00];
 245         status = "okay";
 246
 247         mdio {
 248                 #address-cells = <1>;
 249                 #size-cells = <0>;
 250
 251                 ethphy0: ethernet-phy@0 {
 252                         compatible = "ethernet-phy-ieee802.3-c22";
 253                         reg = <0>;
 254                         ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 255                         ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 256                         tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 257                         rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 258                 };
 259         };
 260 };
 261
 262 &gpio1 {
 263         gpio-line-names = "", "", "", "", "", "", "", "",
 264                 "", "", "", "", "", "m2_reset", "", "m2_wdis#",
 265                 "", "", "", "", "", "", "", "",
 266                 "", "", "", "", "", "", "", "";
 267 };
 268
 269 &gpio2 {
 270         gpio-line-names = "", "", "", "", "", "", "", "",
 271                 "uart2_en#", "", "", "", "", "", "", "",
 272                 "", "", "", "", "", "", "", "",
 273                 "", "", "", "", "", "", "", "";
 274 };
 275
 276 &gpio3 {
 277         gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#",
 278                 "", "", "", "", "", "", "", "",
 279                 "", "", "", "", "", "", "", "",
 280                 "", "", "", "", "", "", "", "";
 281 };
 282
 283 &gpio4 {
 284         gpio-line-names = "", "", "", "", "", "", "", "",
 285                 "", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "",
 286                 "", "", "", "", "amp_gpio4", "app_gpio1", "", "uart1_rs485",
 287                 "", "uart1_term", "uart1_half", "app_gpio2",
 288                 "mipi_gpio1", "", "", "";
 289 };
 290
 291 &gpio5 {
 292         gpio-line-names = "", "", "", "mipi_gpio4",
 293                 "mipi_gpio3", "mipi_gpio2", "", "",
 294                 "", "", "", "", "", "", "", "",
 295                 "", "", "", "", "", "", "", "",
 296                 "", "", "", "", "", "", "", "";
 297 };
 298
 299 &i2c1 {
 300         clock-frequency = <100000>;
 301         pinctrl-names = "default", "gpio";
 302         pinctrl-0 = <&pinctrl_i2c1>;
 303         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 304         scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 305         sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 306         status = "okay";
 307
 308         gsc: gsc@20 {
 309                 compatible = "gw,gsc";
 310                 reg = <0x20>;
 311                 pinctrl-0 = <&pinctrl_gsc>;
 312                 interrupt-parent = <&gpio2>;
 313                 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
 314                 interrupt-controller;
 315                 #interrupt-cells = <1>;
 316
 317                 adc {
 318                         compatible = "gw,gsc-adc";
 319                         #address-cells = <1>;
 320                         #size-cells = <0>;
 321
 322                         channel@6 {
 323                                 gw,mode = <0>;
 324                                 reg = <0x06>;
 325                                 label = "temp";
 326                         };
 327
 328                         channel@8 {
 329                                 gw,mode = <1>;
 330                                 reg = <0x08>;
 331                                 label = "vdd_bat";
 332                         };
 333
 334                         channel@82 {
 335                                 gw,mode = <2>;
 336                                 reg = <0x82>;
 337                                 label = "vin";
 338                                 gw,voltage-divider-ohms = <22100 1000>;
 339                                 gw,voltage-offset-microvolt = <700000>;
 340                         };
 341
 342                         channel@84 {
 343                                 gw,mode = <2>;
 344                                 reg = <0x84>;
 345                                 label = "vin_4p0";
 346                                 gw,voltage-divider-ohms = <10000 10000>;
 347                         };
 348
 349                         channel@86 {
 350                                 gw,mode = <2>;
 351                                 reg = <0x86>;
 352                                 label = "vdd_3p3";
 353                                 gw,voltage-divider-ohms = <10000 10000>;
 354                         };
 355
 356                         channel@88 {
 357                                 gw,mode = <2>;
 358                                 reg = <0x88>;
 359                                 label = "vdd_0p9";
 360                         };
 361
 362                         channel@8c {
 363                                 gw,mode = <2>;
 364                                 reg = <0x8c>;
 365                                 label = "vdd_soc";
 366                         };
 367
 368                         channel@8e {
 369                                 gw,mode = <2>;
 370                                 reg = <0x8e>;
 371                                 label = "vdd_arm";
 372                         };
 373
 374                         channel@90 {
 375                                 gw,mode = <2>;
 376                                 reg = <0x90>;
 377                                 label = "vdd_1p8";
 378                         };
 379
 380                         channel@92 {
 381                                 gw,mode = <2>;
 382                                 reg = <0x92>;
 383                                 label = "vdd_dram";
 384                         };
 385
 386                         channel@98 {
 387                                 gw,mode = <2>;
 388                                 reg = <0x98>;
 389                                 label = "vdd_1p0";
 390                         };
 391
 392                         channel@9a {
 393                                 gw,mode = <2>;
 394                                 reg = <0x9a>;
 395                                 label = "vdd_2p5";
 396                                 gw,voltage-divider-ohms = <10000 10000>;
 397                         };
 398
 399                         channel@9c {
 400                                 gw,mode = <2>;
 401                                 reg = <0x9c>;
 402                                 label = "vdd_5p0";
 403                                 gw,voltage-divider-ohms = <10000 10000>;
 404                         };
 405
 406                         channel@a2 {
 407                                 gw,mode = <2>;
 408                                 reg = <0xa2>;
 409                                 label = "vdd_gsc";
 410                                 gw,voltage-divider-ohms = <10000 10000>;
 411                         };
 412                 };
 413         };
 414
 415         gpio: gpio@23 {
 416                 compatible = "nxp,pca9555";
 417                 reg = <0x23>;
 418                 gpio-controller;
 419                 #gpio-cells = <2>;
 420                 interrupt-parent = <&gsc>;
 421                 interrupts = <4>;
 422         };
 423
 424         pmic@4b {
 425                 compatible = "rohm,bd71847";
 426                 reg = <0x4b>;
 427                 pinctrl-names = "default";
 428                 pinctrl-0 = <&pinctrl_pmic>;
 429                 interrupt-parent = <&gpio3>;
 430                 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
 431                 rohm,reset-snvs-powered;
 432                 #clock-cells = <0>;
 433                 clocks = <&osc_32k 0>;
 434                 clock-output-names = "clk-32k-out";
 435
 436                 regulators {
 437                         /* vdd_soc: 0.805-0.900V (typ=0.8V) */
 438                         BUCK1 {
 439                                 regulator-name = "buck1";
 440                                 regulator-min-microvolt = <700000>;
 441                                 regulator-max-microvolt = <1300000>;
 442                                 regulator-boot-on;
 443                                 regulator-always-on;
 444                                 regulator-ramp-delay = <1250>;
 445                         };
 446
 447                         /* vdd_arm: 0.805-1.0V (typ=0.9V) */
 448                         buck2: BUCK2 {
 449                                 regulator-name = "buck2";
 450                                 regulator-min-microvolt = <700000>;
 451                                 regulator-max-microvolt = <1300000>;
 452                                 regulator-boot-on;
 453                                 regulator-always-on;
 454                                 regulator-ramp-delay = <1250>;
 455                                 rohm,dvs-run-voltage = <1000000>;
 456                                 rohm,dvs-idle-voltage = <900000>;
 457                         };
 458
 459                         /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
 460                         BUCK3 {
 461                                 regulator-name = "buck3";
 462                                 regulator-min-microvolt = <700000>;
 463                                 regulator-max-microvolt = <1350000>;
 464                                 regulator-boot-on;
 465                                 regulator-always-on;
 466                         };
 467
 468                         /* vdd_3p3 */
 469                         BUCK4 {
 470                                 regulator-name = "buck4";
 471                                 regulator-min-microvolt = <3000000>;
 472                                 regulator-max-microvolt = <3300000>;
 473                                 regulator-boot-on;
 474                                 regulator-always-on;
 475                         };
 476
 477                         /* vdd_1p8 */
 478                         BUCK5 {
 479                                 regulator-name = "buck5";
 480                                 regulator-min-microvolt = <1605000>;
 481                                 regulator-max-microvolt = <1995000>;
 482                                 regulator-boot-on;
 483                                 regulator-always-on;
 484                         };
 485
 486                         /* vdd_dram */
 487                         BUCK6 {
 488                                 regulator-name = "buck6";
 489                                 regulator-min-microvolt = <800000>;
 490                                 regulator-max-microvolt = <1400000>;
 491                                 regulator-boot-on;
 492                                 regulator-always-on;
 493                         };
 494
 495                         /* nvcc_snvs_1p8 */
 496                         LDO1 {
 497                                 regulator-name = "ldo1";
 498                                 regulator-min-microvolt = <1600000>;
 499                                 regulator-max-microvolt = <1900000>;
 500                                 regulator-boot-on;
 501                                 regulator-always-on;
 502                         };
 503
 504                         /* vdd_snvs_0p8 */
 505                         LDO2 {
 506                                 regulator-name = "ldo2";
 507                                 regulator-min-microvolt = <800000>;
 508                                 regulator-max-microvolt = <900000>;
 509                                 regulator-boot-on;
 510                                 regulator-always-on;
 511                         };
 512
 513                         /* vdda_1p8 */
 514                         LDO3 {
 515                                 regulator-name = "ldo3";
 516                                 regulator-min-microvolt = <1800000>;
 517                                 regulator-max-microvolt = <3300000>;
 518                                 regulator-boot-on;
 519                                 regulator-always-on;
 520                         };
 521
 522                         LDO4 {
 523                                 regulator-name = "ldo4";
 524                                 regulator-min-microvolt = <900000>;
 525                                 regulator-max-microvolt = <1800000>;
 526                                 regulator-boot-on;
 527                                 regulator-always-on;
 528                         };
 529
 530                         LDO6 {
 531                                 regulator-name = "ldo6";
 532                                 regulator-min-microvolt = <900000>;
 533                                 regulator-max-microvolt = <1800000>;
 534                                 regulator-boot-on;
 535                                 regulator-always-on;
 536                         };
 537                 };
 538         };
 539
 540         eeprom@50 {
 541                 compatible = "atmel,24c02";
 542                 reg = <0x50>;
 543                 pagesize = <16>;
 544         };
 545
 546         eeprom@51 {
 547                 compatible = "atmel,24c02";
 548                 reg = <0x51>;
 549                 pagesize = <16>;
 550         };
 551
 552         eeprom@52 {
 553                 compatible = "atmel,24c02";
 554                 reg = <0x52>;
 555                 pagesize = <16>;
 556         };
 557
 558         eeprom@53 {
 559                 compatible = "atmel,24c02";
 560                 reg = <0x53>;
 561                 pagesize = <16>;
 562         };
 563
 564         rtc@68 {
 565                 compatible = "dallas,ds1672";
 566                 reg = <0x68>;
 567         };
 568 };
 569
 570 &i2c2 {
 571         clock-frequency = <400000>;
 572         pinctrl-names = "default", "gpio";
 573         pinctrl-0 = <&pinctrl_i2c2>;
 574         pinctrl-1 = <&pinctrl_i2c2_gpio>;
 575         scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 576         sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 577         status = "okay";
 578
 579         accelerometer@19 {
 580                 compatible = "st,lis2de12";
 581                 pinctrl-names = "default";
 582                 pinctrl-0 = <&pinctrl_accel>;
 583                 reg = <0x19>;
 584                 st,drdy-int-pin = <1>;
 585                 interrupt-parent = <&gpio1>;
 586                 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
 587                 interrupt-names = "INT1";
 588         };
 589 };
 590
 591 /* off-board header */
 592 &i2c3 {
 593         clock-frequency = <400000>;
 594         pinctrl-names = "default", "gpio";
 595         pinctrl-0 = <&pinctrl_i2c3>;
 596         pinctrl-1 = <&pinctrl_i2c3_gpio>;
 597         scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 598         sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 599         status = "okay";
 600 };
 601
 602 /* off-board header */
 603 &i2c4 {
 604         clock-frequency = <400000>;
 605         pinctrl-names = "default", "gpio";
 606         pinctrl-0 = <&pinctrl_i2c4>;
 607         pinctrl-1 = <&pinctrl_i2c4_gpio>;
 608         scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 609         sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 610         status = "okay";
 611 };
 612
 613 &pcie_phy {
 614         fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
 615         fsl,clkreq-unsupported;
 616         clocks = <&pcie0_refclk>;
 617         clock-names = "ref";
 618         status = "okay";
 619 };
 620
 621 &pcie0 {
 622         pinctrl-names = "default";
 623         pinctrl-0 = <&pinctrl_pcie0>;
 624         reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
 625         clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
 626                  <&pcie0_refclk>;
 627         clock-names = "pcie", "pcie_aux", "pcie_bus";
 628         assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
 629                           <&clk IMX8MM_CLK_PCIE1_CTRL>;
 630         assigned-clock-rates = <10000000>, <250000000>;
 631         assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
 632                                  <&clk IMX8MM_SYS_PLL2_250M>;
 633         status = "okay";
 634
 635         pcie@0,0 {
 636                 reg = <0x0000 0 0 0 0>;
 637                 #address-cells = <1>;
 638                 #size-cells = <0>;
 639
 640                 eth1: pcie@1,0 {
 641                         reg = <0x0000 0 0 0 0>;
 642                         #address-cells = <1>;
 643                         #size-cells = <0>;
 644
 645                         local-mac-address = [00 00 00 00 00 00];
 646                 };
 647         };
 648 };
 649
 650 /* off-board header */
 651 &sai3 {
 652         pinctrl-names = "default";
 653         pinctrl-0 = <&pinctrl_sai3>;
 654         assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
 655         assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
 656         assigned-clock-rates = <24576000>;
 657         status = "okay";
 658 };
 659
 660 /* RS232/RS485/RS422 selectable */
 661 &uart1 {
 662         pinctrl-names = "default";
 663         pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
 664         rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
 665         cts-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
 666         uart-has-rtscts;
 667         status = "okay";
 668 };
 669
 670 /* RS232 console */
 671 &uart2 {
 672         pinctrl-names = "default";
 673         pinctrl-0 = <&pinctrl_uart2>;
 674         status = "okay";
 675 };
 676
 677 /* bluetooth HCI */
 678 &uart3 {
 679         pinctrl-names = "default";
 680         pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
 681         rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
 682         cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 683         uart-has-rtscts;
 684         status = "okay";
 685
 686         bluetooth {
 687                 compatible = "brcm,bcm4330-bt";
 688                 shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
 689         };
 690 };
 691
 692 /* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */
 693 &uart4 {
 694         pinctrl-names = "default";
 695         pinctrl-0 = <&pinctrl_uart4>;
 696         rts-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
 697         cts-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;
 698         dtr-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>;
 699         dsr-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>;
 700         dcd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
 701         uart-has-rtscts;
 702         status = "okay";
 703 };
 704
 705 &usbotg1 {
 706         dr_mode = "host";
 707         vbus-supply = <&reg_usb1_vbus>;
 708         disable-over-current;
 709         status = "okay";
 710 };
 711
 712 &usbotg2 {
 713         dr_mode = "host";
 714         disable-over-current;
 715         status = "okay";
 716 };
 717
 718 /* SDIO WiFi */
 719 &usdhc2 {
 720         pinctrl-names = "default";
 721         pinctrl-0 = <&pinctrl_usdhc2>;
 722         bus-width = <4>;
 723         non-removable;
 724         vmmc-supply = <&reg_wifi>;
 725         status = "okay";
 726 };
 727
 728 /* eMMC */
 729 &usdhc3 {
 730         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 731         pinctrl-0 = <&pinctrl_usdhc3>;
 732         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 733         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 734         bus-width = <8>;
 735         non-removable;
 736         status = "okay";
 737 };
 738
 739 &wdog1 {
 740         pinctrl-names = "default";
 741         pinctrl-0 = <&pinctrl_wdog>;
 742         fsl,ext-reset-output;
 743         status = "okay";
 744 };
 745
 746 &iomuxc {
 747         pinctrl-names = "default";
 748         pinctrl-0 = <&pinctrl_hog>;
 749
 750         pinctrl_hog: hoggrp {
 751                 fsl,pins = <
 752                         MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1       0x40000159 /* M2_GDIS# */
 753                         MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13      0x40000041 /* M2_RESET */
 754                         MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7      0x40000119 /* M2_OFF# */
 755                         MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15      0x40000159 /* M2_WDIS# */
 756                         MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14       0x40000041 /* AMP GPIO1 */
 757                         MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12       0x40000041 /* AMP GPIO2 */
 758                         MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11        0x40000041 /* AMP GPIO3 */
 759                         MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20       0x40000041 /* AMP_GPIO4 */
 760                         MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21       0x40000041 /* APP GPIO1 */
 761                         MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27       0x40000041 /* APP GPIO2 */
 762                         MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8        0x40000041 /* UART2_EN# */
 763                         MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28       0x40000041 /* MIPI_GPIO1 */
 764                         MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5    0x40000041 /* MIPI_GPIO2 */
 765                         MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4         0x40000041 /* MIPI_GPIO3/PWM2 */
 766                         MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3         0x40000041 /* MIPI_GPIO4/PWM3 */
 767                 >;
 768         };
 769
 770         pinctrl_accel: accelgrp {
 771                 fsl,pins = <
 772                         MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12      0x159
 773                 >;
 774         };
 775
 776         pinctrl_fec1: fec1grp {
 777                 fsl,pins = <
 778                         MX8MM_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
 779                         MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO               0x3
 780                         MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3           0x1f
 781                         MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2           0x1f
 782                         MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x1f
 783                         MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x1f
 784                         MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3           0x91
 785                         MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2           0x91
 786                         MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91
 787                         MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91
 788                         MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC           0x1f
 789                         MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC           0x91
 790                         MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 791                         MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 792                         MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10              0x19 /* RST# */
 793                         MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11              0x19 /* IRQ# */
 794                         MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN    0x141
 795                         MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT   0x141
 796                 >;
 797         };
 798
 799         pinctrl_gsc: gscgrp {
 800                 fsl,pins = <
 801                         MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6        0x40
 802                 >;
 803         };
 804
 805         pinctrl_i2c1: i2c1grp {
 806                 fsl,pins = <
 807                         MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL          0x400001c3
 808                         MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA          0x400001c3
 809                 >;
 810         };
 811
 812         pinctrl_i2c1_gpio: i2c1gpiogrp {
 813                 fsl,pins = <
 814                         MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14        0x400001c3
 815                         MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15        0x400001c3
 816                 >;
 817         };
 818
 819         pinctrl_i2c2: i2c2grp {
 820                 fsl,pins = <
 821                         MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL          0x400001c3
 822                         MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA          0x400001c3
 823                 >;
 824         };
 825
 826         pinctrl_i2c2_gpio: i2c2gpiogrp {
 827                 fsl,pins = <
 828                         MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16        0x400001c3
 829                         MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17        0x400001c3
 830                 >;
 831         };
 832
 833         pinctrl_i2c3: i2c3grp {
 834                 fsl,pins = <
 835                         MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL          0x400001c3
 836                         MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA          0x400001c3
 837                 >;
 838         };
 839
 840         pinctrl_i2c3_gpio: i2c3gpiogrp {
 841                 fsl,pins = <
 842                         MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18        0x400001c3
 843                         MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19        0x400001c3
 844                 >;
 845         };
 846
 847         pinctrl_i2c4: i2c4grp {
 848                 fsl,pins = <
 849                         MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL          0x400001c3
 850                         MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA          0x400001c3
 851                 >;
 852         };
 853
 854         pinctrl_i2c4_gpio: i2c4gpiogrp {
 855                 fsl,pins = <
 856                         MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20        0x400001c3
 857                         MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21        0x400001c3
 858                 >;
 859         };
 860
 861         pinctrl_gpio_leds: gpioledgrp {
 862                 fsl,pins = <
 863                         MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21       0x19
 864                         MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23       0x19
 865                         MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22       0x19
 866                         MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20        0x19
 867                         MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25       0x19
 868                 >;
 869         };
 870
 871         pinctrl_pcie0: pciegrp {
 872                 fsl,pins = <
 873                         MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5        0x41
 874                 >;
 875         };
 876
 877         pinctrl_pmic: pmicgrp {
 878                 fsl,pins = <
 879                         MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8      0x41
 880                 >;
 881         };
 882
 883         pinctrl_pps: ppsgrp {
 884                 fsl,pins = <
 885                         MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24       0x141 /* PPS */
 886                 >;
 887         };
 888
 889         pinctrl_reg_wl: regwlgrp {
 890                 fsl,pins = <
 891                         MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19     0x41 /* WLAN_WLON */
 892                 >;
 893         };
 894
 895         pinctrl_reg_usb1: regusb1grp {
 896                 fsl,pins = <
 897                         MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7        0x41
 898                 >;
 899         };
 900
 901         pinctrl_sai3: sai3grp {
 902                 fsl,pins = <
 903                         MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
 904                         MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0     0xd6
 905                         MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
 906                         MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
 907                         MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
 908                 >;
 909         };
 910
 911         pinctrl_spi1: spi1grp {
 912                 fsl,pins = <
 913                         MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK    0x82
 914                         MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI    0x82
 915                         MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO    0x82
 916                         MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9       0x40
 917                         MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3        0x140 /* CAN_IRQ# */
 918                 >;
 919         };
 920
 921         pinctrl_spi2: spi2grp {
 922                 fsl,pins = <
 923                         MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK    0x82
 924                         MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI    0x82
 925                         MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO    0x82
 926                         MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13      0x40 /* SS0 */
 927                 >;
 928         };
 929
 930         pinctrl_uart1: uart1grp {
 931                 fsl,pins = <
 932                         MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX     0x140
 933                         MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX     0x140
 934                         MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10       0x140 /* RTS */
 935                         MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24       0x140 /* CTS */
 936                 >;
 937         };
 938
 939         pinctrl_uart1_gpio: uart1gpiogrp {
 940                 fsl,pins = <
 941                         MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26       0x40000110 /* HALF */
 942                         MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25        0x40000110 /* TERM */
 943                         MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23       0x40000110 /* RS485 */
 944                 >;
 945         };
 946
 947         pinctrl_uart2: uart2grp {
 948                 fsl,pins = <
 949                         MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140
 950                         MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140
 951                 >;
 952         };
 953
 954         pinctrl_uart3_gpio: uart3_gpiogrp {
 955                 fsl,pins = <
 956                         MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12        0x41 /* BT_EN# */
 957                 >;
 958         };
 959
 960         pinctrl_uart3: uart3grp {
 961                 fsl,pins = <
 962                         MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX     0x140
 963                         MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX     0x140
 964                         MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0          0x140 /* CTS */
 965                         MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1          0x140 /* RTS */
 966                 >;
 967         };
 968
 969         pinctrl_uart4: uart4grp {
 970                 fsl,pins = <
 971                         MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX     0x140
 972                         MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX     0x140
 973                         MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1         0x140 /* CTS */
 974                         MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2        0x140 /* RTS */
 975                         MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3        0x140 /* DTR */
 976                         MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4        0x140 /* DSR */
 977                         MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6        0x140 /* DCD */
 978                         MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7        0x140 /* RI */
 979                         MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0        0x140 /* GNSS_PPS */
 980                         MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6       0x141 /* GNSS_GASP */
 981                 >;
 982         };
 983
 984         pinctrl_usdhc2: usdhc2grp {
 985                 fsl,pins = <
 986                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x190
 987                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d0
 988                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d0
 989                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d0
 990                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d0
 991                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d0
 992                 >;
 993         };
 994
 995         pinctrl_usdhc3: usdhc3grp {
 996                 fsl,pins = <
 997                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK       0x190
 998                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d0
 999                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d0
1000                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d0
1001                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d0
1002                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d0
1003                         MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d0
1004                         MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d0
1005                         MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d0
1006                         MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d0
1007                         MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x190
1008                 >;
1009         };
1010
1011         pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1012                 fsl,pins = <
1013                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK       0x194
1014                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d4
1015                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d4
1016                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d4
1017                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d4
1018                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d4
1019                         MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d4
1020                         MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d4
1021                         MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d4
1022                         MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d4
1023                         MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x194
1024                 >;
1025         };
1026
1027         pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1028                 fsl,pins = <
1029                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK       0x196
1030                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d6
1031                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d6
1032                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d6
1033                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d6
1034                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d6
1035                         MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d6
1036                         MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d6
1037                         MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d6
1038                         MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d6
1039                         MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x196
1040                 >;
1041         };
1042
1043         pinctrl_wdog: wdoggrp {
1044                 fsl,pins = <
1045                         MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B    0xc6
1046                 >;
1047         };
1048 };