1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2020 Gateworks Corporation
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
13 #include "imx8mm.dtsi"
16 model = "Gateworks Venice GW7901 i.MX8MM board";
17 compatible = "gw,imx8mm-gw7901", "fsl,imx8mm";
34 device_type = "memory";
35 reg = <0x0 0x40000000 0 0x80000000>;
39 compatible = "gpio-keys";
43 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
50 interrupt-parent = <&gsc>;
57 interrupt-parent = <&gsc>;
64 interrupt-parent = <&gsc>;
71 interrupt-parent = <&gsc>;
76 label = "switch_hold";
78 interrupt-parent = <&gsc>;
84 compatible = "gpio-leds";
87 function = LED_FUNCTION_STATUS;
88 color = <LED_COLOR_ID_RED>;
90 gpios = <&leds_gpio 0 GPIO_ACTIVE_HIGH>;
91 default-state = "off";
95 function = LED_FUNCTION_STATUS;
96 color = <LED_COLOR_ID_GREEN>;
98 gpios = <&leds_gpio 1 GPIO_ACTIVE_HIGH>;
99 default-state = "off";
103 function = LED_FUNCTION_STATUS;
104 color = <LED_COLOR_ID_RED>;
106 gpios = <&leds_gpio 2 GPIO_ACTIVE_HIGH>;
107 default-state = "off";
111 function = LED_FUNCTION_STATUS;
112 color = <LED_COLOR_ID_GREEN>;
114 gpios = <&leds_gpio 3 GPIO_ACTIVE_HIGH>;
115 default-state = "off";
119 function = LED_FUNCTION_STATUS;
120 color = <LED_COLOR_ID_RED>;
122 gpios = <&leds_gpio 4 GPIO_ACTIVE_HIGH>;
123 default-state = "off";
127 function = LED_FUNCTION_STATUS;
128 color = <LED_COLOR_ID_GREEN>;
130 gpios = <&leds_gpio 5 GPIO_ACTIVE_HIGH>;
131 default-state = "off";
135 function = LED_FUNCTION_STATUS;
136 color = <LED_COLOR_ID_RED>;
138 gpios = <&leds_gpio 8 GPIO_ACTIVE_HIGH>;
139 default-state = "off";
143 function = LED_FUNCTION_STATUS;
144 color = <LED_COLOR_ID_GREEN>;
146 gpios = <&leds_gpio 9 GPIO_ACTIVE_HIGH>;
147 default-state = "off";
151 function = LED_FUNCTION_STATUS;
152 color = <LED_COLOR_ID_RED>;
154 gpios = <&leds_gpio 10 GPIO_ACTIVE_HIGH>;
155 default-state = "off";
159 function = LED_FUNCTION_STATUS;
160 color = <LED_COLOR_ID_GREEN>;
162 gpios = <&leds_gpio 11 GPIO_ACTIVE_HIGH>;
163 default-state = "off";
167 function = LED_FUNCTION_STATUS;
168 color = <LED_COLOR_ID_RED>;
170 gpios = <&leds_gpio 12 GPIO_ACTIVE_HIGH>;
171 default-state = "off";
175 function = LED_FUNCTION_STATUS;
176 color = <LED_COLOR_ID_GREEN>;
178 gpios = <&leds_gpio 13 GPIO_ACTIVE_HIGH>;
179 default-state = "off";
183 pcie0_refclk: pcie0-refclk {
184 compatible = "fixed-clock";
186 clock-frequency = <100000000>;
189 reg_3p3v: regulator-3p3v {
190 compatible = "regulator-fixed";
191 regulator-name = "3P3V";
192 regulator-min-microvolt = <3300000>;
193 regulator-max-microvolt = <3300000>;
197 pinctrl-names = "default";
198 pinctrl-0 = <&pinctrl_reg_ioexp>;
199 compatible = "regulator-fixed";
200 regulator-name = "ioexp";
201 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
203 startup-delay-us = <100>;
204 regulator-min-microvolt = <3300000>;
205 regulator-max-microvolt = <3300000>;
210 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_reg_isouart>;
212 compatible = "regulator-fixed";
213 regulator-name = "iso_uart";
214 gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
215 startup-delay-us = <100>;
216 regulator-min-microvolt = <3300000>;
217 regulator-max-microvolt = <3300000>;
221 reg_usb2_vbus: regulator-usb2 {
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_reg_usb2>;
224 compatible = "regulator-fixed";
225 regulator-name = "usb_usb2_vbus";
226 gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
228 regulator-min-microvolt = <5000000>;
229 regulator-max-microvolt = <5000000>;
232 reg_wifi: regulator-wifi {
233 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_reg_wl>;
235 compatible = "regulator-fixed";
236 regulator-name = "wifi";
237 gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
239 startup-delay-us = <100>;
240 regulator-min-microvolt = <3300000>;
241 regulator-max-microvolt = <3300000>;
246 operating-points-v2 = <&ddrc_opp_table>;
248 ddrc_opp_table: opp-table {
249 compatible = "operating-points-v2";
252 opp-hz = /bits/ 64 <25000000>;
256 opp-hz = /bits/ 64 <100000000>;
260 opp-hz = /bits/ 64 <750000000>;
270 pinctrl-names = "default";
271 pinctrl-0 = <&pinctrl_spi1>;
272 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
276 compatible = "jedec,spi-nor";
278 spi-max-frequency = <40000000>;
284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_fec1>;
286 phy-mode = "rgmii-id";
287 local-mac-address = [00 00 00 00 00 00];
297 gpio-line-names = "uart1_rs422#", "", "", "uart1_rs485#",
298 "", "uart1_rs232#", "dig1_in", "dig1_out",
299 "", "", "", "", "", "", "", "",
300 "", "", "", "", "", "", "", "",
301 "", "", "", "", "", "", "", "";
305 gpio-line-names = "", "", "", "",
306 "", "", "uart3_rs232#", "uart3_rs422#",
307 "uart3_rs485#", "", "", "", "", "", "", "",
308 "", "", "", "", "", "", "", "",
309 "", "", "", "uart4_rs485#", "", "sim1det#", "sim2det#", "";
313 gpio-line-names = "", "", "", "dig2_out", "dig2_in", "sim2sel", "", "",
314 "", "", "uart4_rs232#", "", "", "uart4_rs422#", "", "",
315 "", "", "", "", "", "", "", "",
316 "", "", "", "", "", "", "", "";
328 clock-frequency = <100000>;
329 pinctrl-names = "default", "gpio";
330 pinctrl-0 = <&pinctrl_i2c1>;
331 pinctrl-1 = <&pinctrl_i2c1_gpio>;
332 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
333 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
337 compatible = "gw,gsc";
339 pinctrl-0 = <&pinctrl_gsc>;
340 interrupt-parent = <&gpio4>;
341 interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
342 interrupt-controller;
343 #interrupt-cells = <1>;
346 compatible = "gw,gsc-adc";
347 #address-cells = <1>;
366 gw,voltage-divider-ohms = <22100 1000>;
373 gw,voltage-divider-ohms = <22100 1000>;
380 gw,voltage-divider-ohms = <22100 1000>;
387 gw,voltage-divider-ohms = <10000 10000>;
394 gw,voltage-divider-ohms = <10000 10000>;
437 gw,voltage-divider-ohms = <10000 10000>;
443 compatible = "nxp,pca9555";
447 interrupt-parent = <&gsc>;
452 compatible = "atmel,24c02";
458 compatible = "atmel,24c02";
464 compatible = "atmel,24c02";
470 compatible = "atmel,24c02";
476 compatible = "dallas,ds1672";
482 clock-frequency = <400000>;
483 pinctrl-names = "default", "gpio";
484 pinctrl-0 = <&pinctrl_i2c2>;
485 pinctrl-1 = <&pinctrl_i2c2_gpio>;
486 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
487 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
491 compatible = "rohm,bd71847";
493 pinctrl-names = "default";
494 pinctrl-0 = <&pinctrl_pmic>;
495 interrupt-parent = <&gpio3>;
496 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
497 rohm,reset-snvs-powered;
499 clocks = <&osc_32k 0>;
500 clock-output-names = "clk-32k-out";
503 /* vdd_soc: 0.805-0.900V (typ=0.8V) */
505 regulator-name = "buck1";
506 regulator-min-microvolt = <700000>;
507 regulator-max-microvolt = <1300000>;
510 regulator-ramp-delay = <1250>;
513 /* vdd_arm: 0.805-1.0V (typ=0.9V) */
515 regulator-name = "buck2";
516 regulator-min-microvolt = <700000>;
517 regulator-max-microvolt = <1300000>;
520 regulator-ramp-delay = <1250>;
521 rohm,dvs-run-voltage = <1000000>;
522 rohm,dvs-idle-voltage = <900000>;
525 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
527 regulator-name = "buck3";
528 regulator-min-microvolt = <700000>;
529 regulator-max-microvolt = <1350000>;
536 regulator-name = "buck4";
537 regulator-min-microvolt = <3000000>;
538 regulator-max-microvolt = <3300000>;
545 regulator-name = "buck5";
546 regulator-min-microvolt = <1605000>;
547 regulator-max-microvolt = <1995000>;
554 regulator-name = "buck6";
555 regulator-min-microvolt = <800000>;
556 regulator-max-microvolt = <1400000>;
563 regulator-name = "ldo1";
564 regulator-min-microvolt = <1600000>;
565 regulator-max-microvolt = <1900000>;
572 regulator-name = "ldo2";
573 regulator-min-microvolt = <800000>;
574 regulator-max-microvolt = <900000>;
581 regulator-name = "ldo3";
582 regulator-min-microvolt = <1800000>;
583 regulator-max-microvolt = <3300000>;
589 regulator-name = "ldo4";
590 regulator-min-microvolt = <900000>;
591 regulator-max-microvolt = <1800000>;
597 regulator-name = "ldo6";
598 regulator-min-microvolt = <900000>;
599 regulator-max-microvolt = <1800000>;
608 clock-frequency = <400000>;
609 pinctrl-names = "default", "gpio";
610 pinctrl-0 = <&pinctrl_i2c3>;
611 pinctrl-1 = <&pinctrl_i2c3_gpio>;
612 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
613 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
617 compatible = "nxp,pca9555";
624 compatible = "microchip,ksz9897";
626 pinctrl-0 = <&pinctrl_ksz>;
627 interrupt-parent = <&gpio4>;
628 interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
629 phy-mode = "rgmii-id";
632 #address-cells = <1>;
638 phy-mode = "internal";
639 local-mac-address = [00 00 00 00 00 00];
645 phy-mode = "internal";
646 local-mac-address = [00 00 00 00 00 00];
652 phy-mode = "internal";
653 local-mac-address = [00 00 00 00 00 00];
659 phy-mode = "internal";
660 local-mac-address = [00 00 00 00 00 00];
667 phy-mode = "rgmii-id";
678 compatible = "atmel,atecc508a";
684 clock-frequency = <400000>;
685 pinctrl-names = "default", "gpio";
686 pinctrl-0 = <&pinctrl_i2c4>;
687 pinctrl-1 = <&pinctrl_i2c4_gpio>;
688 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
689 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
694 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
695 fsl,clkreq-unsupported;
696 clocks = <&pcie0_refclk>;
702 pinctrl-names = "default";
703 pinctrl-0 = <&pinctrl_pcie0>;
704 reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
705 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
707 clock-names = "pcie", "pcie_aux", "pcie_bus";
708 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
709 <&clk IMX8MM_CLK_PCIE1_CTRL>;
710 assigned-clock-rates = <10000000>, <250000000>;
711 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
712 <&clk IMX8MM_SYS_PLL2_250M>;
729 pinctrl-names = "default";
730 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
731 rts-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
732 cts-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
733 dtr-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
734 dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
735 dcd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
742 pinctrl-names = "default";
743 pinctrl-0 = <&pinctrl_uart2>;
748 pinctrl-names = "default";
749 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
750 cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
751 rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
757 pinctrl-names = "default";
758 pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_uart4_gpio>;
759 cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
760 rts-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
767 disable-over-current;
773 vbus-supply = <®_usb2_vbus>;
779 pinctrl-names = "default";
780 pinctrl-0 = <&pinctrl_usdhc1>;
783 vmmc-supply = <®_wifi>;
789 pinctrl-names = "default", "state_100mhz", "state_200mhz";
790 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
791 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
792 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
793 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
795 vmmc-supply = <®_3p3v>;
801 pinctrl-names = "default", "state_100mhz", "state_200mhz";
802 pinctrl-0 = <&pinctrl_usdhc3>;
803 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
804 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
811 pinctrl-names = "default";
812 pinctrl-0 = <&pinctrl_wdog>;
813 fsl,ext-reset-output;
818 pinctrl-names = "default";
819 pinctrl-0 = <&pinctrl_hog>;
821 pinctrl_hog: hoggrp {
823 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* DIG2_OUT */
824 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* DIG2_IN */
825 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* DIG1_IN */
826 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIG1_OUT */
827 MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x40000041 /* SIM2DET# */
828 MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x40000041 /* SIM1DET# */
829 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* SIM2SEL */
833 pinctrl_fec1: fec1grp {
835 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
836 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
837 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
838 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
839 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
840 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
841 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
842 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
843 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
844 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
845 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
846 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
847 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
848 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
849 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* IRQ# */
850 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* RST# */
854 pinctrl_gsc: gscgrp {
856 MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x159
860 pinctrl_i2c1: i2c1grp {
862 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
863 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
867 pinctrl_i2c1_gpio: i2c1gpiogrp {
869 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
870 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
874 pinctrl_i2c2: i2c2grp {
876 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
877 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
881 pinctrl_i2c2_gpio: i2c2gpiogrp {
883 MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
884 MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
888 pinctrl_i2c3: i2c3grp {
890 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
891 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
895 pinctrl_i2c3_gpio: i2c3gpiogrp {
897 MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
898 MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
902 pinctrl_i2c4: i2c4grp {
904 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
905 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
909 pinctrl_i2c4_gpio: i2c4gpiogrp {
911 MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3
912 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3
916 pinctrl_ksz: kszgrp {
918 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x41
919 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x41 /* RST# */
923 pinctrl_pcie0: pciegrp {
925 MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x40000041 /* WDIS# */
926 MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x41
930 pinctrl_pmic: pmicgrp {
932 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41
936 pinctrl_reg_isouart: regisouartgrp {
938 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041
942 pinctrl_reg_ioexp: regioexpgrp {
944 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041
948 pinctrl_reg_wl: regwlgrp {
950 MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x40000041
954 pinctrl_reg_usb2: regusb1grp {
956 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x41
957 MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x140
958 MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x140
962 pinctrl_spi1: spi1grp {
964 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
965 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
966 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
967 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140
971 pinctrl_uart1: uart1grp {
973 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
974 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
975 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140
976 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140
977 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x140
978 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x140
979 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x140
983 pinctrl_uart1_gpio: uart1gpiogrp {
985 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000041 /* RS422# */
986 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000041 /* RS485# */
987 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x40000041 /* RS232# */
991 pinctrl_uart2: uart2grp {
993 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
994 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
998 pinctrl_uart3: uart3grp {
1000 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
1001 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
1002 MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x140
1003 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140
1007 pinctrl_uart3_gpio: uart3gpiogrp {
1009 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000110 /* RS232# */
1010 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000110 /* RS422# */
1011 MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000110 /* RS485# */
1015 pinctrl_uart4: uart4grp {
1017 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
1018 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
1019 MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x140
1020 MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x140
1024 pinctrl_uart4_gpio: uart4gpiogrp {
1027 MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x40000041 /* RS232# */
1028 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000041 /* RS422# */
1029 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* RS485# */
1033 pinctrl_usdhc1: usdhc1grp {
1035 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
1036 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
1037 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
1038 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
1039 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
1040 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
1044 pinctrl_usdhc2: usdhc2grp {
1046 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
1047 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
1048 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
1049 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
1050 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
1051 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
1055 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1057 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
1058 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
1059 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
1060 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
1061 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
1062 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
1066 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1068 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
1069 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
1070 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
1071 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
1072 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
1073 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
1077 pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
1079 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
1080 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
1084 pinctrl_usdhc3: usdhc3grp {
1086 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
1087 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
1088 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
1089 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
1090 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
1091 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
1092 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
1093 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
1094 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
1095 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
1096 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
1100 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1102 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
1103 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
1104 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
1105 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
1106 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
1107 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
1108 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
1109 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
1110 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
1111 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
1112 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
1116 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1118 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
1119 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
1120 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
1121 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
1122 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
1123 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
1124 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
1125 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
1126 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
1127 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
1128 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
1132 pinctrl_wdog: wdoggrp {
1134 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6