1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2020 Gateworks Corporation
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/net/ti-dp83867.h>
12 device_type = "memory";
13 reg = <0x0 0x40000000 0 0x80000000>;
17 compatible = "gpio-keys";
21 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
28 interrupt-parent = <&gsc>;
35 interrupt-parent = <&gsc>;
42 interrupt-parent = <&gsc>;
49 interrupt-parent = <&gsc>;
54 label = "switch_hold";
56 interrupt-parent = <&gsc>;
63 cpu-supply = <&buck3_reg>;
67 cpu-supply = <&buck3_reg>;
71 cpu-supply = <&buck3_reg>;
75 cpu-supply = <&buck3_reg>;
79 operating-points-v2 = <&ddrc_opp_table>;
81 ddrc_opp_table: opp-table {
82 compatible = "operating-points-v2";
85 opp-hz = /bits/ 64 <25000000>;
89 opp-hz = /bits/ 64 <100000000>;
93 opp-hz = /bits/ 64 <750000000>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_fec1>;
101 phy-mode = "rgmii-id";
102 phy-handle = <ðphy0>;
106 #address-cells = <1>;
109 ethphy0: ethernet-phy@0 {
110 compatible = "ethernet-phy-ieee802.3-c22";
112 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
113 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
114 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
115 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
121 clock-frequency = <100000>;
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_i2c1>;
127 compatible = "gw,gsc";
129 pinctrl-0 = <&pinctrl_gsc>;
130 interrupt-parent = <&gpio2>;
131 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
132 interrupt-controller;
133 #interrupt-cells = <1>;
134 #address-cells = <1>;
138 compatible = "gw,gsc-adc";
139 #address-cells = <1>;
164 gw,voltage-divider-ohms = <22100 1000>;
171 gw,voltage-divider-ohms = <10000 10000>;
178 gw,voltage-divider-ohms = <10000 10000>;
203 gw,voltage-divider-ohms = <10000 10000>;
210 gw,voltage-divider-ohms = <10000 10000>;
229 gw,voltage-divider-ohms = <10000 10000>;
234 #address-cells = <1>;
236 compatible = "gw,gsc-fan";
242 compatible = "nxp,pca9555";
246 interrupt-parent = <&gsc>;
251 compatible = "atmel,24c02";
257 compatible = "atmel,24c02";
263 compatible = "atmel,24c02";
269 compatible = "atmel,24c02";
275 compatible = "dallas,ds1672";
280 compatible = "mps,mp5416";
281 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_pmic>;
287 regulator-name = "vdd_0p95";
288 regulator-min-microvolt = <805000>;
289 regulator-max-microvolt = <1000000>;
290 regulator-max-microamp = <2500000>;
295 regulator-name = "vdd_soc";
296 regulator-min-microvolt = <805000>;
297 regulator-max-microvolt = <900000>;
298 regulator-max-microamp = <1000000>;
303 regulator-name = "vdd_arm";
304 regulator-min-microvolt = <805000>;
305 regulator-max-microvolt = <1000000>;
306 regulator-max-microamp = <2200000>;
311 regulator-name = "vdd_1p8";
312 regulator-min-microvolt = <1800000>;
313 regulator-max-microvolt = <1800000>;
314 regulator-max-microamp = <500000>;
319 regulator-name = "nvcc_snvs_1p8";
320 regulator-min-microvolt = <1800000>;
321 regulator-max-microvolt = <1800000>;
322 regulator-max-microamp = <300000>;
327 regulator-name = "vdd_snvs_0p8";
328 regulator-min-microvolt = <800000>;
329 regulator-max-microvolt = <800000>;
334 regulator-name = "vdd_0p95";
335 regulator-min-microvolt = <800000>;
336 regulator-max-microvolt = <800000>;
341 regulator-name = "vdd_1p8";
342 regulator-min-microvolt = <1800000>;
343 regulator-max-microvolt = <1800000>;
351 clock-frequency = <400000>;
352 pinctrl-names = "default";
353 pinctrl-0 = <&pinctrl_i2c2>;
357 compatible = "atmel,24c32";
365 pinctrl-names = "default";
366 pinctrl-0 = <&pinctrl_uart2>;
372 pinctrl-names = "default", "state_100mhz", "state_200mhz";
373 pinctrl-0 = <&pinctrl_usdhc3>;
374 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
375 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
382 pinctrl-names = "default";
383 pinctrl-0 = <&pinctrl_wdog>;
384 fsl,ext-reset-output;
389 pinctrl_fec1: fec1grp {
391 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
392 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
393 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
394 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
395 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
396 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
397 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
398 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
399 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
400 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
401 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
402 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
403 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
404 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
405 MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x19
409 pinctrl_gsc: gscgrp {
411 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x159
415 pinctrl_i2c1: i2c1grp {
417 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
418 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
422 pinctrl_i2c2: i2c2grp {
424 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
425 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
429 pinctrl_pmic: pmicgrp {
431 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
435 pinctrl_uart2: uart2grp {
437 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
438 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
442 pinctrl_usdhc3: usdhc3grp {
444 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
445 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
446 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
447 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
448 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
449 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
450 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
451 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
452 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
453 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
454 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
458 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
460 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
461 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
462 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
463 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
464 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
465 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
466 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
467 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
468 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
469 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
470 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
474 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
476 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
477 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
478 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
479 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
480 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
481 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
482 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
483 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
484 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
485 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
486 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
490 pinctrl_wdog: wdoggrp {
492 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6