1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/usb/pd.h>
12 model = "FSL i.MX8MM EVK board";
13 compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
20 device_type = "memory";
21 reg = <0x0 0x40000000 0 0x80000000>;
25 compatible = "gpio-leds";
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_gpio_led>;
31 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
36 reg_usdhc2_vmmc: regulator-usdhc2 {
37 compatible = "regulator-fixed";
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
40 regulator-name = "VSD_3V3";
41 regulator-min-microvolt = <3300000>;
42 regulator-max-microvolt = <3300000>;
43 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
48 #sound-dai-cells = <0>;
49 compatible = "wlf,wm8524";
50 pinctrl-names = "default";
51 pinctrl-0 = <&pinctrl_gpio_wlf>;
52 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
56 compatible = "simple-audio-card";
57 simple-audio-card,name = "wm8524-audio";
58 simple-audio-card,format = "i2s";
59 simple-audio-card,frame-master = <&cpudai>;
60 simple-audio-card,bitclock-master = <&cpudai>;
61 simple-audio-card,widgets =
62 "Line", "Left Line Out Jack",
63 "Line", "Right Line Out Jack";
64 simple-audio-card,routing =
65 "Left Line Out Jack", "LINEVOUTL",
66 "Right Line Out Jack", "LINEVOUTR";
68 cpudai: simple-audio-card,cpu {
70 dai-tdm-slot-num = <2>;
71 dai-tdm-slot-width = <32>;
74 simple-audio-card,codec {
75 sound-dai = <&wm8524>;
76 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
82 cpu-supply = <&buck2_reg>;
86 cpu-supply = <&buck2_reg>;
90 cpu-supply = <&buck2_reg>;
94 cpu-supply = <&buck2_reg>;
98 operating-points-v2 = <&ddrc_opp_table>;
100 ddrc_opp_table: opp-table {
101 compatible = "operating-points-v2";
104 opp-hz = /bits/ 64 <25000000>;
108 opp-hz = /bits/ 64 <100000000>;
112 opp-hz = /bits/ 64 <750000000>;
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_fec1>;
120 phy-mode = "rgmii-id";
121 phy-handle = <ðphy0>;
122 phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
123 phy-reset-duration = <10>;
128 #address-cells = <1>;
131 ethphy0: ethernet-phy@0 {
132 compatible = "ethernet-phy-ieee802.3-c22";
139 clock-frequency = <400000>;
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_i2c1>;
145 compatible = "rohm,bd71847";
147 pinctrl-0 = <&pinctrl_pmic>;
148 interrupt-parent = <&gpio1>;
149 interrupts = <3 GPIO_ACTIVE_LOW>;
150 rohm,reset-snvs-powered;
154 regulator-name = "BUCK1";
155 regulator-min-microvolt = <700000>;
156 regulator-max-microvolt = <1300000>;
159 regulator-ramp-delay = <1250>;
163 regulator-name = "BUCK2";
164 regulator-min-microvolt = <700000>;
165 regulator-max-microvolt = <1300000>;
168 regulator-ramp-delay = <1250>;
169 rohm,dvs-run-voltage = <1000000>;
170 rohm,dvs-idle-voltage = <900000>;
174 // BUCK5 in datasheet
175 regulator-name = "BUCK3";
176 regulator-min-microvolt = <700000>;
177 regulator-max-microvolt = <1350000>;
183 // BUCK6 in datasheet
184 regulator-name = "BUCK4";
185 regulator-min-microvolt = <3000000>;
186 regulator-max-microvolt = <3300000>;
192 // BUCK7 in datasheet
193 regulator-name = "BUCK5";
194 regulator-min-microvolt = <1605000>;
195 regulator-max-microvolt = <1995000>;
201 // BUCK8 in datasheet
202 regulator-name = "BUCK6";
203 regulator-min-microvolt = <800000>;
204 regulator-max-microvolt = <1400000>;
210 regulator-name = "LDO1";
211 regulator-min-microvolt = <1600000>;
212 regulator-max-microvolt = <3300000>;
218 regulator-name = "LDO2";
219 regulator-min-microvolt = <800000>;
220 regulator-max-microvolt = <900000>;
226 regulator-name = "LDO3";
227 regulator-min-microvolt = <1800000>;
228 regulator-max-microvolt = <3300000>;
234 regulator-name = "LDO4";
235 regulator-min-microvolt = <900000>;
236 regulator-max-microvolt = <1800000>;
242 regulator-name = "LDO6";
243 regulator-min-microvolt = <900000>;
244 regulator-max-microvolt = <1800000>;
253 clock-frequency = <400000>;
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_i2c2>;
259 compatible = "nxp,ptn5110";
260 pinctrl-names = "default";
261 pinctrl-0 = <&pinctrl_typec1>;
263 interrupt-parent = <&gpio2>;
268 typec1_dr_sw: endpoint {
269 remote-endpoint = <&usb1_drd_sw>;
273 typec1_con: connector {
274 compatible = "usb-c-connector";
278 try-power-role = "sink";
279 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
280 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
281 PDO_VAR(5000, 20000, 3000)>;
282 op-sink-microwatt = <15000000>;
289 clock-frequency = <400000>;
290 pinctrl-names = "default";
291 pinctrl-0 = <&pinctrl_i2c3>;
295 compatible = "ti,tca6416";
303 pinctrl-names = "default";
304 pinctrl-0 = <&pinctrl_sai3>;
305 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
306 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
307 assigned-clock-rates = <24576000>;
315 &uart2 { /* console */
316 pinctrl-names = "default";
317 pinctrl-0 = <&pinctrl_uart2>;
330 usb1_drd_sw: endpoint {
331 remote-endpoint = <&typec1_dr_sw>;
337 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
338 assigned-clock-rates = <200000000>;
339 pinctrl-names = "default", "state_100mhz", "state_200mhz";
340 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
341 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
342 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
343 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
345 vmmc-supply = <®_usdhc2_vmmc>;
350 assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
351 assigned-clock-rates = <400000000>;
352 pinctrl-names = "default", "state_100mhz", "state_200mhz";
353 pinctrl-0 = <&pinctrl_usdhc3>;
354 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
355 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
362 pinctrl-names = "default";
363 pinctrl-0 = <&pinctrl_wdog>;
364 fsl,ext-reset-output;
369 pinctrl-names = "default";
371 pinctrl_fec1: fec1grp {
373 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
374 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
375 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
376 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
377 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
378 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
379 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
380 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
381 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
382 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
383 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
384 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
385 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
386 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
387 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
391 pinctrl_gpio_led: gpioledgrp {
393 MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
397 pinctrl_gpio_wlf: gpiowlfgrp {
399 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6
403 pinctrl_i2c1: i2c1grp {
405 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
406 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
410 pinctrl_i2c2: i2c2grp {
412 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
413 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
417 pinctrl_i2c3: i2c3grp {
419 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
420 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
424 pinctrl_pmic: pmicirq {
426 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
430 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
432 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
436 pinctrl_sai3: sai3grp {
438 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
439 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
440 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
441 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
445 pinctrl_typec1: typec1grp {
447 MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
451 pinctrl_uart2: uart2grp {
453 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
454 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
458 pinctrl_usdhc2_gpio: usdhc2grpgpio {
460 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
464 pinctrl_usdhc2: usdhc2grp {
466 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
467 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
468 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
469 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
470 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
471 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
472 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
476 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
478 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
479 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
480 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
481 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
482 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
483 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
484 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
488 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
490 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
491 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
492 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
493 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
494 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
495 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
496 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
500 pinctrl_usdhc3: usdhc3grp {
502 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
503 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
504 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
505 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
506 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
507 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
508 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
509 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
510 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
511 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
512 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
516 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
518 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
519 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
520 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
521 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
522 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
523 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
524 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
525 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
526 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
527 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
528 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
532 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
534 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
535 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
536 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
537 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
538 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
539 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
540 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
541 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
542 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
543 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
544 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
548 pinctrl_wdog: wdoggrp {
550 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6