1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2020 NXP
4 * Dong Aisheng <aisheng.dong@nxp.com>
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
10 lsio_subsys: bus@5d000000 {
11 compatible = "simple-bus";
14 ranges = <0x5d000000 0x0 0x5d000000 0x1000000>;
16 lsio_mem_clk: clock-lsio-mem {
17 compatible = "fixed-clock";
19 clock-frequency = <200000000>;
20 clock-output-names = "lsio_mem_clk";
23 lsio_bus_clk: clock-lsio-bus {
24 compatible = "fixed-clock";
26 clock-frequency = <100000000>;
27 clock-output-names = "lsio_bus_clk";
30 lsio_gpio0: gpio@5d080000 {
31 reg = <0x5d080000 0x10000>;
32 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
36 #interrupt-cells = <2>;
37 power-domains = <&pd IMX_SC_R_GPIO_0>;
40 lsio_gpio1: gpio@5d090000 {
41 reg = <0x5d090000 0x10000>;
42 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
46 #interrupt-cells = <2>;
47 power-domains = <&pd IMX_SC_R_GPIO_1>;
50 lsio_gpio2: gpio@5d0a0000 {
51 reg = <0x5d0a0000 0x10000>;
52 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
56 #interrupt-cells = <2>;
57 power-domains = <&pd IMX_SC_R_GPIO_2>;
60 lsio_gpio3: gpio@5d0b0000 {
61 reg = <0x5d0b0000 0x10000>;
62 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
66 #interrupt-cells = <2>;
67 power-domains = <&pd IMX_SC_R_GPIO_3>;
70 lsio_gpio4: gpio@5d0c0000 {
71 reg = <0x5d0c0000 0x10000>;
72 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
76 #interrupt-cells = <2>;
77 power-domains = <&pd IMX_SC_R_GPIO_4>;
80 lsio_gpio5: gpio@5d0d0000 {
81 reg = <0x5d0d0000 0x10000>;
82 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
86 #interrupt-cells = <2>;
87 power-domains = <&pd IMX_SC_R_GPIO_5>;
90 lsio_gpio6: gpio@5d0e0000 {
91 reg = <0x5d0e0000 0x10000>;
92 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
96 #interrupt-cells = <2>;
97 power-domains = <&pd IMX_SC_R_GPIO_6>;
100 lsio_gpio7: gpio@5d0f0000 {
101 reg = <0x5d0f0000 0x10000>;
102 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
105 interrupt-controller;
106 #interrupt-cells = <2>;
107 power-domains = <&pd IMX_SC_R_GPIO_7>;
110 lsio_mu0: mailbox@5d1b0000 {
111 reg = <0x5d1b0000 0x10000>;
112 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
117 lsio_mu1: mailbox@5d1c0000 {
118 reg = <0x5d1c0000 0x10000>;
119 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
123 lsio_mu2: mailbox@5d1d0000 {
124 reg = <0x5d1d0000 0x10000>;
125 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
130 lsio_mu3: mailbox@5d1e0000 {
131 reg = <0x5d1e0000 0x10000>;
132 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
137 lsio_mu4: mailbox@5d1f0000 {
138 reg = <0x5d1f0000 0x10000>;
139 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
144 lsio_mu13: mailbox@5d280000 {
145 reg = <0x5d280000 0x10000>;
146 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
148 power-domains = <&pd IMX_SC_R_MU_13A>;
152 pwm0_lpcg: clock-controller@5d400000 {
153 compatible = "fsl,imx8qxp-lpcg";
154 reg = <0x5d400000 0x10000>;
156 clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
157 <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
158 <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
160 <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
161 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
162 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
164 clock-output-names = "pwm0_lpcg_ipg_clk",
165 "pwm0_lpcg_ipg_hf_clk",
166 "pwm0_lpcg_ipg_s_clk",
167 "pwm0_lpcg_ipg_slv_clk",
168 "pwm0_lpcg_ipg_mstr_clk";
169 power-domains = <&pd IMX_SC_R_PWM_0>;
172 pwm1_lpcg: clock-controller@5d410000 {
173 compatible = "fsl,imx8qxp-lpcg";
174 reg = <0x5d410000 0x10000>;
176 clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
177 <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
178 <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
180 <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
181 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
182 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
184 clock-output-names = "pwm1_lpcg_ipg_clk",
185 "pwm1_lpcg_ipg_hf_clk",
186 "pwm1_lpcg_ipg_s_clk",
187 "pwm1_lpcg_ipg_slv_clk",
188 "pwm1_lpcg_ipg_mstr_clk";
189 power-domains = <&pd IMX_SC_R_PWM_1>;
192 pwm2_lpcg: clock-controller@5d420000 {
193 compatible = "fsl,imx8qxp-lpcg";
194 reg = <0x5d420000 0x10000>;
196 clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
197 <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
198 <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
200 <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
201 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
202 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
204 clock-output-names = "pwm2_lpcg_ipg_clk",
205 "pwm2_lpcg_ipg_hf_clk",
206 "pwm2_lpcg_ipg_s_clk",
207 "pwm2_lpcg_ipg_slv_clk",
208 "pwm2_lpcg_ipg_mstr_clk";
209 power-domains = <&pd IMX_SC_R_PWM_2>;
212 pwm3_lpcg: clock-controller@5d430000 {
213 compatible = "fsl,imx8qxp-lpcg";
214 reg = <0x5d430000 0x10000>;
216 clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
217 <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
218 <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
220 <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
221 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
222 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
224 clock-output-names = "pwm3_lpcg_ipg_clk",
225 "pwm3_lpcg_ipg_hf_clk",
226 "pwm3_lpcg_ipg_s_clk",
227 "pwm3_lpcg_ipg_slv_clk",
228 "pwm3_lpcg_ipg_mstr_clk";
229 power-domains = <&pd IMX_SC_R_PWM_3>;
232 pwm4_lpcg: clock-controller@5d440000 {
233 compatible = "fsl,imx8qxp-lpcg";
234 reg = <0x5d440000 0x10000>;
236 clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
237 <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
238 <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
240 <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>;
241 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
242 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
244 clock-output-names = "pwm4_lpcg_ipg_clk",
245 "pwm4_lpcg_ipg_hf_clk",
246 "pwm4_lpcg_ipg_s_clk",
247 "pwm4_lpcg_ipg_slv_clk",
248 "pwm4_lpcg_ipg_mstr_clk";
249 power-domains = <&pd IMX_SC_R_PWM_4>;
252 pwm5_lpcg: clock-controller@5d450000 {
253 compatible = "fsl,imx8qxp-lpcg";
254 reg = <0x5d450000 0x10000>;
256 clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
257 <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
258 <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
260 <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>;
261 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
262 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
264 clock-output-names = "pwm5_lpcg_ipg_clk",
265 "pwm5_lpcg_ipg_hf_clk",
266 "pwm5_lpcg_ipg_s_clk",
267 "pwm5_lpcg_ipg_slv_clk",
268 "pwm5_lpcg_ipg_mstr_clk";
269 power-domains = <&pd IMX_SC_R_PWM_5>;
272 pwm6_lpcg: clock-controller@5d460000 {
273 compatible = "fsl,imx8qxp-lpcg";
274 reg = <0x5d460000 0x10000>;
276 clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
277 <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
278 <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
280 <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>;
281 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
282 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
284 clock-output-names = "pwm6_lpcg_ipg_clk",
285 "pwm6_lpcg_ipg_hf_clk",
286 "pwm6_lpcg_ipg_s_clk",
287 "pwm6_lpcg_ipg_slv_clk",
288 "pwm6_lpcg_ipg_mstr_clk";
289 power-domains = <&pd IMX_SC_R_PWM_6>;
292 pwm7_lpcg: clock-controller@5d470000 {
293 compatible = "fsl,imx8qxp-lpcg";
294 reg = <0x5d470000 0x10000>;
296 clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
297 <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
298 <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
300 <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>;
301 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
302 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
304 clock-output-names = "pwm7_lpcg_ipg_clk",
305 "pwm7_lpcg_ipg_hf_clk",
306 "pwm7_lpcg_ipg_s_clk",
307 "pwm7_lpcg_ipg_slv_clk",
308 "pwm7_lpcg_ipg_mstr_clk";
309 power-domains = <&pd IMX_SC_R_PWM_7>;