arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018-2020 NXP
   4  *      Dong Aisheng <aisheng.dong@nxp.com>
   5  */
   6
   7 #include <dt-bindings/clock/imx8-lpcg.h>
   8 #include <dt-bindings/firmware/imx/rsrc.h>
   9
  10 lsio_bus_clk: clock-lsio-bus {
  11         compatible = "fixed-clock";
  12         #clock-cells = <0>;
  13         clock-frequency = <100000000>;
  14         clock-output-names = "lsio_bus_clk";
  15 };
  16
  17 lsio_subsys: bus@5d000000 {
  18         compatible = "simple-bus";
  19         #address-cells = <1>;
  20         #size-cells = <1>;
  21         ranges = <0x5d000000 0x0 0x5d000000 0x1000000>,
  22                  <0x08000000 0x0 0x08000000 0x10000000>;
  23
  24         lsio_pwm0: pwm@5d000000 {
  25                 compatible = "fsl,imx27-pwm";
  26                 reg = <0x5d000000 0x10000>;
  27                 clock-names = "ipg", "per";
  28                 clocks = <&pwm0_lpcg 4>,
  29                          <&pwm0_lpcg 1>;
  30                 assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
  31                 assigned-clock-rates = <24000000>;
  32                 #pwm-cells = <2>;
  33                 status = "disabled";
  34         };
  35
  36         lsio_pwm1: pwm@5d010000 {
  37                 compatible = "fsl,imx27-pwm";
  38                 reg = <0x5d010000 0x10000>;
  39                 clock-names = "ipg", "per";
  40                 clocks = <&pwm1_lpcg 4>,
  41                          <&pwm1_lpcg 1>;
  42                 assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
  43                 assigned-clock-rates = <24000000>;
  44                 #pwm-cells = <2>;
  45                 status = "disabled";
  46         };
  47
  48         lsio_pwm2: pwm@5d020000 {
  49                 compatible = "fsl,imx27-pwm";
  50                 reg = <0x5d020000 0x10000>;
  51                 clock-names = "ipg", "per";
  52                 clocks = <&pwm2_lpcg 4>,
  53                          <&pwm2_lpcg 1>;
  54                 assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
  55                 assigned-clock-rates = <24000000>;
  56                 #pwm-cells = <2>;
  57                 status = "disabled";
  58         };
  59
  60         lsio_pwm3: pwm@5d030000 {
  61                 compatible = "fsl,imx27-pwm";
  62                 reg = <0x5d030000 0x10000>;
  63                 clock-names = "ipg", "per";
  64                 clocks = <&pwm3_lpcg 4>,
  65                          <&pwm3_lpcg 1>;
  66                 assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
  67                 assigned-clock-rates = <24000000>;
  68                 #pwm-cells = <2>;
  69                 status = "disabled";
  70         };
  71
  72         lsio_gpio0: gpio@5d080000 {
  73                 reg = <0x5d080000 0x10000>;
  74                 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
  75                 gpio-controller;
  76                 #gpio-cells = <2>;
  77                 interrupt-controller;
  78                 #interrupt-cells = <2>;
  79                 power-domains = <&pd IMX_SC_R_GPIO_0>;
  80         };
  81
  82         lsio_gpio1: gpio@5d090000 {
  83                 reg = <0x5d090000 0x10000>;
  84                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
  85                 gpio-controller;
  86                 #gpio-cells = <2>;
  87                 interrupt-controller;
  88                 #interrupt-cells = <2>;
  89                 power-domains = <&pd IMX_SC_R_GPIO_1>;
  90         };
  91
  92         lsio_gpio2: gpio@5d0a0000 {
  93                 reg = <0x5d0a0000 0x10000>;
  94                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
  95                 gpio-controller;
  96                 #gpio-cells = <2>;
  97                 interrupt-controller;
  98                 #interrupt-cells = <2>;
  99                 power-domains = <&pd IMX_SC_R_GPIO_2>;
 100         };
 101
 102         lsio_gpio3: gpio@5d0b0000 {
 103                 reg = <0x5d0b0000 0x10000>;
 104                 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 105                 gpio-controller;
 106                 #gpio-cells = <2>;
 107                 interrupt-controller;
 108                 #interrupt-cells = <2>;
 109                 power-domains = <&pd IMX_SC_R_GPIO_3>;
 110         };
 111
 112         lsio_gpio4: gpio@5d0c0000 {
 113                 reg = <0x5d0c0000 0x10000>;
 114                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 115                 gpio-controller;
 116                 #gpio-cells = <2>;
 117                 interrupt-controller;
 118                 #interrupt-cells = <2>;
 119                 power-domains = <&pd IMX_SC_R_GPIO_4>;
 120         };
 121
 122         lsio_gpio5: gpio@5d0d0000 {
 123                 reg = <0x5d0d0000 0x10000>;
 124                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 125                 gpio-controller;
 126                 #gpio-cells = <2>;
 127                 interrupt-controller;
 128                 #interrupt-cells = <2>;
 129                 power-domains = <&pd IMX_SC_R_GPIO_5>;
 130         };
 131
 132         lsio_gpio6: gpio@5d0e0000 {
 133                 reg = <0x5d0e0000 0x10000>;
 134                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 135                 gpio-controller;
 136                 #gpio-cells = <2>;
 137                 interrupt-controller;
 138                 #interrupt-cells = <2>;
 139                 power-domains = <&pd IMX_SC_R_GPIO_6>;
 140         };
 141
 142         lsio_gpio7: gpio@5d0f0000 {
 143                 reg = <0x5d0f0000 0x10000>;
 144                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 145                 gpio-controller;
 146                 #gpio-cells = <2>;
 147                 interrupt-controller;
 148                 #interrupt-cells = <2>;
 149                 power-domains = <&pd IMX_SC_R_GPIO_7>;
 150         };
 151
 152         flexspi0: spi@5d120000 {
 153                 #address-cells = <1>;
 154                 #size-cells = <0>;
 155                 compatible = "nxp,imx8qxp-fspi";
 156                 reg = <0x5d120000 0x10000>, <0x08000000 0x10000000>;
 157                 reg-names = "fspi_base", "fspi_mmap";
 158                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 159                 clocks = <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>,
 160                          <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>;
 161                 clock-names = "fspi_en", "fspi";
 162                 power-domains = <&pd IMX_SC_R_FSPI_0>;
 163                 status = "disabled";
 164         };
 165
 166         lsio_mu0: mailbox@5d1b0000 {
 167                 reg = <0x5d1b0000 0x10000>;
 168                 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
 169                 #mbox-cells = <2>;
 170                 status = "disabled";
 171         };
 172
 173         lsio_mu1: mailbox@5d1c0000 {
 174                 reg = <0x5d1c0000 0x10000>;
 175                 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
 176                 #mbox-cells = <2>;
 177         };
 178
 179         lsio_mu2: mailbox@5d1d0000 {
 180                 reg = <0x5d1d0000 0x10000>;
 181                 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
 182                 #mbox-cells = <2>;
 183                 status = "disabled";
 184         };
 185
 186         lsio_mu3: mailbox@5d1e0000 {
 187                 reg = <0x5d1e0000 0x10000>;
 188                 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
 189                 #mbox-cells = <2>;
 190                 status = "disabled";
 191         };
 192
 193         lsio_mu4: mailbox@5d1f0000 {
 194                 reg = <0x5d1f0000 0x10000>;
 195                 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
 196                 #mbox-cells = <2>;
 197                 status = "disabled";
 198         };
 199
 200         lsio_mu5: mailbox@5d200000 {
 201                 reg = <0x5d200000 0x10000>;
 202                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 203                 #mbox-cells = <2>;
 204                 power-domains = <&pd IMX_SC_R_MU_5A>;
 205                 status = "disabled";
 206         };
 207
 208         lsio_mu6: mailbox@5d210000 {
 209                 reg = <0x5d210000 0x10000>;
 210                 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
 211                 #mbox-cells = <2>;
 212                 power-domains = <&pd IMX_SC_R_MU_6A>;
 213                 status = "disabled";
 214         };
 215
 216         lsio_mu13: mailbox@5d280000 {
 217                 reg = <0x5d280000 0x10000>;
 218                 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
 219                 #mbox-cells = <2>;
 220                 power-domains = <&pd IMX_SC_R_MU_13A>;
 221         };
 222
 223         /* LPCG clocks */
 224         pwm0_lpcg: clock-controller@5d400000 {
 225                 compatible = "fsl,imx8qxp-lpcg";
 226                 reg = <0x5d400000 0x10000>;
 227                 #clock-cells = <1>;
 228                 clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
 229                          <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
 230                          <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
 231                          <&lsio_bus_clk>,
 232                          <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
 233                 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
 234                                 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
 235                                 <IMX_LPCG_CLK_6>;
 236                 clock-output-names = "pwm0_lpcg_ipg_clk",
 237                                      "pwm0_lpcg_ipg_hf_clk",
 238                                      "pwm0_lpcg_ipg_s_clk",
 239                                      "pwm0_lpcg_ipg_slv_clk",
 240                                      "pwm0_lpcg_ipg_mstr_clk";
 241                 power-domains = <&pd IMX_SC_R_PWM_0>;
 242         };
 243
 244         pwm1_lpcg: clock-controller@5d410000 {
 245                 compatible = "fsl,imx8qxp-lpcg";
 246                 reg = <0x5d410000 0x10000>;
 247                 #clock-cells = <1>;
 248                 clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
 249                          <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
 250                          <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
 251                          <&lsio_bus_clk>,
 252                          <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
 253                 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
 254                                 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
 255                                 <IMX_LPCG_CLK_6>;
 256                 clock-output-names = "pwm1_lpcg_ipg_clk",
 257                                      "pwm1_lpcg_ipg_hf_clk",
 258                                      "pwm1_lpcg_ipg_s_clk",
 259                                      "pwm1_lpcg_ipg_slv_clk",
 260                                      "pwm1_lpcg_ipg_mstr_clk";
 261                 power-domains = <&pd IMX_SC_R_PWM_1>;
 262         };
 263
 264         pwm2_lpcg: clock-controller@5d420000 {
 265                 compatible = "fsl,imx8qxp-lpcg";
 266                 reg = <0x5d420000 0x10000>;
 267                 #clock-cells = <1>;
 268                 clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
 269                          <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
 270                          <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
 271                          <&lsio_bus_clk>,
 272                          <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
 273                 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
 274                                 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
 275                                 <IMX_LPCG_CLK_6>;
 276                 clock-output-names = "pwm2_lpcg_ipg_clk",
 277                                      "pwm2_lpcg_ipg_hf_clk",
 278                                      "pwm2_lpcg_ipg_s_clk",
 279                                      "pwm2_lpcg_ipg_slv_clk",
 280                                      "pwm2_lpcg_ipg_mstr_clk";
 281                 power-domains = <&pd IMX_SC_R_PWM_2>;
 282         };
 283
 284         pwm3_lpcg: clock-controller@5d430000 {
 285                 compatible = "fsl,imx8qxp-lpcg";
 286                 reg = <0x5d430000 0x10000>;
 287                 #clock-cells = <1>;
 288                 clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
 289                          <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
 290                          <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
 291                          <&lsio_bus_clk>,
 292                          <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
 293                 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
 294                                 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
 295                                 <IMX_LPCG_CLK_6>;
 296                 clock-output-names = "pwm3_lpcg_ipg_clk",
 297                                      "pwm3_lpcg_ipg_hf_clk",
 298                                      "pwm3_lpcg_ipg_s_clk",
 299                                      "pwm3_lpcg_ipg_slv_clk",
 300                                      "pwm3_lpcg_ipg_mstr_clk";
 301                 power-domains = <&pd IMX_SC_R_PWM_3>;
 302         };
 303
 304         pwm4_lpcg: clock-controller@5d440000 {
 305                 compatible = "fsl,imx8qxp-lpcg";
 306                 reg = <0x5d440000 0x10000>;
 307                 #clock-cells = <1>;
 308                 clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
 309                          <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
 310                          <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
 311                          <&lsio_bus_clk>,
 312                          <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>;
 313                 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
 314                                 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
 315                                 <IMX_LPCG_CLK_6>;
 316                 clock-output-names = "pwm4_lpcg_ipg_clk",
 317                                      "pwm4_lpcg_ipg_hf_clk",
 318                                      "pwm4_lpcg_ipg_s_clk",
 319                                      "pwm4_lpcg_ipg_slv_clk",
 320                                      "pwm4_lpcg_ipg_mstr_clk";
 321                 power-domains = <&pd IMX_SC_R_PWM_4>;
 322         };
 323
 324         pwm5_lpcg: clock-controller@5d450000 {
 325                 compatible = "fsl,imx8qxp-lpcg";
 326                 reg = <0x5d450000 0x10000>;
 327                 #clock-cells = <1>;
 328                 clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
 329                          <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
 330                          <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
 331                          <&lsio_bus_clk>,
 332                          <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>;
 333                 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
 334                                 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
 335                                 <IMX_LPCG_CLK_6>;
 336                 clock-output-names = "pwm5_lpcg_ipg_clk",
 337                                      "pwm5_lpcg_ipg_hf_clk",
 338                                      "pwm5_lpcg_ipg_s_clk",
 339                                      "pwm5_lpcg_ipg_slv_clk",
 340                                      "pwm5_lpcg_ipg_mstr_clk";
 341                 power-domains = <&pd IMX_SC_R_PWM_5>;
 342         };
 343
 344         pwm6_lpcg: clock-controller@5d460000 {
 345                 compatible = "fsl,imx8qxp-lpcg";
 346                 reg = <0x5d460000 0x10000>;
 347                 #clock-cells = <1>;
 348                 clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
 349                          <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
 350                          <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
 351                          <&lsio_bus_clk>,
 352                          <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>;
 353                 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
 354                                 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
 355                                 <IMX_LPCG_CLK_6>;
 356                 clock-output-names = "pwm6_lpcg_ipg_clk",
 357                                      "pwm6_lpcg_ipg_hf_clk",
 358                                      "pwm6_lpcg_ipg_s_clk",
 359                                      "pwm6_lpcg_ipg_slv_clk",
 360                                      "pwm6_lpcg_ipg_mstr_clk";
 361                 power-domains = <&pd IMX_SC_R_PWM_6>;
 362         };
 363
 364         pwm7_lpcg: clock-controller@5d470000 {
 365                 compatible = "fsl,imx8qxp-lpcg";
 366                 reg = <0x5d470000 0x10000>;
 367                 #clock-cells = <1>;
 368                 clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
 369                          <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
 370                          <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
 371                          <&lsio_bus_clk>,
 372                          <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>;
 373                 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
 374                                 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
 375                                 <IMX_LPCG_CLK_6>;
 376                 clock-output-names = "pwm7_lpcg_ipg_clk",
 377                                      "pwm7_lpcg_ipg_hf_clk",
 378                                      "pwm7_lpcg_ipg_s_clk",
 379                                      "pwm7_lpcg_ipg_slv_clk",
 380                                      "pwm7_lpcg_ipg_mstr_clk";
 381                 power-domains = <&pd IMX_SC_R_PWM_7>;
 382         };
 383 };