1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2019-2021 NXP
4 * Zhou Guoniu <guoniu.zhou@nxp.com>
6 img_subsys: bus@58000000 {
7 compatible = "simple-bus";
10 ranges = <0x58000000 0x0 0x58000000 0x1000000>;
12 img_ipg_clk: clock-img-ipg {
13 compatible = "fixed-clock";
15 clock-frequency = <200000000>;
16 clock-output-names = "img_ipg_clk";
19 jpegdec: jpegdec@58400000 {
20 reg = <0x58400000 0x00050000>;
21 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
22 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
23 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
24 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
25 clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
26 <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
27 clock-names = "per", "ipg";
28 assigned-clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
29 <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
30 assigned-clock-rates = <200000000>, <200000000>;
31 power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>,
32 <&pd IMX_SC_R_MJPEG_DEC_S0>,
33 <&pd IMX_SC_R_MJPEG_DEC_S1>,
34 <&pd IMX_SC_R_MJPEG_DEC_S2>,
35 <&pd IMX_SC_R_MJPEG_DEC_S3>;
38 jpegenc: jpegenc@58450000 {
39 reg = <0x58450000 0x00050000>;
40 interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
41 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
42 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
43 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
44 clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
45 <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
46 clock-names = "per", "ipg";
47 assigned-clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
48 <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
49 assigned-clock-rates = <200000000>, <200000000>;
50 power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>,
51 <&pd IMX_SC_R_MJPEG_ENC_S0>,
52 <&pd IMX_SC_R_MJPEG_ENC_S1>,
53 <&pd IMX_SC_R_MJPEG_ENC_S2>,
54 <&pd IMX_SC_R_MJPEG_ENC_S3>;
57 img_jpeg_dec_lpcg: clock-controller@585d0000 {
58 compatible = "fsl,imx8qxp-lpcg";
59 reg = <0x585d0000 0x10000>;
61 clocks = <&img_ipg_clk>, <&img_ipg_clk>;
62 clock-indices = <IMX_LPCG_CLK_0>,
64 clock-output-names = "img_jpeg_dec_lpcg_clk",
65 "img_jpeg_dec_lpcg_ipg_clk";
66 power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>;
69 img_jpeg_enc_lpcg: clock-controller@585f0000 {
70 compatible = "fsl,imx8qxp-lpcg";
71 reg = <0x585f0000 0x10000>;
73 clocks = <&img_ipg_clk>, <&img_ipg_clk>;
74 clock-indices = <IMX_LPCG_CLK_0>,
76 clock-output-names = "img_jpeg_enc_lpcg_clk",
77 "img_jpeg_enc_lpcg_ipg_clk";
78 power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>;