1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
5 // Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
12 /memreserve/ 0x80000000 0x00010000;
15 compatible = "fsl,lx2160a";
16 interrupt-parent = <&gic>;
28 // 8 clusters having 2 Cortex-A72 cores each
31 compatible = "arm,cortex-a72";
32 enable-method = "psci";
34 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
35 d-cache-size = <0x8000>;
36 d-cache-line-size = <64>;
38 i-cache-size = <0xC000>;
39 i-cache-line-size = <64>;
41 next-level-cache = <&cluster0_l2>;
42 cpu-idle-states = <&cpu_pw15>;
48 compatible = "arm,cortex-a72";
49 enable-method = "psci";
51 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
52 d-cache-size = <0x8000>;
53 d-cache-line-size = <64>;
55 i-cache-size = <0xC000>;
56 i-cache-line-size = <64>;
58 next-level-cache = <&cluster0_l2>;
59 cpu-idle-states = <&cpu_pw15>;
65 compatible = "arm,cortex-a72";
66 enable-method = "psci";
68 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
69 d-cache-size = <0x8000>;
70 d-cache-line-size = <64>;
72 i-cache-size = <0xC000>;
73 i-cache-line-size = <64>;
75 next-level-cache = <&cluster1_l2>;
76 cpu-idle-states = <&cpu_pw15>;
82 compatible = "arm,cortex-a72";
83 enable-method = "psci";
85 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
86 d-cache-size = <0x8000>;
87 d-cache-line-size = <64>;
89 i-cache-size = <0xC000>;
90 i-cache-line-size = <64>;
92 next-level-cache = <&cluster1_l2>;
93 cpu-idle-states = <&cpu_pw15>;
99 compatible = "arm,cortex-a72";
100 enable-method = "psci";
102 clocks = <&clockgen QORIQ_CLK_CMUX 2>;
103 d-cache-size = <0x8000>;
104 d-cache-line-size = <64>;
105 d-cache-sets = <128>;
106 i-cache-size = <0xC000>;
107 i-cache-line-size = <64>;
108 i-cache-sets = <192>;
109 next-level-cache = <&cluster2_l2>;
110 cpu-idle-states = <&cpu_pw15>;
111 #cooling-cells = <2>;
116 compatible = "arm,cortex-a72";
117 enable-method = "psci";
119 clocks = <&clockgen QORIQ_CLK_CMUX 2>;
120 d-cache-size = <0x8000>;
121 d-cache-line-size = <64>;
122 d-cache-sets = <128>;
123 i-cache-size = <0xC000>;
124 i-cache-line-size = <64>;
125 i-cache-sets = <192>;
126 next-level-cache = <&cluster2_l2>;
127 cpu-idle-states = <&cpu_pw15>;
128 #cooling-cells = <2>;
133 compatible = "arm,cortex-a72";
134 enable-method = "psci";
136 clocks = <&clockgen QORIQ_CLK_CMUX 3>;
137 d-cache-size = <0x8000>;
138 d-cache-line-size = <64>;
139 d-cache-sets = <128>;
140 i-cache-size = <0xC000>;
141 i-cache-line-size = <64>;
142 i-cache-sets = <192>;
143 next-level-cache = <&cluster3_l2>;
144 cpu-idle-states = <&cpu_pw15>;
145 #cooling-cells = <2>;
150 compatible = "arm,cortex-a72";
151 enable-method = "psci";
153 clocks = <&clockgen QORIQ_CLK_CMUX 3>;
154 d-cache-size = <0x8000>;
155 d-cache-line-size = <64>;
156 d-cache-sets = <128>;
157 i-cache-size = <0xC000>;
158 i-cache-line-size = <64>;
159 i-cache-sets = <192>;
160 next-level-cache = <&cluster3_l2>;
161 cpu-idle-states = <&cpu_pw15>;
162 #cooling-cells = <2>;
167 compatible = "arm,cortex-a72";
168 enable-method = "psci";
170 clocks = <&clockgen QORIQ_CLK_CMUX 4>;
171 d-cache-size = <0x8000>;
172 d-cache-line-size = <64>;
173 d-cache-sets = <128>;
174 i-cache-size = <0xC000>;
175 i-cache-line-size = <64>;
176 i-cache-sets = <192>;
177 next-level-cache = <&cluster4_l2>;
178 cpu-idle-states = <&cpu_pw15>;
179 #cooling-cells = <2>;
184 compatible = "arm,cortex-a72";
185 enable-method = "psci";
187 clocks = <&clockgen QORIQ_CLK_CMUX 4>;
188 d-cache-size = <0x8000>;
189 d-cache-line-size = <64>;
190 d-cache-sets = <128>;
191 i-cache-size = <0xC000>;
192 i-cache-line-size = <64>;
193 i-cache-sets = <192>;
194 next-level-cache = <&cluster4_l2>;
195 cpu-idle-states = <&cpu_pw15>;
196 #cooling-cells = <2>;
201 compatible = "arm,cortex-a72";
202 enable-method = "psci";
204 clocks = <&clockgen QORIQ_CLK_CMUX 5>;
205 d-cache-size = <0x8000>;
206 d-cache-line-size = <64>;
207 d-cache-sets = <128>;
208 i-cache-size = <0xC000>;
209 i-cache-line-size = <64>;
210 i-cache-sets = <192>;
211 next-level-cache = <&cluster5_l2>;
212 cpu-idle-states = <&cpu_pw15>;
213 #cooling-cells = <2>;
218 compatible = "arm,cortex-a72";
219 enable-method = "psci";
221 clocks = <&clockgen QORIQ_CLK_CMUX 5>;
222 d-cache-size = <0x8000>;
223 d-cache-line-size = <64>;
224 d-cache-sets = <128>;
225 i-cache-size = <0xC000>;
226 i-cache-line-size = <64>;
227 i-cache-sets = <192>;
228 next-level-cache = <&cluster5_l2>;
229 cpu-idle-states = <&cpu_pw15>;
230 #cooling-cells = <2>;
235 compatible = "arm,cortex-a72";
236 enable-method = "psci";
238 clocks = <&clockgen QORIQ_CLK_CMUX 6>;
239 d-cache-size = <0x8000>;
240 d-cache-line-size = <64>;
241 d-cache-sets = <128>;
242 i-cache-size = <0xC000>;
243 i-cache-line-size = <64>;
244 i-cache-sets = <192>;
245 next-level-cache = <&cluster6_l2>;
246 cpu-idle-states = <&cpu_pw15>;
247 #cooling-cells = <2>;
252 compatible = "arm,cortex-a72";
253 enable-method = "psci";
255 clocks = <&clockgen QORIQ_CLK_CMUX 6>;
256 d-cache-size = <0x8000>;
257 d-cache-line-size = <64>;
258 d-cache-sets = <128>;
259 i-cache-size = <0xC000>;
260 i-cache-line-size = <64>;
261 i-cache-sets = <192>;
262 next-level-cache = <&cluster6_l2>;
263 cpu-idle-states = <&cpu_pw15>;
264 #cooling-cells = <2>;
269 compatible = "arm,cortex-a72";
270 enable-method = "psci";
272 clocks = <&clockgen QORIQ_CLK_CMUX 7>;
273 d-cache-size = <0x8000>;
274 d-cache-line-size = <64>;
275 d-cache-sets = <128>;
276 i-cache-size = <0xC000>;
277 i-cache-line-size = <64>;
278 i-cache-sets = <192>;
279 next-level-cache = <&cluster7_l2>;
280 cpu-idle-states = <&cpu_pw15>;
281 #cooling-cells = <2>;
286 compatible = "arm,cortex-a72";
287 enable-method = "psci";
289 clocks = <&clockgen QORIQ_CLK_CMUX 7>;
290 d-cache-size = <0x8000>;
291 d-cache-line-size = <64>;
292 d-cache-sets = <128>;
293 i-cache-size = <0xC000>;
294 i-cache-line-size = <64>;
295 i-cache-sets = <192>;
296 next-level-cache = <&cluster7_l2>;
297 cpu-idle-states = <&cpu_pw15>;
298 #cooling-cells = <2>;
301 cluster0_l2: l2-cache0 {
302 compatible = "cache";
303 cache-size = <0x100000>;
304 cache-line-size = <64>;
309 cluster1_l2: l2-cache1 {
310 compatible = "cache";
311 cache-size = <0x100000>;
312 cache-line-size = <64>;
317 cluster2_l2: l2-cache2 {
318 compatible = "cache";
319 cache-size = <0x100000>;
320 cache-line-size = <64>;
325 cluster3_l2: l2-cache3 {
326 compatible = "cache";
327 cache-size = <0x100000>;
328 cache-line-size = <64>;
333 cluster4_l2: l2-cache4 {
334 compatible = "cache";
335 cache-size = <0x100000>;
336 cache-line-size = <64>;
341 cluster5_l2: l2-cache5 {
342 compatible = "cache";
343 cache-size = <0x100000>;
344 cache-line-size = <64>;
349 cluster6_l2: l2-cache6 {
350 compatible = "cache";
351 cache-size = <0x100000>;
352 cache-line-size = <64>;
357 cluster7_l2: l2-cache7 {
358 compatible = "cache";
359 cache-size = <0x100000>;
360 cache-line-size = <64>;
366 compatible = "arm,idle-state";
367 idle-state-name = "PW15";
368 arm,psci-suspend-param = <0x0>;
369 entry-latency-us = <2000>;
370 exit-latency-us = <2000>;
371 min-residency-us = <6000>;
375 gic: interrupt-controller@6000000 {
376 compatible = "arm,gic-v3";
377 reg = <0x0 0x06000000 0 0x10000>, // GIC Dist
378 <0x0 0x06200000 0 0x200000>, // GICR (RD_base +
380 <0x0 0x0c0c0000 0 0x2000>, // GICC
381 <0x0 0x0c0d0000 0 0x1000>, // GICH
382 <0x0 0x0c0e0000 0 0x20000>; // GICV
383 #interrupt-cells = <3>;
384 #address-cells = <2>;
387 interrupt-controller;
388 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
390 its: gic-its@6020000 {
391 compatible = "arm,gic-v3-its";
393 reg = <0x0 0x6020000 0 0x20000>;
398 compatible = "arm,armv8-timer";
399 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
400 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
406 compatible = "arm,cortex-a72-pmu";
407 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
411 compatible = "arm,psci-0.2";
416 // DRAM space - 1, size : 2 GB DRAM
417 device_type = "memory";
418 reg = <0x00000000 0x80000000 0 0x80000000>;
421 ddr1: memory-controller@1080000 {
422 compatible = "fsl,qoriq-memory-controller";
423 reg = <0x0 0x1080000 0x0 0x1000>;
424 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
428 ddr2: memory-controller@1090000 {
429 compatible = "fsl,qoriq-memory-controller";
430 reg = <0x0 0x1090000 0x0 0x1000>;
431 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
435 // One clock unit-sysclk node which bootloader require during DT fix-up
437 compatible = "fixed-clock";
439 clock-frequency = <100000000>; // fixed up by bootloader
440 clock-output-names = "sysclk";
445 polling-delay-passive = <1000>;
446 polling-delay = <5000>;
447 thermal-sensors = <&tmu 0>;
450 cluster6_7_alert: cluster6-7-alert {
451 temperature = <85000>;
456 cluster6_7_crit: cluster6-7-crit {
457 temperature = <95000>;
465 trip = <&cluster6_7_alert>;
467 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
468 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
469 <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
470 <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
471 <&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
472 <&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
473 <&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
474 <&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
475 <&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
476 <&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
477 <&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
478 <&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
479 <&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
480 <&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
481 <&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
482 <&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
488 polling-delay-passive = <1000>;
489 polling-delay = <5000>;
490 thermal-sensors = <&tmu 1>;
494 temperature = <85000>;
500 temperature = <95000>;
508 polling-delay-passive = <1000>;
509 polling-delay = <5000>;
510 thermal-sensors = <&tmu 2>;
514 temperature = <85000>;
520 temperature = <95000>;
528 polling-delay-passive = <1000>;
529 polling-delay = <5000>;
530 thermal-sensors = <&tmu 3>;
534 temperature = <85000>;
540 temperature = <95000>;
548 polling-delay-passive = <1000>;
549 polling-delay = <5000>;
550 thermal-sensors = <&tmu 4>;
554 temperature = <85000>;
560 temperature = <95000>;
568 polling-delay-passive = <1000>;
569 polling-delay = <5000>;
570 thermal-sensors = <&tmu 5>;
574 temperature = <85000>;
580 temperature = <95000>;
588 polling-delay-passive = <1000>;
589 polling-delay = <5000>;
590 thermal-sensors = <&tmu 6>;
594 temperature = <85000>;
600 temperature = <95000>;
609 compatible = "simple-bus";
610 #address-cells = <2>;
613 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
615 crypto: crypto@8000000 {
616 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
618 #address-cells = <1>;
620 ranges = <0x0 0x00 0x8000000 0x100000>;
621 reg = <0x00 0x8000000 0x0 0x100000>;
622 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
627 compatible = "fsl,sec-v5.0-job-ring",
628 "fsl,sec-v4.0-job-ring";
629 reg = <0x10000 0x10000>;
630 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
634 compatible = "fsl,sec-v5.0-job-ring",
635 "fsl,sec-v4.0-job-ring";
636 reg = <0x20000 0x10000>;
637 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
641 compatible = "fsl,sec-v5.0-job-ring",
642 "fsl,sec-v4.0-job-ring";
643 reg = <0x30000 0x10000>;
644 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
648 compatible = "fsl,sec-v5.0-job-ring",
649 "fsl,sec-v4.0-job-ring";
650 reg = <0x40000 0x10000>;
651 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
655 clockgen: clock-controller@1300000 {
656 compatible = "fsl,lx2160a-clockgen";
657 reg = <0 0x1300000 0 0xa0000>;
662 dcfg: syscon@1e00000 {
663 compatible = "fsl,lx2160a-dcfg", "syscon";
664 reg = <0x0 0x1e00000 0x0 0x10000>;
668 isc: syscon@1f70000 {
669 compatible = "fsl,lx2160a-isc", "syscon";
670 reg = <0x0 0x1f70000 0x0 0x10000>;
672 #address-cells = <1>;
674 ranges = <0x0 0x0 0x1f70000 0x10000>;
676 extirq: interrupt-controller@14 {
677 compatible = "fsl,lx2160a-extirq", "fsl,ls1088a-extirq";
678 #interrupt-cells = <2>;
679 #address-cells = <0>;
680 interrupt-controller;
683 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
684 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
685 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
686 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
687 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
688 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
689 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
690 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
691 <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
692 <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
693 <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
694 <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
695 interrupt-map-mask = <0xffffffff 0x0>;
700 compatible = "fsl,qoriq-tmu";
701 reg = <0x0 0x1f80000 0x0 0x10000>;
702 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
703 fsl,tmu-range = <0x800000e6 0x8001017d>;
704 fsl,tmu-calibration =
705 /* Calibration data group 1 */
706 <0x00000000 0x00000035
707 /* Calibration data group 2 */
708 0x00000001 0x00000154>;
710 #thermal-sensor-cells = <1>;
714 compatible = "fsl,vf610-i2c";
715 #address-cells = <1>;
717 reg = <0x0 0x2000000 0x0 0x10000>;
718 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
720 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
721 QORIQ_CLK_PLL_DIV(16)>;
722 scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
727 compatible = "fsl,vf610-i2c";
728 #address-cells = <1>;
730 reg = <0x0 0x2010000 0x0 0x10000>;
731 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
733 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
734 QORIQ_CLK_PLL_DIV(16)>;
739 compatible = "fsl,vf610-i2c";
740 #address-cells = <1>;
742 reg = <0x0 0x2020000 0x0 0x10000>;
743 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
745 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
746 QORIQ_CLK_PLL_DIV(16)>;
751 compatible = "fsl,vf610-i2c";
752 #address-cells = <1>;
754 reg = <0x0 0x2030000 0x0 0x10000>;
755 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
757 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
758 QORIQ_CLK_PLL_DIV(16)>;
763 compatible = "fsl,vf610-i2c";
764 #address-cells = <1>;
766 reg = <0x0 0x2040000 0x0 0x10000>;
767 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
769 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
770 QORIQ_CLK_PLL_DIV(16)>;
771 scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>;
776 compatible = "fsl,vf610-i2c";
777 #address-cells = <1>;
779 reg = <0x0 0x2050000 0x0 0x10000>;
780 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
782 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
783 QORIQ_CLK_PLL_DIV(16)>;
788 compatible = "fsl,vf610-i2c";
789 #address-cells = <1>;
791 reg = <0x0 0x2060000 0x0 0x10000>;
792 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
794 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
795 QORIQ_CLK_PLL_DIV(16)>;
800 compatible = "fsl,vf610-i2c";
801 #address-cells = <1>;
803 reg = <0x0 0x2070000 0x0 0x10000>;
804 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
806 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
807 QORIQ_CLK_PLL_DIV(16)>;
812 compatible = "nxp,lx2160a-fspi";
813 #address-cells = <1>;
815 reg = <0x0 0x20c0000 0x0 0x10000>,
816 <0x0 0x20000000 0x0 0x10000000>;
817 reg-names = "fspi_base", "fspi_mmap";
818 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
819 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
820 QORIQ_CLK_PLL_DIV(4)>,
821 <&clockgen QORIQ_CLK_PLATFORM_PLL
822 QORIQ_CLK_PLL_DIV(4)>;
823 clock-names = "fspi_en", "fspi";
828 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
829 #address-cells = <1>;
831 reg = <0x0 0x2100000 0x0 0x10000>;
832 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
833 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
834 QORIQ_CLK_PLL_DIV(8)>;
835 clock-names = "dspi";
836 spi-num-chipselects = <5>;
842 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
843 #address-cells = <1>;
845 reg = <0x0 0x2110000 0x0 0x10000>;
846 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
847 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
848 QORIQ_CLK_PLL_DIV(8)>;
849 clock-names = "dspi";
850 spi-num-chipselects = <5>;
856 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
857 #address-cells = <1>;
859 reg = <0x0 0x2120000 0x0 0x10000>;
860 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
861 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
862 QORIQ_CLK_PLL_DIV(8)>;
863 clock-names = "dspi";
864 spi-num-chipselects = <5>;
869 esdhc0: esdhc@2140000 {
870 compatible = "fsl,esdhc";
871 reg = <0x0 0x2140000 0x0 0x10000>;
872 interrupts = <0 28 0x4>; /* Level high type */
873 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
874 QORIQ_CLK_PLL_DIV(2)>;
876 voltage-ranges = <1800 1800 3300 3300>;
883 esdhc1: esdhc@2150000 {
884 compatible = "fsl,esdhc";
885 reg = <0x0 0x2150000 0x0 0x10000>;
886 interrupts = <0 63 0x4>; /* Level high type */
887 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
888 QORIQ_CLK_PLL_DIV(2)>;
890 voltage-ranges = <1800 1800 3300 3300>;
899 compatible = "fsl,lx2160ar1-flexcan";
900 reg = <0x0 0x2180000 0x0 0x10000>;
901 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
902 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
903 QORIQ_CLK_PLL_DIV(8)>,
904 <&clockgen QORIQ_CLK_SYSCLK 0>;
905 clock-names = "ipg", "per";
906 fsl,clk-source = <0>;
911 compatible = "fsl,lx2160ar1-flexcan";
912 reg = <0x0 0x2190000 0x0 0x10000>;
913 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
914 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
915 QORIQ_CLK_PLL_DIV(8)>,
916 <&clockgen QORIQ_CLK_SYSCLK 0>;
917 clock-names = "ipg", "per";
918 fsl,clk-source = <0>;
922 uart0: serial@21c0000 {
923 compatible = "arm,sbsa-uart","arm,pl011";
924 reg = <0x0 0x21c0000 0x0 0x1000>;
925 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
926 current-speed = <115200>;
930 uart1: serial@21d0000 {
931 compatible = "arm,sbsa-uart","arm,pl011";
932 reg = <0x0 0x21d0000 0x0 0x1000>;
933 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
934 current-speed = <115200>;
938 uart2: serial@21e0000 {
939 compatible = "arm,sbsa-uart","arm,pl011";
940 reg = <0x0 0x21e0000 0x0 0x1000>;
941 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
942 current-speed = <115200>;
946 uart3: serial@21f0000 {
947 compatible = "arm,sbsa-uart","arm,pl011";
948 reg = <0x0 0x21f0000 0x0 0x1000>;
949 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
950 current-speed = <115200>;
954 gpio0: gpio@2300000 {
955 compatible = "fsl,qoriq-gpio";
956 reg = <0x0 0x2300000 0x0 0x10000>;
957 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
961 interrupt-controller;
962 #interrupt-cells = <2>;
965 gpio1: gpio@2310000 {
966 compatible = "fsl,qoriq-gpio";
967 reg = <0x0 0x2310000 0x0 0x10000>;
968 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
972 interrupt-controller;
973 #interrupt-cells = <2>;
976 gpio2: gpio@2320000 {
977 compatible = "fsl,qoriq-gpio";
978 reg = <0x0 0x2320000 0x0 0x10000>;
979 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
983 interrupt-controller;
984 #interrupt-cells = <2>;
987 gpio3: gpio@2330000 {
988 compatible = "fsl,qoriq-gpio";
989 reg = <0x0 0x2330000 0x0 0x10000>;
990 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
994 interrupt-controller;
995 #interrupt-cells = <2>;
999 compatible = "arm,sbsa-gwdt";
1000 reg = <0x0 0x23a0000 0 0x1000>,
1001 <0x0 0x2390000 0 0x1000>;
1002 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1006 rcpm: power-controller@1e34040 {
1007 compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+";
1008 reg = <0x0 0x1e34040 0x0 0x1c>;
1009 #fsl,rcpm-wakeup-cells = <7>;
1013 ftm_alarm0: timer@2800000 {
1014 compatible = "fsl,lx2160a-ftm-alarm";
1015 reg = <0x0 0x2800000 0x0 0x10000>;
1016 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
1017 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1021 compatible = "snps,dwc3";
1022 reg = <0x0 0x3100000 0x0 0x10000>;
1023 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1025 snps,quirk-frame-length-adjustment = <0x20>;
1026 snps,dis_rxdet_inp3_quirk;
1027 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1028 status = "disabled";
1032 compatible = "snps,dwc3";
1033 reg = <0x0 0x3110000 0x0 0x10000>;
1034 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1036 snps,quirk-frame-length-adjustment = <0x20>;
1037 snps,dis_rxdet_inp3_quirk;
1038 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1039 status = "disabled";
1042 sata0: sata@3200000 {
1043 compatible = "fsl,lx2160a-ahci";
1044 reg = <0x0 0x3200000 0x0 0x10000>,
1045 <0x7 0x100520 0x0 0x4>;
1046 reg-names = "ahci", "sata-ecc";
1047 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1048 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1049 QORIQ_CLK_PLL_DIV(4)>;
1051 status = "disabled";
1054 sata1: sata@3210000 {
1055 compatible = "fsl,lx2160a-ahci";
1056 reg = <0x0 0x3210000 0x0 0x10000>,
1057 <0x7 0x100520 0x0 0x4>;
1058 reg-names = "ahci", "sata-ecc";
1059 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1060 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1061 QORIQ_CLK_PLL_DIV(4)>;
1063 status = "disabled";
1066 sata2: sata@3220000 {
1067 compatible = "fsl,lx2160a-ahci";
1068 reg = <0x0 0x3220000 0x0 0x10000>,
1069 <0x7 0x100520 0x0 0x4>;
1070 reg-names = "ahci", "sata-ecc";
1071 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1072 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1073 QORIQ_CLK_PLL_DIV(4)>;
1075 status = "disabled";
1078 sata3: sata@3230000 {
1079 compatible = "fsl,lx2160a-ahci";
1080 reg = <0x0 0x3230000 0x0 0x10000>,
1081 <0x7 0x100520 0x0 0x4>;
1082 reg-names = "ahci", "sata-ecc";
1083 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1084 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1085 QORIQ_CLK_PLL_DIV(4)>;
1087 status = "disabled";
1090 pcie1: pcie@3400000 {
1091 compatible = "fsl,lx2160a-pcie";
1092 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
1093 <0x80 0x00000000 0x0 0x00002000>; /* configuration space */
1094 reg-names = "csr_axi_slave", "config_axi_slave";
1095 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1096 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1097 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1098 interrupt-names = "aer", "pme", "intr";
1099 #address-cells = <3>;
1101 device_type = "pci";
1105 bus-range = <0x0 0xff>;
1106 ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1107 msi-parent = <&its>;
1108 #interrupt-cells = <1>;
1109 interrupt-map-mask = <0 0 0 7>;
1110 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1111 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1112 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1113 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1114 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1115 status = "disabled";
1118 pcie2: pcie@3500000 {
1119 compatible = "fsl,lx2160a-pcie";
1120 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
1121 <0x88 0x00000000 0x0 0x00002000>; /* configuration space */
1122 reg-names = "csr_axi_slave", "config_axi_slave";
1123 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1124 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1125 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1126 interrupt-names = "aer", "pme", "intr";
1127 #address-cells = <3>;
1129 device_type = "pci";
1133 bus-range = <0x0 0xff>;
1134 ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1135 msi-parent = <&its>;
1136 #interrupt-cells = <1>;
1137 interrupt-map-mask = <0 0 0 7>;
1138 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1139 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1140 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1141 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1142 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1143 status = "disabled";
1146 pcie3: pcie@3600000 {
1147 compatible = "fsl,lx2160a-pcie";
1148 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
1149 <0x90 0x00000000 0x0 0x00002000>; /* configuration space */
1150 reg-names = "csr_axi_slave", "config_axi_slave";
1151 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1152 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1153 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1154 interrupt-names = "aer", "pme", "intr";
1155 #address-cells = <3>;
1157 device_type = "pci";
1161 bus-range = <0x0 0xff>;
1162 ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1163 msi-parent = <&its>;
1164 #interrupt-cells = <1>;
1165 interrupt-map-mask = <0 0 0 7>;
1166 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1167 <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1168 <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1169 <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1170 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1171 status = "disabled";
1174 pcie4: pcie@3700000 {
1175 compatible = "fsl,lx2160a-pcie";
1176 reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
1177 <0x98 0x00000000 0x0 0x00002000>; /* configuration space */
1178 reg-names = "csr_axi_slave", "config_axi_slave";
1179 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1180 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1181 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1182 interrupt-names = "aer", "pme", "intr";
1183 #address-cells = <3>;
1185 device_type = "pci";
1189 bus-range = <0x0 0xff>;
1190 ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1191 msi-parent = <&its>;
1192 #interrupt-cells = <1>;
1193 interrupt-map-mask = <0 0 0 7>;
1194 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1195 <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1196 <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1197 <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1198 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1199 status = "disabled";
1202 pcie5: pcie@3800000 {
1203 compatible = "fsl,lx2160a-pcie";
1204 reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */
1205 <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
1206 reg-names = "csr_axi_slave", "config_axi_slave";
1207 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1208 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1209 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1210 interrupt-names = "aer", "pme", "intr";
1211 #address-cells = <3>;
1213 device_type = "pci";
1217 bus-range = <0x0 0xff>;
1218 ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1219 msi-parent = <&its>;
1220 #interrupt-cells = <1>;
1221 interrupt-map-mask = <0 0 0 7>;
1222 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
1223 <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1224 <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1225 <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
1226 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1227 status = "disabled";
1230 pcie6: pcie@3900000 {
1231 compatible = "fsl,lx2160a-pcie";
1232 reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */
1233 <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
1234 reg-names = "csr_axi_slave", "config_axi_slave";
1235 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1236 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1237 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1238 interrupt-names = "aer", "pme", "intr";
1239 #address-cells = <3>;
1241 device_type = "pci";
1245 bus-range = <0x0 0xff>;
1246 ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1247 msi-parent = <&its>;
1248 #interrupt-cells = <1>;
1249 interrupt-map-mask = <0 0 0 7>;
1250 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1251 <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1252 <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1253 <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1254 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1255 status = "disabled";
1258 smmu: iommu@5000000 {
1259 compatible = "arm,mmu-500";
1260 reg = <0 0x5000000 0 0x800000>;
1262 #global-interrupts = <14>;
1263 // global secure fault
1264 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
1266 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
1267 // global non-secure fault
1268 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
1269 // combined non-secure
1270 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1271 // performance counter interrupts 0-9
1272 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
1273 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
1274 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
1275 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
1276 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
1277 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
1278 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1279 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
1280 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
1281 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
1282 // per context interrupt, 64 interrupts
1283 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1284 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1285 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1286 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1287 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1288 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1289 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
1290 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1291 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
1292 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1293 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
1294 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1295 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
1296 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
1297 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
1298 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
1299 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
1300 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1301 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
1302 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
1303 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
1304 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
1305 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
1306 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
1307 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1308 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
1309 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
1310 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
1311 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
1312 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
1313 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
1314 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
1315 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
1316 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
1317 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
1318 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1319 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1320 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1321 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1322 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1323 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1324 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1325 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1326 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1327 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1328 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1329 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1330 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
1331 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
1332 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1334 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
1335 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1336 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
1337 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
1338 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
1339 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
1342 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
1343 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
1344 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
1345 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
1346 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1351 compatible = "fsl,dpaa2-console";
1352 reg = <0x00000000 0x08340020 0 0x2>;
1356 compatible = "fsl,dpaa2-ptp";
1357 reg = <0x0 0x8b95000 0x0 0x100>;
1358 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1359 QORIQ_CLK_PLL_DIV(2)>;
1364 /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
1365 emdio1: mdio@8b96000 {
1366 compatible = "fsl,fman-memac-mdio";
1367 reg = <0x0 0x8b96000 0x0 0x1000>;
1368 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1369 #address-cells = <1>;
1372 status = "disabled";
1375 emdio2: mdio@8b97000 {
1376 compatible = "fsl,fman-memac-mdio";
1377 reg = <0x0 0x8b97000 0x0 0x1000>;
1378 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1380 #address-cells = <1>;
1382 status = "disabled";
1385 pcs_mdio1: mdio@8c07000 {
1386 compatible = "fsl,fman-memac-mdio";
1387 reg = <0x0 0x8c07000 0x0 0x1000>;
1389 #address-cells = <1>;
1391 status = "disabled";
1393 pcs1: ethernet-phy@0 {
1398 pcs_mdio2: mdio@8c0b000 {
1399 compatible = "fsl,fman-memac-mdio";
1400 reg = <0x0 0x8c0b000 0x0 0x1000>;
1402 #address-cells = <1>;
1404 status = "disabled";
1406 pcs2: ethernet-phy@0 {
1411 pcs_mdio3: mdio@8c0f000 {
1412 compatible = "fsl,fman-memac-mdio";
1413 reg = <0x0 0x8c0f000 0x0 0x1000>;
1415 #address-cells = <1>;
1417 status = "disabled";
1419 pcs3: ethernet-phy@0 {
1424 pcs_mdio4: mdio@8c13000 {
1425 compatible = "fsl,fman-memac-mdio";
1426 reg = <0x0 0x8c13000 0x0 0x1000>;
1428 #address-cells = <1>;
1430 status = "disabled";
1432 pcs4: ethernet-phy@0 {
1437 pcs_mdio5: mdio@8c17000 {
1438 compatible = "fsl,fman-memac-mdio";
1439 reg = <0x0 0x8c17000 0x0 0x1000>;
1441 #address-cells = <1>;
1443 status = "disabled";
1445 pcs5: ethernet-phy@0 {
1450 pcs_mdio6: mdio@8c1b000 {
1451 compatible = "fsl,fman-memac-mdio";
1452 reg = <0x0 0x8c1b000 0x0 0x1000>;
1454 #address-cells = <1>;
1456 status = "disabled";
1458 pcs6: ethernet-phy@0 {
1463 pcs_mdio7: mdio@8c1f000 {
1464 compatible = "fsl,fman-memac-mdio";
1465 reg = <0x0 0x8c1f000 0x0 0x1000>;
1467 #address-cells = <1>;
1469 status = "disabled";
1471 pcs7: ethernet-phy@0 {
1476 pcs_mdio8: mdio@8c23000 {
1477 compatible = "fsl,fman-memac-mdio";
1478 reg = <0x0 0x8c23000 0x0 0x1000>;
1480 #address-cells = <1>;
1482 status = "disabled";
1484 pcs8: ethernet-phy@0 {
1489 pcs_mdio9: mdio@8c27000 {
1490 compatible = "fsl,fman-memac-mdio";
1491 reg = <0x0 0x8c27000 0x0 0x1000>;
1493 #address-cells = <1>;
1495 status = "disabled";
1497 pcs9: ethernet-phy@0 {
1502 pcs_mdio10: mdio@8c2b000 {
1503 compatible = "fsl,fman-memac-mdio";
1504 reg = <0x0 0x8c2b000 0x0 0x1000>;
1506 #address-cells = <1>;
1508 status = "disabled";
1510 pcs10: ethernet-phy@0 {
1515 pcs_mdio11: mdio@8c2f000 {
1516 compatible = "fsl,fman-memac-mdio";
1517 reg = <0x0 0x8c2f000 0x0 0x1000>;
1519 #address-cells = <1>;
1521 status = "disabled";
1523 pcs11: ethernet-phy@0 {
1528 pcs_mdio12: mdio@8c33000 {
1529 compatible = "fsl,fman-memac-mdio";
1530 reg = <0x0 0x8c33000 0x0 0x1000>;
1532 #address-cells = <1>;
1534 status = "disabled";
1536 pcs12: ethernet-phy@0 {
1541 pcs_mdio13: mdio@8c37000 {
1542 compatible = "fsl,fman-memac-mdio";
1543 reg = <0x0 0x8c37000 0x0 0x1000>;
1545 #address-cells = <1>;
1547 status = "disabled";
1549 pcs13: ethernet-phy@0 {
1554 pcs_mdio14: mdio@8c3b000 {
1555 compatible = "fsl,fman-memac-mdio";
1556 reg = <0x0 0x8c3b000 0x0 0x1000>;
1558 #address-cells = <1>;
1560 status = "disabled";
1562 pcs14: ethernet-phy@0 {
1567 pcs_mdio15: mdio@8c3f000 {
1568 compatible = "fsl,fman-memac-mdio";
1569 reg = <0x0 0x8c3f000 0x0 0x1000>;
1571 #address-cells = <1>;
1573 status = "disabled";
1575 pcs15: ethernet-phy@0 {
1580 pcs_mdio16: mdio@8c43000 {
1581 compatible = "fsl,fman-memac-mdio";
1582 reg = <0x0 0x8c43000 0x0 0x1000>;
1584 #address-cells = <1>;
1586 status = "disabled";
1588 pcs16: ethernet-phy@0 {
1593 pcs_mdio17: mdio@8c47000 {
1594 compatible = "fsl,fman-memac-mdio";
1595 reg = <0x0 0x8c47000 0x0 0x1000>;
1597 #address-cells = <1>;
1599 status = "disabled";
1601 pcs17: ethernet-phy@0 {
1606 pcs_mdio18: mdio@8c4b000 {
1607 compatible = "fsl,fman-memac-mdio";
1608 reg = <0x0 0x8c4b000 0x0 0x1000>;
1610 #address-cells = <1>;
1612 status = "disabled";
1614 pcs18: ethernet-phy@0 {
1619 fsl_mc: fsl-mc@80c000000 {
1620 compatible = "fsl,qoriq-mc";
1621 reg = <0x00000008 0x0c000000 0 0x40>,
1622 <0x00000000 0x08340000 0 0x40000>;
1623 msi-parent = <&its>;
1624 /* iommu-map property is fixed up by u-boot */
1625 iommu-map = <0 &smmu 0 0>;
1627 #address-cells = <3>;
1631 * Region type 0x0 - MC portals
1632 * Region type 0x1 - QBMAN portals
1634 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
1635 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
1638 * Define the maximum number of MACs present on the SoC.
1641 #address-cells = <1>;
1644 dpmac1: ethernet@1 {
1645 compatible = "fsl,qoriq-mc-dpmac";
1647 pcs-handle = <&pcs1>;
1650 dpmac2: ethernet@2 {
1651 compatible = "fsl,qoriq-mc-dpmac";
1653 pcs-handle = <&pcs2>;
1656 dpmac3: ethernet@3 {
1657 compatible = "fsl,qoriq-mc-dpmac";
1659 pcs-handle = <&pcs3>;
1662 dpmac4: ethernet@4 {
1663 compatible = "fsl,qoriq-mc-dpmac";
1665 pcs-handle = <&pcs4>;
1668 dpmac5: ethernet@5 {
1669 compatible = "fsl,qoriq-mc-dpmac";
1671 pcs-handle = <&pcs5>;
1674 dpmac6: ethernet@6 {
1675 compatible = "fsl,qoriq-mc-dpmac";
1677 pcs-handle = <&pcs6>;
1680 dpmac7: ethernet@7 {
1681 compatible = "fsl,qoriq-mc-dpmac";
1683 pcs-handle = <&pcs7>;
1686 dpmac8: ethernet@8 {
1687 compatible = "fsl,qoriq-mc-dpmac";
1689 pcs-handle = <&pcs8>;
1692 dpmac9: ethernet@9 {
1693 compatible = "fsl,qoriq-mc-dpmac";
1695 pcs-handle = <&pcs9>;
1698 dpmac10: ethernet@a {
1699 compatible = "fsl,qoriq-mc-dpmac";
1701 pcs-handle = <&pcs10>;
1704 dpmac11: ethernet@b {
1705 compatible = "fsl,qoriq-mc-dpmac";
1707 pcs-handle = <&pcs11>;
1710 dpmac12: ethernet@c {
1711 compatible = "fsl,qoriq-mc-dpmac";
1713 pcs-handle = <&pcs12>;
1716 dpmac13: ethernet@d {
1717 compatible = "fsl,qoriq-mc-dpmac";
1719 pcs-handle = <&pcs13>;
1722 dpmac14: ethernet@e {
1723 compatible = "fsl,qoriq-mc-dpmac";
1725 pcs-handle = <&pcs14>;
1728 dpmac15: ethernet@f {
1729 compatible = "fsl,qoriq-mc-dpmac";
1731 pcs-handle = <&pcs15>;
1734 dpmac16: ethernet@10 {
1735 compatible = "fsl,qoriq-mc-dpmac";
1737 pcs-handle = <&pcs16>;
1740 dpmac17: ethernet@11 {
1741 compatible = "fsl,qoriq-mc-dpmac";
1743 pcs-handle = <&pcs17>;
1746 dpmac18: ethernet@12 {
1747 compatible = "fsl,qoriq-mc-dpmac";
1749 pcs-handle = <&pcs18>;