1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree file for LX2160ARDB
5 // Copyright 2018-2020 NXP
9 #include "fsl-lx2160a.dtsi"
12 model = "NXP Layerscape LX2160ARDB";
13 compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
41 phy-handle = <&aquantia_phy1>;
42 phy-connection-type = "usxgmii";
43 managed = "in-band-status";
47 phy-handle = <&aquantia_phy2>;
48 phy-connection-type = "usxgmii";
49 managed = "in-band-status";
53 phy-handle = <&rgmii_phy1>;
54 phy-connection-type = "rgmii-id";
58 phy-handle = <&rgmii_phy2>;
59 phy-connection-type = "rgmii-id";
65 rgmii_phy1: ethernet-phy@1 {
67 compatible = "ethernet-phy-id004d.d072";
72 rgmii_phy2: ethernet-phy@2 {
74 compatible = "ethernet-phy-id004d.d072";
79 aquantia_phy1: ethernet-phy@4 {
81 compatible = "ethernet-phy-ieee802.3-c45";
85 aquantia_phy2: ethernet-phy@5 {
87 compatible = "ethernet-phy-ieee802.3-c45";
96 max-bitrate = <5000000>;
104 max-bitrate = <5000000>;
126 mt35xu512aba0: flash@0 {
127 #address-cells = <1>;
129 compatible = "jedec,spi-nor";
131 spi-max-frequency = <50000000>;
133 spi-rx-bus-width = <8>;
134 spi-tx-bus-width = <8>;
137 mt35xu512aba1: flash@1 {
138 #address-cells = <1>;
140 compatible = "jedec,spi-nor";
142 spi-max-frequency = <50000000>;
144 spi-rx-bus-width = <8>;
145 spi-tx-bus-width = <8>;
153 compatible = "nxp,pca9547";
155 #address-cells = <1>;
159 #address-cells = <1>;
164 compatible = "ti,ina220";
166 shunt-resistor = <500>;
171 #address-cells = <1>;
175 temperature-sensor@4c {
176 compatible = "nxp,sa56004";
178 vcc-supply = <&sb_3v3>;
181 temperature-sensor@4d {
182 compatible = "nxp,sa56004";
184 vcc-supply = <&sb_3v3>;
194 compatible = "nxp,pcf2129";
196 /* IRQ_RTC_B -> IRQ08, active low */
197 interrupts-extended = <&extirq 8 IRQ_TYPE_LEVEL_LOW>;