1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
5 * Copyright 2016 Freescale Semiconductor, Inc.
8 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 compatible = "fsl,ls2080a";
17 interrupt-parent = <&gic>;
36 device_type = "memory";
37 reg = <0x00000000 0x80000000 0 0x80000000>;
38 /* DRAM space - 1, size : 2 GB DRAM */
42 compatible = "fixed-clock";
44 clock-frequency = <100000000>;
45 clock-output-names = "sysclk";
48 gic: interrupt-controller@6000000 {
49 compatible = "arm,gic-v3";
50 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
51 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
52 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
53 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
54 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
55 #interrupt-cells = <3>;
60 interrupts = <1 9 0x4>;
62 its: gic-its@6020000 {
63 compatible = "arm,gic-v3-its";
65 reg = <0x0 0x6020000 0 0x20000>;
69 rstcr: syscon@1e60000 {
70 compatible = "fsl,ls2080a-rstcr", "syscon";
71 reg = <0x0 0x1e60000 0x0 0x4>;
75 compatible ="syscon-reboot";
82 cpu_thermal: cpu-thermal {
83 polling-delay-passive = <1000>;
84 polling-delay = <5000>;
86 thermal-sensors = <&tmu 4>;
89 cpu_alert: cpu-alert {
90 temperature = <75000>;
95 temperature = <85000>;
105 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
106 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
107 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
108 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
109 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
110 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
111 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
112 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
119 compatible = "arm,armv8-timer";
120 interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
121 <1 14 4>, /* Physical Non-Secure PPI, active-low */
122 <1 11 4>, /* Virtual PPI, active-low */
123 <1 10 4>; /* Hypervisor PPI, active-low */
128 compatible = "arm,armv8-pmuv3";
129 interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
133 compatible = "arm,psci-0.2";
138 compatible = "simple-bus";
139 #address-cells = <2>;
142 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
144 clockgen: clocking@1300000 {
145 compatible = "fsl,ls2080a-clockgen";
146 reg = <0 0x1300000 0 0xa0000>;
152 compatible = "fsl,ls2080a-dcfg", "syscon";
153 reg = <0x0 0x1e00000 0x0 0x10000>;
158 compatible = "fsl,qoriq-tmu";
159 reg = <0x0 0x1f80000 0x0 0x10000>;
160 interrupts = <0 23 0x4>;
161 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
162 fsl,tmu-calibration = <0x00000000 0x00000026
163 0x00000001 0x0000002d
164 0x00000002 0x00000032
165 0x00000003 0x00000039
166 0x00000004 0x0000003f
167 0x00000005 0x00000046
168 0x00000006 0x0000004d
169 0x00000007 0x00000054
170 0x00000008 0x0000005a
171 0x00000009 0x00000061
172 0x0000000a 0x0000006a
173 0x0000000b 0x00000071
175 0x00010000 0x00000025
176 0x00010001 0x0000002c
177 0x00010002 0x00000035
178 0x00010003 0x0000003d
179 0x00010004 0x00000045
180 0x00010005 0x0000004e
181 0x00010006 0x00000057
182 0x00010007 0x00000061
183 0x00010008 0x0000006b
184 0x00010009 0x00000076
186 0x00020000 0x00000029
187 0x00020001 0x00000033
188 0x00020002 0x0000003d
189 0x00020003 0x00000049
190 0x00020004 0x00000056
191 0x00020005 0x00000061
192 0x00020006 0x0000006d
194 0x00030000 0x00000021
195 0x00030001 0x0000002a
196 0x00030002 0x0000003c
197 0x00030003 0x0000004e>;
199 #thermal-sensor-cells = <1>;
202 serial0: serial@21c0500 {
203 compatible = "fsl,ns16550", "ns16550a";
204 reg = <0x0 0x21c0500 0x0 0x100>;
205 clocks = <&clockgen 4 3>;
206 interrupts = <0 32 0x4>; /* Level high type */
209 serial1: serial@21c0600 {
210 compatible = "fsl,ns16550", "ns16550a";
211 reg = <0x0 0x21c0600 0x0 0x100>;
212 clocks = <&clockgen 4 3>;
213 interrupts = <0 32 0x4>; /* Level high type */
216 serial2: serial@21d0500 {
217 compatible = "fsl,ns16550", "ns16550a";
218 reg = <0x0 0x21d0500 0x0 0x100>;
219 clocks = <&clockgen 4 3>;
220 interrupts = <0 33 0x4>; /* Level high type */
223 serial3: serial@21d0600 {
224 compatible = "fsl,ns16550", "ns16550a";
225 reg = <0x0 0x21d0600 0x0 0x100>;
226 clocks = <&clockgen 4 3>;
227 interrupts = <0 33 0x4>; /* Level high type */
230 cluster1_core0_watchdog: wdt@c000000 {
231 compatible = "arm,sp805-wdt", "arm,primecell";
232 reg = <0x0 0xc000000 0x0 0x1000>;
233 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
234 clock-names = "apb_pclk", "wdog_clk";
237 cluster1_core1_watchdog: wdt@c010000 {
238 compatible = "arm,sp805-wdt", "arm,primecell";
239 reg = <0x0 0xc010000 0x0 0x1000>;
240 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
241 clock-names = "apb_pclk", "wdog_clk";
244 cluster2_core0_watchdog: wdt@c100000 {
245 compatible = "arm,sp805-wdt", "arm,primecell";
246 reg = <0x0 0xc100000 0x0 0x1000>;
247 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
248 clock-names = "apb_pclk", "wdog_clk";
251 cluster2_core1_watchdog: wdt@c110000 {
252 compatible = "arm,sp805-wdt", "arm,primecell";
253 reg = <0x0 0xc110000 0x0 0x1000>;
254 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
255 clock-names = "apb_pclk", "wdog_clk";
258 cluster3_core0_watchdog: wdt@c200000 {
259 compatible = "arm,sp805-wdt", "arm,primecell";
260 reg = <0x0 0xc200000 0x0 0x1000>;
261 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
262 clock-names = "apb_pclk", "wdog_clk";
265 cluster3_core1_watchdog: wdt@c210000 {
266 compatible = "arm,sp805-wdt", "arm,primecell";
267 reg = <0x0 0xc210000 0x0 0x1000>;
268 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
269 clock-names = "apb_pclk", "wdog_clk";
272 cluster4_core0_watchdog: wdt@c300000 {
273 compatible = "arm,sp805-wdt", "arm,primecell";
274 reg = <0x0 0xc300000 0x0 0x1000>;
275 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
276 clock-names = "apb_pclk", "wdog_clk";
279 cluster4_core1_watchdog: wdt@c310000 {
280 compatible = "arm,sp805-wdt", "arm,primecell";
281 reg = <0x0 0xc310000 0x0 0x1000>;
282 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
283 clock-names = "apb_pclk", "wdog_clk";
286 crypto: crypto@8000000 {
287 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
289 #address-cells = <1>;
291 ranges = <0x0 0x00 0x8000000 0x100000>;
292 reg = <0x00 0x8000000 0x0 0x100000>;
293 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
297 compatible = "fsl,sec-v5.0-job-ring",
298 "fsl,sec-v4.0-job-ring";
299 reg = <0x10000 0x10000>;
300 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
304 compatible = "fsl,sec-v5.0-job-ring",
305 "fsl,sec-v4.0-job-ring";
306 reg = <0x20000 0x10000>;
307 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
311 compatible = "fsl,sec-v5.0-job-ring",
312 "fsl,sec-v4.0-job-ring";
313 reg = <0x30000 0x10000>;
314 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
318 compatible = "fsl,sec-v5.0-job-ring",
319 "fsl,sec-v4.0-job-ring";
320 reg = <0x40000 0x10000>;
321 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
326 compatible = "fsl,dpaa2-console";
327 reg = <0x00000000 0x08340020 0 0x2>;
331 compatible = "fsl,dpaa2-ptp";
332 reg = <0x0 0x8b95000 0x0 0x100>;
333 clocks = <&clockgen 4 1>;
338 fsl_mc: fsl-mc@80c000000 {
339 compatible = "fsl,qoriq-mc";
340 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
341 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
343 iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
345 #address-cells = <3>;
349 * Region type 0x0 - MC portals
350 * Region type 0x1 - QBMAN portals
352 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
353 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
356 * Define the maximum number of MACs present on the SoC.
359 #address-cells = <1>;
363 compatible = "fsl,qoriq-mc-dpmac";
368 compatible = "fsl,qoriq-mc-dpmac";
373 compatible = "fsl,qoriq-mc-dpmac";
378 compatible = "fsl,qoriq-mc-dpmac";
383 compatible = "fsl,qoriq-mc-dpmac";
388 compatible = "fsl,qoriq-mc-dpmac";
393 compatible = "fsl,qoriq-mc-dpmac";
398 compatible = "fsl,qoriq-mc-dpmac";
403 compatible = "fsl,qoriq-mc-dpmac";
408 compatible = "fsl,qoriq-mc-dpmac";
413 compatible = "fsl,qoriq-mc-dpmac";
418 compatible = "fsl,qoriq-mc-dpmac";
423 compatible = "fsl,qoriq-mc-dpmac";
428 compatible = "fsl,qoriq-mc-dpmac";
433 compatible = "fsl,qoriq-mc-dpmac";
438 compatible = "fsl,qoriq-mc-dpmac";
444 smmu: iommu@5000000 {
445 compatible = "arm,mmu-500";
446 reg = <0 0x5000000 0 0x800000>;
447 #global-interrupts = <12>;
449 stream-match-mask = <0x7C00>;
451 interrupts = <0 13 4>, /* global secure fault */
452 <0 14 4>, /* combined secure interrupt */
453 <0 15 4>, /* global non-secure fault */
454 <0 16 4>, /* combined non-secure interrupt */
455 /* performance counter interrupts 0-7 */
456 <0 211 4>, <0 212 4>,
457 <0 213 4>, <0 214 4>,
458 <0 215 4>, <0 216 4>,
459 <0 217 4>, <0 218 4>,
460 /* per context interrupt, 64 interrupts */
461 <0 146 4>, <0 147 4>,
462 <0 148 4>, <0 149 4>,
463 <0 150 4>, <0 151 4>,
464 <0 152 4>, <0 153 4>,
465 <0 154 4>, <0 155 4>,
466 <0 156 4>, <0 157 4>,
467 <0 158 4>, <0 159 4>,
468 <0 160 4>, <0 161 4>,
469 <0 162 4>, <0 163 4>,
470 <0 164 4>, <0 165 4>,
471 <0 166 4>, <0 167 4>,
472 <0 168 4>, <0 169 4>,
473 <0 170 4>, <0 171 4>,
474 <0 172 4>, <0 173 4>,
475 <0 174 4>, <0 175 4>,
476 <0 176 4>, <0 177 4>,
477 <0 178 4>, <0 179 4>,
478 <0 180 4>, <0 181 4>,
479 <0 182 4>, <0 183 4>,
480 <0 184 4>, <0 185 4>,
481 <0 186 4>, <0 187 4>,
482 <0 188 4>, <0 189 4>,
483 <0 190 4>, <0 191 4>,
484 <0 192 4>, <0 193 4>,
485 <0 194 4>, <0 195 4>,
486 <0 196 4>, <0 197 4>,
487 <0 198 4>, <0 199 4>,
488 <0 200 4>, <0 201 4>,
489 <0 202 4>, <0 203 4>,
490 <0 204 4>, <0 205 4>,
491 <0 206 4>, <0 207 4>,
492 <0 208 4>, <0 209 4>;
497 compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
498 #address-cells = <1>;
500 reg = <0x0 0x2100000 0x0 0x10000>;
501 interrupts = <0 26 0x4>; /* Level high type */
502 clocks = <&clockgen 4 3>;
503 clock-names = "dspi";
504 spi-num-chipselects = <5>;
508 esdhc: esdhc@2140000 {
510 compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
511 reg = <0x0 0x2140000 0x0 0x10000>;
512 interrupts = <0 28 0x4>; /* Level high type */
513 clocks = <&clockgen 4 1>;
514 voltage-ranges = <1800 1800 3300 3300>;
520 gpio0: gpio@2300000 {
521 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
522 reg = <0x0 0x2300000 0x0 0x10000>;
523 interrupts = <0 36 0x4>; /* Level high type */
527 interrupt-controller;
528 #interrupt-cells = <2>;
531 gpio1: gpio@2310000 {
532 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
533 reg = <0x0 0x2310000 0x0 0x10000>;
534 interrupts = <0 36 0x4>; /* Level high type */
538 interrupt-controller;
539 #interrupt-cells = <2>;
542 gpio2: gpio@2320000 {
543 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
544 reg = <0x0 0x2320000 0x0 0x10000>;
545 interrupts = <0 37 0x4>; /* Level high type */
549 interrupt-controller;
550 #interrupt-cells = <2>;
553 gpio3: gpio@2330000 {
554 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
555 reg = <0x0 0x2330000 0x0 0x10000>;
556 interrupts = <0 37 0x4>; /* Level high type */
560 interrupt-controller;
561 #interrupt-cells = <2>;
566 compatible = "fsl,vf610-i2c";
567 #address-cells = <1>;
569 reg = <0x0 0x2000000 0x0 0x10000>;
570 interrupts = <0 34 0x4>; /* Level high type */
572 clocks = <&clockgen 4 3>;
577 compatible = "fsl,vf610-i2c";
578 #address-cells = <1>;
580 reg = <0x0 0x2010000 0x0 0x10000>;
581 interrupts = <0 34 0x4>; /* Level high type */
583 clocks = <&clockgen 4 3>;
588 compatible = "fsl,vf610-i2c";
589 #address-cells = <1>;
591 reg = <0x0 0x2020000 0x0 0x10000>;
592 interrupts = <0 35 0x4>; /* Level high type */
594 clocks = <&clockgen 4 3>;
599 compatible = "fsl,vf610-i2c";
600 #address-cells = <1>;
602 reg = <0x0 0x2030000 0x0 0x10000>;
603 interrupts = <0 35 0x4>; /* Level high type */
605 clocks = <&clockgen 4 3>;
609 compatible = "fsl,ifc", "simple-bus";
610 reg = <0x0 0x2240000 0x0 0x20000>;
611 interrupts = <0 21 0x4>; /* Level high type */
613 #address-cells = <2>;
616 ranges = <0 0 0x5 0x80000000 0x08000000
617 2 0 0x5 0x30000000 0x00010000
618 3 0 0x5 0x20000000 0x00010000>;
622 compatible = "fsl,ls2080a-qspi";
623 #address-cells = <1>;
625 reg = <0x0 0x20c0000 0x0 0x10000>,
626 <0x0 0x20000000 0x0 0x10000000>;
627 reg-names = "QuadSPI", "QuadSPI-memory";
628 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
630 clock-names = "qspi_en", "qspi";
634 pcie1: pcie@3400000 {
635 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
636 reg-names = "regs", "config";
637 interrupts = <0 108 0x4>; /* Level high type */
638 interrupt-names = "intr";
639 #address-cells = <3>;
644 bus-range = <0x0 0xff>;
646 #interrupt-cells = <1>;
647 interrupt-map-mask = <0 0 0 7>;
648 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
649 <0000 0 0 2 &gic 0 0 0 110 4>,
650 <0000 0 0 3 &gic 0 0 0 111 4>,
651 <0000 0 0 4 &gic 0 0 0 112 4>;
652 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
656 pcie2: pcie@3500000 {
657 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
658 reg-names = "regs", "config";
659 interrupts = <0 113 0x4>; /* Level high type */
660 interrupt-names = "intr";
661 #address-cells = <3>;
666 bus-range = <0x0 0xff>;
668 #interrupt-cells = <1>;
669 interrupt-map-mask = <0 0 0 7>;
670 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
671 <0000 0 0 2 &gic 0 0 0 115 4>,
672 <0000 0 0 3 &gic 0 0 0 116 4>,
673 <0000 0 0 4 &gic 0 0 0 117 4>;
674 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
678 pcie3: pcie@3600000 {
679 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
680 reg-names = "regs", "config";
681 interrupts = <0 118 0x4>; /* Level high type */
682 interrupt-names = "intr";
683 #address-cells = <3>;
687 num-viewport = <256>;
688 bus-range = <0x0 0xff>;
690 #interrupt-cells = <1>;
691 interrupt-map-mask = <0 0 0 7>;
692 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
693 <0000 0 0 2 &gic 0 0 0 120 4>,
694 <0000 0 0 3 &gic 0 0 0 121 4>,
695 <0000 0 0 4 &gic 0 0 0 122 4>;
696 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
700 pcie4: pcie@3700000 {
701 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
702 reg-names = "regs", "config";
703 interrupts = <0 123 0x4>; /* Level high type */
704 interrupt-names = "intr";
705 #address-cells = <3>;
710 bus-range = <0x0 0xff>;
712 #interrupt-cells = <1>;
713 interrupt-map-mask = <0 0 0 7>;
714 interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
715 <0000 0 0 2 &gic 0 0 0 125 4>,
716 <0000 0 0 3 &gic 0 0 0 126 4>,
717 <0000 0 0 4 &gic 0 0 0 127 4>;
718 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
722 sata0: sata@3200000 {
724 compatible = "fsl,ls2080a-ahci";
725 reg = <0x0 0x3200000 0x0 0x10000>;
726 interrupts = <0 133 0x4>; /* Level high type */
727 clocks = <&clockgen 4 3>;
731 sata1: sata@3210000 {
733 compatible = "fsl,ls2080a-ahci";
734 reg = <0x0 0x3210000 0x0 0x10000>;
735 interrupts = <0 136 0x4>; /* Level high type */
736 clocks = <&clockgen 4 3>;
742 compatible = "snps,dwc3";
743 reg = <0x0 0x3100000 0x0 0x10000>;
744 interrupts = <0 80 0x4>; /* Level high type */
746 snps,quirk-frame-length-adjustment = <0x20>;
747 snps,dis_rxdet_inp3_quirk;
748 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
753 compatible = "snps,dwc3";
754 reg = <0x0 0x3110000 0x0 0x10000>;
755 interrupts = <0 81 0x4>; /* Level high type */
757 snps,quirk-frame-length-adjustment = <0x20>;
758 snps,dis_rxdet_inp3_quirk;
759 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
763 compatible = "arm,ccn-504";
764 reg = <0x0 0x04000000 0x0 0x01000000>;
765 interrupts = <0 12 4>;
768 rcpm: power-controller@1e34040 {
769 compatible = "fsl,ls208xa-rcpm", "fsl,qoriq-rcpm-2.1+";
770 reg = <0x0 0x1e34040 0x0 0x18>;
771 #fsl,rcpm-wakeup-cells = <6>;
774 ftm_alarm0: timer@2800000 {
775 compatible = "fsl,ls208xa-ftm-alarm";
776 reg = <0x0 0x2800000 0x0 0x10000>;
777 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
778 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
782 ddr1: memory-controller@1080000 {
783 compatible = "fsl,qoriq-memory-controller";
784 reg = <0x0 0x1080000 0x0 0x1000>;
785 interrupts = <0 17 0x4>;
789 ddr2: memory-controller@1090000 {
790 compatible = "fsl,qoriq-memory-controller";
791 reg = <0x0 0x1090000 0x0 0x1000>;
792 interrupts = <0 18 0x4>;
798 compatible = "linaro,optee-tz";