2 * Device Tree Include file for Freescale Layerscape-2088A family SoC.
4 * Copyright 2016 Freescale Semiconductor, Inc.
7 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
9 * This file is dual-licensed: you can use it either under the terms
10 * of the GPLv2 or the X11 license, at your option. Note that this dual
11 * licensing only applies to this file, and not this project as a
14 * a) This library is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of the
17 * License, or (at your option) any later version.
19 * This library is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
48 #include "fsl-ls208xa.dtsi"
53 compatible = "arm,cortex-a72";
55 clocks = <&clockgen 1 0>;
56 cpu-idle-states = <&CPU_PW20>;
57 next-level-cache = <&cluster0_l2>;
63 compatible = "arm,cortex-a72";
65 clocks = <&clockgen 1 0>;
66 cpu-idle-states = <&CPU_PW20>;
67 next-level-cache = <&cluster0_l2>;
72 compatible = "arm,cortex-a72";
74 clocks = <&clockgen 1 1>;
75 cpu-idle-states = <&CPU_PW20>;
76 next-level-cache = <&cluster1_l2>;
82 compatible = "arm,cortex-a72";
84 clocks = <&clockgen 1 1>;
85 cpu-idle-states = <&CPU_PW20>;
86 next-level-cache = <&cluster1_l2>;
91 compatible = "arm,cortex-a72";
93 clocks = <&clockgen 1 2>;
94 next-level-cache = <&cluster2_l2>;
95 cpu-idle-states = <&CPU_PW20>;
101 compatible = "arm,cortex-a72";
103 clocks = <&clockgen 1 2>;
104 cpu-idle-states = <&CPU_PW20>;
105 next-level-cache = <&cluster2_l2>;
110 compatible = "arm,cortex-a72";
112 clocks = <&clockgen 1 3>;
113 cpu-idle-states = <&CPU_PW20>;
114 next-level-cache = <&cluster3_l2>;
115 #cooling-cells = <2>;
120 compatible = "arm,cortex-a72";
122 clocks = <&clockgen 1 3>;
123 cpu-idle-states = <&CPU_PW20>;
124 next-level-cache = <&cluster3_l2>;
127 cluster0_l2: l2-cache0 {
128 compatible = "cache";
131 cluster1_l2: l2-cache1 {
132 compatible = "cache";
135 cluster2_l2: l2-cache2 {
136 compatible = "cache";
139 cluster3_l2: l2-cache3 {
140 compatible = "cache";
144 compatible = "arm,idle-state";
145 idle-state-name = "PW20";
146 arm,psci-suspend-param = <0x00010000>;
147 entry-latency-us = <2000>;
148 exit-latency-us = <2000>;
149 min-residency-us = <6000>;
154 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
155 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
157 ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000
158 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>;
162 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
163 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
165 ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000
166 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>;
170 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
171 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
173 ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000
174 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>;
178 reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
179 0x38 0x00000000 0x0 0x00002000>; /* configuration space */
181 ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000
182 0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>;